1 files changed, 19 insertions, 32 deletions
diff --git a/serdes/serdes_tx.v b/serdes/serdes_tx.v
index fa4abe5df..2e5e3bd80 100644
--- a/serdes/serdes_tx.v
+++ b/serdes/serdes_tx.v
@@ -33,11 +33,9 @@ module serdes_tx
      
      // TX Stream Interface
      input [31:0] rd_dat_i,
-     output rd_read_o,
-     output rd_done_o,
-     output rd_error_o,
-     input rd_sop_i,
-     input rd_eop_i,
+     input [3:0] rd_flags_i,
+     output rd_ready_o,
+     input rd_ready_i,
 
      // Flow control interface
      input inhibit_tx,
@@ -79,36 +77,25 @@ module serdes_tx
    reg [3:0]   wait_count;
    
    // Internal FIFO, size 9 is 2K, size 10 is 4K bytes
-   wire        sop_o, eop_o, write, full, read, empty;
+   wire        sop_o, eop_o;
    wire [31:0] data_o;
-   reg 	       xfer_active;
-   
-   cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
-     (.clk(clk),.rst(rst),.clear(0),
-      .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
-      .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty),
+
+   wire        rd_sop_i  = rd_flags_i[0];
+   wire        rd_eop_i  = rd_flags_i[1];
+   wire [1:0]  rd_occ_i = rd_flags_i[3:2];  // Unused
+
+   wire        have_data, empty, read;
+   fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
+     (.clk(clk),.reset(rst),.clear(0),
+      .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o),
+      .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data),
       .space(), .occupied(fifo_occupied) );
-   assign      fifo_full = full;
-   assign      fifo_empty = empty;
-   
-   // Buffer interface to internal FIFO
-   always @(posedge clk)
-     if(rst)
-       xfer_active <= 0;
-     else if(rd_eop_i & ~full)  // In case we can't store last line right away
-       xfer_active <= 0;
-     else if(rd_sop_i)
-       xfer_active <= 1;
-   
-   assign      write = xfer_active & ~full;
-   
-   assign      rd_read_o = write;
-   assign      rd_done_o = 0;        // Always take everything we're given
-   assign      rd_error_o = 0;       // No chance for errors anticipated
-   
    
-   // FIXME Implement flow control
+   assign fifo_full   = ~rd_ready_o;
+   assign empty       = ~have_data;
+   assign fifo_empty  = empty;
    
+   // FIXME Implement flow control   
    reg [15:0]  second_word;
    reg [33:0]  pipeline;
    
@@ -193,7 +180,7 @@ module serdes_tx
    
    CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC);
 
-   assign debug = { 26'd0, full, empty, xfer_active, state[2:0] };
+   assign debug = { 28'd0, state[2:0] };
    
 endmodule // serdes_tx