diff options
Diffstat (limited to 'sdr_lib')
| -rw-r--r-- | sdr_lib/rx_control.v | 46 | ||||
| -rw-r--r-- | sdr_lib/tx_control.v | 58 |
2 files changed, 36 insertions, 68 deletions
diff --git a/sdr_lib/rx_control.v b/sdr_lib/rx_control.v index d41a28bcf..ae821e822 100644 --- a/sdr_lib/rx_control.v +++ b/sdr_lib/rx_control.v @@ -9,15 +9,12 @@ module rx_control input [31:0] master_time, output overrun, - // To Buffer interface + // To FIFO interface of Buffer Pool output [31:0] wr_dat_o, - output wr_write_o, - output wr_done_o, - output wr_error_o, - + output [3:0] wr_flags_o, input wr_ready_i, - input wr_full_i, - + output wr_ready_o, + // From DSP Core input [31:0] sample, output run, @@ -68,35 +65,10 @@ module rx_control // Buffer interface to internal FIFO wire write, full, read, empty; wire sop_o, eop_o; - - reg xfer_state; - localparam XFER_IDLE = 1'b0; - localparam XFER_GO = 1'b1; - - always @(posedge clk) - if(rst) - xfer_state <= XFER_IDLE; - else - if(clear_overrun) - xfer_state <= XFER_IDLE; - else - case(xfer_state) - XFER_IDLE : - if(wr_ready_i) - xfer_state <= XFER_GO; - XFER_GO : - if((eop_o | wr_full_i) & wr_write_o) - xfer_state <= XFER_IDLE; - default : - xfer_state <= XFER_IDLE; - endcase // case(xfer_state) + assign wr_flags_o = {2'b00, eop_o, sop_o}; + assign wr_ready_o = ~empty; + assign read = wr_ready_i & wr_ready_o; - assign wr_write_o = (xfer_state == XFER_GO) & ~empty; - assign wr_done_o = (eop_o & wr_write_o); - assign wr_error_o = 0; // FIXME add check here for eop if we have wr_full_i once we have IBS - - assign read = wr_write_o | (~empty & ~sop_o); // FIXME what if there is junk between packets? - wire [33:0] fifo_line; // Internal FIFO, size 9 is 2K, size 10 is 4K @@ -206,8 +178,8 @@ module rx_control ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) & ~empty_ctrl; - assign debug_rx = { 6'd0,send_imm,chain, - wr_write_o, wr_done_o, wr_ready_i, wr_full_i,xfer_state,eop_o, sop_o, run, + assign debug_rx = { 8'd0, + 1'd0, send_imm, chain, wr_ready_i,wr_ready_o, eop_o, sop_o, run, write,full,read,empty,write_ctrl,full_ctrl,read_ctrl,empty_ctrl, sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] }; endmodule // rx_control diff --git a/sdr_lib/tx_control.v b/sdr_lib/tx_control.v index 0c4ab1a52..8766afd8b 100644 --- a/sdr_lib/tx_control.v +++ b/sdr_lib/tx_control.v @@ -9,13 +9,11 @@ module tx_control input [31:0] master_time, output underrun, - // To Buffer interface + // To FIFO interface from Buffer Pool input [31:0] rd_dat_i, - input rd_sop_i, - input rd_eop_i, - output rd_read_o, - output rd_done_o, - output rd_error_o, + input [3:0] rd_flags_i, + input rd_ready_i, + output rd_ready_o, // To DSP Core output [31:0] sample, @@ -31,6 +29,10 @@ module tx_control output [31:0] debug ); + wire rd_sop_i = rd_flags_i[0]; // Unused + wire rd_eop_i = rd_flags_i[1]; + wire rd_occ_i = rd_flags_i[3:2]; // Unused, should always be 0 + // Buffer interface to internal FIFO wire write_data, write_ctrl, full_data, full_ctrl; wire read_data, read_ctrl, empty_data, empty_ctrl; @@ -39,57 +41,51 @@ module tx_control reg [2:0] held_flags; localparam XFER_IDLE = 0; - localparam XFER_1 = 1; - localparam XFER_2 = 2; - localparam XFER_DATA = 3; + localparam XFER_CTRL = 1; + localparam XFER_PKT = 2; + // Add underrun state? always @(posedge clk) if(rst) xfer_state <= XFER_IDLE; + else if(clear_state) + xfer_state <= XFER_IDLE; else - if(clear_state) - xfer_state <= XFER_IDLE; - else + if(rd_ready_i & rd_ready_o) case(xfer_state) XFER_IDLE : - if(rd_sop_i) - xfer_state <= XFER_1; - XFER_1 : begin - xfer_state <= XFER_2; + xfer_state <= XFER_CTRL; held_flags <= rd_dat_i[2:0]; end - XFER_2 : - if(~full_ctrl) - xfer_state <= XFER_DATA; - XFER_DATA : - if(rd_eop_i & ~full_data) + XFER_CTRL : + xfer_state <= XFER_PKT; + XFER_PKT : + if(rd_eop_i) xfer_state <= XFER_IDLE; endcase // case(xfer_state) - assign write_data = (xfer_state == XFER_DATA) & ~full_data; - assign write_ctrl = (xfer_state == XFER_2) & ~full_ctrl; + assign write_data = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o; + assign write_ctrl = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o; - assign rd_read_o = (xfer_state == XFER_1) | write_data | write_ctrl; - assign rd_done_o = 0; // Always take everything we're given - assign rd_error_o = 0; // Should we indicate overruns here? + assign rd_ready_o = ~full_data & ~full_ctrl; wire [31:0] data_o; - wire sop_o, eop_o, eob, sob, send_imm; + wire eop_o, eob, sob, send_imm; wire [31:0] sendtime; wire [4:0] occ_ctrl; - cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) txctrlfifo + cascadefifo2 #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo (.clk(clk),.rst(rst),.clear(clear_state), - .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write_data), .full(full_data), - .dataout({sop_o,eop_o,data_o}), .read(read_data), .empty(empty_data), + .datain({rd_eop_i,rd_dat_i[31:0]}), .write(write_data), .full(full_data), + .dataout({eop_o,data_o}), .read(read_data), .empty(empty_data), .space(), .occupied(fifo_occupied) ); assign fifo_full = full_data; assign fifo_empty = empty_data; shortfifo #(.WIDTH(35)) ctrlfifo (.clk(clk),.rst(rst),.clear(clear_state), - .datain({held_flags[2:0],rd_dat_i}), .write(write_ctrl), .full(full_ctrl), + .datain({held_flags[2:0],rd_dat_i[31:0]}), .write(write_ctrl), .full(full_ctrl), .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), .empty(empty_ctrl), .space(), .occupied(occ_ctrl) ); |