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-rw-r--r--sdr_lib/ram16.v17
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diff --git a/sdr_lib/ram16.v b/sdr_lib/ram16.v
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+
+
+module ram16 (input clock, input write,
+ input [3:0] wr_addr, input [15:0] wr_data,
+ input [3:0] rd_addr, output reg [15:0] rd_data);
+
+ reg [15:0] ram_array [0:15];
+
+ always @(posedge clock)
+ rd_data <= #1 ram_array[rd_addr];
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+endmodule // ram16
+