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-rw-r--r--mpm/python/usrp_mpm/dboard_manager/magnesium.py67
-rw-r--r--mpm/python/usrp_mpm/periph_manager/base.py6
-rw-r--r--mpm/python/usrp_mpm/sys_utils/dtoverlay.py2
3 files changed, 42 insertions, 33 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py
index df34c996d..23bf1d24c 100644
--- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py
+++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py
@@ -721,53 +721,58 @@ class Magnesium(DboardManagerBase):
jesdcore.set_drp_target('qpll', 0)
# QPLL_CONFIG is spread across two regs: 0x32 (dedicated) and 0x33 (shared)
reg_x32 = QPLL_CFG & 0xFFFF # [16:0] -> [16:0]
- reg_x33 = jesdcore.drp_access(rd = True, addr = 0x33)
+ reg_x33 = jesdcore.drp_access(rd=True, addr=0x33)
reg_x33 = (reg_x33 & 0xF800) | ((QPLL_CFG >> 16) & 0x7FF) # [26:16] -> [11:0]
- jesdcore.drp_access(rd = False, addr = 0x32, wr_data = reg_x32)
- jesdcore.drp_access(rd = False, addr = 0x33, wr_data = reg_x33)
+ jesdcore.drp_access(rd=False, addr=0x32, wr_data=reg_x32)
+ jesdcore.drp_access(rd=False, addr=0x33, wr_data=reg_x33)
# QPLL_FBDIV is shared with other settings in reg 0x36
- reg_x36 = jesdcore.drp_access(rd = True, addr = 0x36)
+ reg_x36 = jesdcore.drp_access(rd=True, addr=0x36)
reg_x36 = (reg_x36 & 0xFC00) | (QPLL_FBDIV & 0x3FF) # in bits [9:0]
- jesdcore.drp_access(rd = False, addr = 0x36, wr_data = reg_x36)
+ jesdcore.drp_access(rd=False, addr=0x36, wr_data=reg_x36)
# Run the QPLL reset sequence and prep the MGTs for modification.
jesdcore.init()
# 3-4) And the 4 MGTs second
if not skip_drp:
- self.log.trace("Changing MGT settings to support {} Gbps".format(new_rate/1e9))
- for lane in range(0,4):
+ self.log.trace("Changing MGT settings to support {} Gbps"
+ .format(new_rate/1e9))
+ for lane in range(4):
jesdcore.set_drp_target('mgt', lane)
# MGT_PMA_RSV is split over 0x99 (LSBs) and 0x9A
reg_x99 = MGT_PMA_RSV & 0xFFFF
- reg_x9A = (MGT_PMA_RSV >> 16) & 0xFFFF
- jesdcore.drp_access(rd = False, addr = 0x99, wr_data = reg_x99)
- jesdcore.drp_access(rd = False, addr = 0x9A, wr_data = reg_x9A)
- # MGT_RX_CLK25_DIV is embedded with others in 0x11. The encoding for
- # the DRP register value is one less than the desired value.
- reg_x11 = jesdcore.drp_access(rd = True, addr = 0x11)
- reg_x11 = (reg_x11 & 0xF83F) | ((MGT_RX_CLK25_DIV-1 & 0x1F) << 6) # [10:6]
- jesdcore.drp_access(rd = False, addr = 0x11, wr_data = reg_x11)
- # MGT_TX_CLK25_DIV is embedded with others in 0x6A. The encoding for
- # the DRP register value is one less than the desired value.
- reg_x6A = jesdcore.drp_access(rd = True, addr = 0x6A)
- reg_x6A = (reg_x6A & 0xFFE0) | (MGT_TX_CLK25_DIV-1 & 0x1F) # [4:0]
- jesdcore.drp_access(rd = False, addr = 0x6A, wr_data = reg_x6A)
+ reg_x9a = (MGT_PMA_RSV >> 16) & 0xFFFF
+ jesdcore.drp_access(rd=False, addr=0x99, wr_data=reg_x99)
+ jesdcore.drp_access(rd=False, addr=0x9A, wr_data=reg_x9a)
+ # MGT_RX_CLK25_DIV is embedded with others in 0x11. The
+ # encoding for the DRP register value is one less than the
+ # desired value.
+ reg_x11 = jesdcore.drp_access(rd=True, addr=0x11)
+ reg_x11 = (reg_x11 & 0xF83F) | \
+ ((MGT_RX_CLK25_DIV-1 & 0x1F) << 6) # [10:6]
+ jesdcore.drp_access(rd=False, addr=0x11, wr_data=reg_x11)
+ # MGT_TX_CLK25_DIV is embedded with others in 0x6A. The
+ # encoding for the DRP register value is one less than the
+ # desired value.
+ reg_x6a = jesdcore.drp_access(rd=True, addr=0x6A)
+ reg_x6a = (reg_x6a & 0xFFE0) | (MGT_TX_CLK25_DIV-1 & 0x1F) # [4:0]
+ jesdcore.drp_access(rd=False, addr=0x6A, wr_data=reg_x6a)
# MGT_RXCDR_CFG is split over 0xA8 (LSBs) through 0xAD
- RXCDR_REG_BASE = 0xA8
- for reg_num in range(0, 6):
- reg_addr = RXCDR_REG_BASE + reg_num
+ for reg_num, reg_addr in enumerate(range(0xA8, 0xAE)):
reg_data = (MGT_RXCDR_CFG >> 16*reg_num) & 0xFFFF
- jesdcore.drp_access(rd = False, addr = reg_addr, wr_data = reg_data)
- # MGT_RXOUT_DIV and MGT_TXOUT_DIV are embedded together in 0x88. The
- # encoding for the DRP register value is drp_val=log2(attribute)
- reg_x88 = (int(math.log(MGT_RXOUT_DIV,2)) & 0x7) | \
- ((int(math.log(MGT_TXOUT_DIV,2)) & 0x7) << 4) # RX=[2:0] TX=[6:4]
- jesdcore.drp_access(rd = False, addr = 0x88, wr_data = reg_x88)
- self.log.trace("GTX settings changed to support {} Gbps".format(new_rate/1e9))
+ jesdcore.drp_access(rd=False, addr=reg_addr, wr_data=reg_data)
+ # MGT_RXOUT_DIV and MGT_TXOUT_DIV are embedded together in
+ # 0x88. The encoding for the DRP register value is
+ # drp_val=log2(attribute)
+ reg_x88 = (int(math.log(MGT_RXOUT_DIV, 2)) & 0x7) | \
+ ((int(math.log(MGT_TXOUT_DIV, 2)) & 0x7) << 4) # RX=[2:0] TX=[6:4]
+ jesdcore.drp_access(rd=False, addr=0x88, wr_data=reg_x88)
+ self.log.trace("GTX settings changed to support {} Gbps"
+ .format(new_rate/1e9))
jesdcore.disable_drp_target()
- self.log.trace("JESD204b Lane Rate set to {} Gbps!".format(new_rate/1e9))
+ self.log.trace("JESD204b Lane Rate set to {} Gbps!"
+ .format(new_rate/1e9))
self.current_jesd_rate = new_rate
return
diff --git a/mpm/python/usrp_mpm/periph_manager/base.py b/mpm/python/usrp_mpm/periph_manager/base.py
index 8fec893f7..d1ae84df6 100644
--- a/mpm/python/usrp_mpm/periph_manager/base.py
+++ b/mpm/python/usrp_mpm/periph_manager/base.py
@@ -10,8 +10,8 @@ Mboard implementation base class
from __future__ import print_function
import os
from hashlib import md5
-from concurrent import futures
from time import sleep
+from concurrent import futures
from builtins import str
from builtins import range
from builtins import object
@@ -571,6 +571,8 @@ class PeriphManagerBase(object):
and is thus defined in the individual device classes.
"""
self.log.warn("Called set_mb_eeprom(), but not implemented!")
+ self.log.debug("Skipping writing EEPROM keys: {}"
+ .format(list(eeprom_vals.keys())))
raise NotImplementedError
def get_db_eeprom(self, dboard_idx):
@@ -599,6 +601,8 @@ class PeriphManagerBase(object):
"""
self.log.warn("Attempted to write dboard `%d' EEPROM, but function " \
"is not implemented.", dboard_idx)
+ self.log.debug("Skipping writing EEPROM keys: {}"
+ .format(list(eeprom_data.keys())))
raise NotImplementedError
#######################################################################
diff --git a/mpm/python/usrp_mpm/sys_utils/dtoverlay.py b/mpm/python/usrp_mpm/sys_utils/dtoverlay.py
index 4dcd43bb9..30f7ae4a0 100644
--- a/mpm/python/usrp_mpm/sys_utils/dtoverlay.py
+++ b/mpm/python/usrp_mpm/sys_utils/dtoverlay.py
@@ -62,7 +62,7 @@ def list_overlays(applied_only=False):
or get_overlay_attrs(overlay_name).get('status') == 'applied'
}
-def list_available_overlays(path):
+def list_available_overlays(path=None):
"""
List available overlay files (dtbo)
"""
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 15:55:27 +0000