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-rw-r--r--mpm/python/usrp_mpm/periph_manager/e31x.py2
-rw-r--r--mpm/python/usrp_mpm/periph_manager/e320.py2
-rw-r--r--mpm/python/usrp_mpm/periph_manager/n3xx.py2
3 files changed, 3 insertions, 3 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e31x.py b/mpm/python/usrp_mpm/periph_manager/e31x.py
index 8043fc704..11f65dd17 100644
--- a/mpm/python/usrp_mpm/periph_manager/e31x.py
+++ b/mpm/python/usrp_mpm/periph_manager/e31x.py
@@ -31,7 +31,7 @@ E310_DEFAULT_CLOCK_SOURCE = 'internal'
E310_DEFAULT_TIME_SOURCE = 'internal'
E310_DEFAULT_ENABLE_FPGPIO = True
E310_DEFAULT_DONT_RELOAD_FPGA = False # False means idle image gets reloaded
-E310_FPGA_COMPAT = (5, 0)
+E310_FPGA_COMPAT = (6, 0)
E310_DBOARD_SLOT_IDX = 0
E310_GPIO_SRC_PS = "PS"
# We use the index positions of RFA and RFB to map between name and radio index
diff --git a/mpm/python/usrp_mpm/periph_manager/e320.py b/mpm/python/usrp_mpm/periph_manager/e320.py
index dc91b20d9..770b449b5 100644
--- a/mpm/python/usrp_mpm/periph_manager/e320.py
+++ b/mpm/python/usrp_mpm/periph_manager/e320.py
@@ -32,7 +32,7 @@ E320_DEFAULT_CLOCK_SOURCE = 'internal'
E320_DEFAULT_TIME_SOURCE = 'internal'
E320_DEFAULT_ENABLE_GPS = True
E320_DEFAULT_ENABLE_FPGPIO = True
-E320_FPGA_COMPAT = (5, 0)
+E320_FPGA_COMPAT = (6, 0)
E320_MONITOR_THREAD_INTERVAL = 1.0 # seconds
E320_DBOARD_SLOT_IDX = 0
E320_GPIO_BANKS = ["FP0",]
diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py
index e73fb81db..7a9f61df7 100644
--- a/mpm/python/usrp_mpm/periph_manager/n3xx.py
+++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py
@@ -41,7 +41,7 @@ N3XX_DEFAULT_ENABLE_PPS_EXPORT = True
N32X_DEFAULT_QSFP_RATE_PRESET = 'Ethernet'
N32X_DEFAULT_QSFP_DRIVER_PRESET = 'Optical'
N32X_QSFP_I2C_LABEL = 'qsfp-i2c'
-N3XX_FPGA_COMPAT = (7, 0)
+N3XX_FPGA_COMPAT = (8, 0)
N3XX_MONITOR_THREAD_INTERVAL = 1.0 # seconds
N3XX_BUS_CLK = 200e6
N3XX_GPIO_BANKS = ["FP0",]