diff options
Diffstat (limited to 'mpm')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx.py | 4 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py index 08ddf6e9e..04014f5b2 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py @@ -35,7 +35,7 @@ N3XX_DEFAULT_TIME_SOURCE = 'internal' N3XX_DEFAULT_ENABLE_GPS = True N3XX_DEFAULT_ENABLE_FPGPIO = True N3XX_DEFAULT_ENABLE_PPS_EXPORT = True -N3XX_FPGA_COMPAT = (5, 2) +N3XX_FPGA_COMPAT = (5, 3) N3XX_MONITOR_THREAD_INTERVAL = 1.0 # seconds # Import daughterboard PIDs from their respective classes @@ -122,7 +122,6 @@ class n3xx(ZynqComponents, PeriphManagerBase): 'temp': 'get_temp_sensor', 'fan': 'get_fan_sensor', } - crossbar_base_port = 3 # It's 3 because 0,1,2 are SFP,SFP,DMA dboard_eeprom_addr = "e0004000.i2c" dboard_eeprom_offset = 0 dboard_eeprom_max_len = 64 @@ -320,6 +319,7 @@ class n3xx(ZynqComponents, PeriphManagerBase): self.mboard_regs_control.get_build_timestamp() self._check_fpga_compat() self._update_fpga_type() + self.crossbar_base_port = self.mboard_regs_control.get_xbar_baseport() # Init clocking self.enable_ref_clock(enable=True) self._ext_clock_freq = None diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py index 0370f6e67..0bfae94e1 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py @@ -176,6 +176,7 @@ class MboardRegsControl(object): MB_SFP1_INFO = 0x002C MB_GPIO_MASTER = 0x0030 MB_GPIO_RADIO_SRC = 0x0034 + MB_XBAR_BASEPORT = 0x0038 # Bitfield locations for the MB_CLOCK_CTRL register. MB_CLOCK_CTRL_PPS_SEL_INT_10 = 0 # pps_sel is one-hot encoded! @@ -412,3 +413,7 @@ class MboardRegsControl(object): .format(sfp0_type, sfp1_type)) return "" + def get_xbar_baseport(self): + "Get the RFNoC crossbar base port" + with self.regs: + return self.peek32(self.MB_XBAR_BASEPORT) |