diff options
Diffstat (limited to 'mpm/python')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e31x.py | 7 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e320.py | 7 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx.py | 5 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/x4xx.py | 7 |
4 files changed, 13 insertions, 13 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e31x.py b/mpm/python/usrp_mpm/periph_manager/e31x.py index 5a228d869..17a21d6e7 100644 --- a/mpm/python/usrp_mpm/periph_manager/e31x.py +++ b/mpm/python/usrp_mpm/periph_manager/e31x.py @@ -386,10 +386,9 @@ class e31x(ZynqComponents, PeriphManagerBase): self.log.warning( "Cannot run init(), device was never fully initialized!") return False - if args.get("clock_source", "") != "": - self.set_clock_source(args.get("clock_source")) - if args.get("time_source", "") != "": - self.set_time_source(args.get("time_source")) + args = self._update_default_args(args) + self.set_clock_source(args.get("clock_source", E310_DEFAULT_CLOCK_SOURCE)) + self.set_time_source(args.get("time_source", E310_DEFAULT_TIME_SOURCE)) if "no_reload_fpga" in args: self._do_not_reload = \ str2bool(args.get("no_reload_fpga")) or args.get("no_reload_fpga") == "" diff --git a/mpm/python/usrp_mpm/periph_manager/e320.py b/mpm/python/usrp_mpm/periph_manager/e320.py index 2878fe2b5..f3a8da12d 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320.py +++ b/mpm/python/usrp_mpm/periph_manager/e320.py @@ -298,10 +298,9 @@ class e320(ZynqComponents, PeriphManagerBase): self.log.warning( "Cannot run init(), device was never fully initialized!") return False - if args.get("clock_source", "") != "": - self.set_clock_source(args.get("clock_source")) - if args.get("time_source", "") != "": - self.set_time_source(args.get("time_source")) + args = self._update_default_args(args) + self.set_clock_source(args.get("clock_source", E320_DEFAULT_CLOCK_SOURCE)) + self.set_time_source(args.get("time_source", E320_DEFAULT_TIME_SOURCE)) result = super(e320, self).init(args) for xport_mgr in itervalues(self._xport_mgrs): xport_mgr.init(args) diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py index 2fbb12365..6800d356b 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py @@ -420,6 +420,7 @@ class n3xx(ZynqComponents, PeriphManagerBase): self.log.error( "Cannot run init(), device was never fully initialized!") return False + args = self._update_default_args(args) # We need to disable the PPS out during clock and dboard initialization in order # to avoid glitches. self.enable_pps_out(False) @@ -429,8 +430,8 @@ class n3xx(ZynqComponents, PeriphManagerBase): # properties should have been set to either the default values (first time # init() is run); or to the previous configured values (updated after a # successful clocking configuration). - args['clock_source'] = args.get('clock_source', self._clock_source) - args['time_source'] = args.get('time_source', self._time_source) + args['clock_source'] = args.get('clock_source', N3XX_DEFAULT_CLOCK_SOURCE) + args['time_source'] = args.get('time_source', N3XX_DEFAULT_TIME_SOURCE) self.set_sync_source(args) # Uh oh, some hard coded product-related info: The N300 has no LO # source connectors on the front panel, so we assume that if this was diff --git a/mpm/python/usrp_mpm/periph_manager/x4xx.py b/mpm/python/usrp_mpm/periph_manager/x4xx.py index 76c9e365d..7479874dc 100644 --- a/mpm/python/usrp_mpm/periph_manager/x4xx.py +++ b/mpm/python/usrp_mpm/periph_manager/x4xx.py @@ -631,6 +631,7 @@ class x4xx(ZynqComponents, PeriphManagerBase): self.log.warning( "Cannot run init(), device was never fully initialized!") return False + args = self._update_default_args(args) # We need to disable the PPS out during clock and dboard initialization in order # to avoid glitches. @@ -638,9 +639,9 @@ class x4xx(ZynqComponents, PeriphManagerBase): self._clocking_auxbrd.set_trig(False) # If the caller has not specified clock_source or time_source, set them - # to the values currently configured. - args['clock_source'] = args.get('clock_source', self._clk_mgr.get_clock_source()) - args['time_source'] = args.get('time_source', self._clk_mgr.get_time_source()) + # to the default values. + args['clock_source'] = args.get('clock_source', X400_DEFAULT_CLOCK_SOURCE) + args['time_source'] = args.get('time_source', X400_DEFAULT_TIME_SOURCE) self.set_sync_source(args) # If a Master Clock Rate was specified, |