diff options
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager')
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/base.py | 2 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/eiscat.py | 18 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py | 4 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/lmk_mg.py | 6 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/magnesium.py | 13 |
5 files changed, 21 insertions, 22 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/base.py b/mpm/python/usrp_mpm/dboard_manager/base.py index 68a3f3d5b..36f446360 100644 --- a/mpm/python/usrp_mpm/dboard_manager/base.py +++ b/mpm/python/usrp_mpm/dboard_manager/base.py @@ -39,7 +39,7 @@ class DboardManagerBase(object): self.log = get_logger('dboardManager') self.slot_idx = slot_idx if 'eeprom_md' not in kwargs: - self.log.warn("No EEPROM metadata given!") + self.log.debug("No EEPROM metadata given!") # In C++, we can only handle dicts if all the values are of the # same type. So we must convert them all to strings here: self.device_info = { diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py index 2b1c247ba..3581784ea 100644 --- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py @@ -71,7 +71,7 @@ class ADS54J56(object): else: self.sync_line = "AB" assert self.sync_line in ('AB', 'CD') - self.log.debug( + self.log.trace( "The next setup() sequence will use sync pin: {}".format( self.sync_line ) @@ -513,25 +513,25 @@ class EISCAT(DboardManagerBase): self.log.debug("Residual DAC offset error: {} ps.".format( offset_error*1e12 )) - self.log.info("Clock Synchronization Complete!") + self.log.debug("Clock Synchronization Complete!") # Go, go, go! if args.get("force_init", False): self.log.info("Forcing re-initialization of dboard.") self.initialized = args.get("force_init", self.initialized) if self.initialized: - self.log.info( + self.log.debug( "Dboard was previously initialized; skipping init. " \ "Specify force_init=1 to force initialization." ) return True - self.log.info("init() called with args `{}'".format( + self.log.debug("init() called with args `{}'".format( ",".join(['{}={}'.format(x, args[x]) for x in args]) )) self.radio_regs = _init_dboard_regs() self.jesd_cores = _init_jesd_cores(self.radio_regs, self.slot_idx) - self.log.info("Radio-register UIO object successfully generated!") + self.log.debug("Radio-register UIO object successfully generated!") self._spi_ifaces = _init_spi_devices() # Chips don't have power yet! - self.log.info("Loaded SPI interfaces!") + self.log.debug("Loaded SPI interfaces!") self._init_power(self.radio_regs) # Now, we can talk to chips via SPI self.dboard_clk_control = _init_clock_control(self.radio_regs) self.lmk = _init_lmk( @@ -546,7 +546,7 @@ class EISCAT(DboardManagerBase): for spi_iface in ('adc0', 'adc1') ] self.dboard_clk_control.enable_mmcm() - self.log.info("Clocking Configured Successfully!") + self.log.debug("Clocking Configured Successfully!") # Synchronize DB Clocks self.clock_synchronizer = ClockSynchronizer( self.radio_regs, @@ -618,7 +618,7 @@ class EISCAT(DboardManagerBase): return True for adc in self.adcs: adc.setup() - self.log.info("ADC Initialization Complete!") + self.log.debug("ADC Initialization Complete!") for jesd_core in self.jesd_cores: jesd_core.init_deframer() return True @@ -649,7 +649,7 @@ class EISCAT(DboardManagerBase): if error: return False - self.log.info("JESD Core Initialized, link up! (woohoo!)") + self.log.debug("JESD Core Initialized, link up! (woohoo!)") self.initialized = True return self.initialized diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py index 1fb756955..c2f35232d 100644 --- a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py @@ -30,7 +30,7 @@ class LMK04828EISCAT(LMK04828): """ Basic init. Turns it on. Let's us read SPI. """ - self.log.info("Reset LMK & Verify") + self.log.debug("Reset LMK & Verify") self.pokes8(( (0x000, 0x90), # Assert reset (0x000, 0x10), # De-assert reset @@ -183,7 +183,7 @@ class LMK04828EISCAT(LMK04828): (0x144, 0xFF), # Disable SYNC on all outputs including sysref (0x143, 0x52), # Pulser selected; SYNC enabled; 1 shot enabled )) - self.log.info("LMK init'd and locked!") + self.log.debug("LMK init'd and locked!") def lmk_shift(self, num_shifts=0): """ diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py b/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py index 22d3de983..3cb6ea7c9 100644 --- a/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py +++ b/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py @@ -61,7 +61,7 @@ class LMK04828Mg(LMK04828): """ Basic init. Turns it on. Let's read SPI. """ - self.log.info("Reset and Verify Chip ID") + self.log.debug("Reset and Verify Chip ID") self.pokes8(( (0x000, 0x90), # Assert reset (0x000, 0x10), # De-assert reset @@ -78,7 +78,7 @@ class LMK04828Mg(LMK04828): clkout_div_val = self.divide_to_reg(self.clkout_divider) clkout_cnt_val = self.divide_to_cnth_cntl_reg(self.clkout_divider) - self.log.info("Register Initialization Commencing...") + self.log.debug("Register Initialization Commencing...") self.pokes8(( (0x100, clkout_div_val), # CLKout Config (0x101, clkout_cnt_val), # CLKout Config @@ -225,7 +225,7 @@ class LMK04828Mg(LMK04828): (0x144, 0xFF), # Disable SYNC on all outputs including sysref (0x143, 0x52), # Pulser selected; SYNC enabled; 1 shot enabled )) - self.log.info("Clocks Initialized and PLLs Locked!") + self.log.debug("Clocks Initialized and PLLs Locked!") def lmk_shift(self, num_shifts=0): """ diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py index 470723e02..7d56dea67 100644 --- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py +++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py @@ -371,10 +371,10 @@ class Magnesium(DboardManagerBase): self.log.debug("Residual DAC offset error: {:.1f} ps.".format( offset_error*1e12 )) - self.log.info("Sample Clock Synchronization Complete!") + self.log.debug("Sample Clock Synchronization Complete!") ## Go, go, go! # Sanity checks and input validation: - self.log.info("init() called with args `{}'".format( + self.log.debug("init() called with args `{}'".format( ",".join(['{}={}'.format(x, args[x]) for x in args]) )) if not self._periphs_initialized: @@ -422,7 +422,7 @@ class Magnesium(DboardManagerBase): self.INIT_PHASE_DAC_WORD, ) db_clk_control.enable_mmcm() - self.log.info("Sample Clocks and Phase DAC Configured Successfully!") + self.log.debug("Sample Clocks and Phase DAC Configured Successfully!") # Synchronize DB Clocks _sync_db_clock(_get_clock_synchronizer()) # Clocks and PPS are now fully active! @@ -464,7 +464,7 @@ class Magnesium(DboardManagerBase): def init_rf_cal(self, args): " Setup RF CAL " - self.log.info("Setting up RF CAL...") + self.log.debug("Setting up RF CAL...") try: self._init_cals_mask = \ self._parse_and_convert_cal_args( @@ -507,8 +507,7 @@ class Magnesium(DboardManagerBase): Arguments: args {string:string} -- device arguments. """ - - self.log.info("Setting up LO source..") + self.log.debug("Setting up LO source..") rx_lo_source = args.get("rx_lo_source", "internal") tx_lo_source = args.get("tx_lo_source", "internal") self.mykonos.set_lo_source("RX", rx_lo_source) @@ -587,7 +586,7 @@ class Magnesium(DboardManagerBase): error_flag = True if error_flag: raise RuntimeError('JESD204B Link Initialization Failed. See MPM logs for details.') - self.log.info("JESD204B Link Initialization & Training Complete") + self.log.debug("JESD204B Link Initialization & Training Complete") def check_mykonos_framer_status(self): " Return True if Mykonos Framer is in good state " |