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-rw-r--r--models/fifo.v3
-rw-r--r--models/fifo_4k_18.v26
2 files changed, 28 insertions, 1 deletions
diff --git a/models/fifo.v b/models/fifo.v
index a04e7da6c..0ade49e9c 100644
--- a/models/fifo.v
+++ b/models/fifo.v
@@ -77,5 +77,6 @@ module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
-endmodule // fifo_1c_1k
+endmodule // fifo
+
diff --git a/models/fifo_4k_18.v b/models/fifo_4k_18.v
new file mode 100644
index 000000000..3efbf74f0
--- /dev/null
+++ b/models/fifo_4k_18.v
@@ -0,0 +1,26 @@
+
+
+module fifo_4k_18
+ (input [17:0] data,
+ input wrreq,
+ input wrclk,
+ output wrfull,
+ output wrempty,
+ output [11:0] wrusedw,
+
+ output [17:0] q,
+ input rdreq,
+ input rdclk,
+ output rdfull,
+ output rdempty,
+ output [11:0] rdusedw,
+
+ input aclr );
+
+fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_4k_18
+
+