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-rwxr-xr-xinband_lib/chan_fifo_reader.v42
-rwxr-xr-xinband_lib/channel_ram.v4
-rwxr-xr-xinband_lib/packet_builder.v18
-rwxr-xr-xinband_lib/register_io.v4
-rwxr-xr-xinband_lib/rx_buffer_inband.v354
-rwxr-xr-xinband_lib/tx_buffer_inband.v45
6 files changed, 241 insertions, 226 deletions
diff --git a/inband_lib/chan_fifo_reader.v b/inband_lib/chan_fifo_reader.v
index 9392bf151..a6edf2c60 100755
--- a/inband_lib/chan_fifo_reader.v
+++ b/inband_lib/chan_fifo_reader.v
@@ -1,7 +1,7 @@
module chan_fifo_reader
( reset, tx_clock, tx_strobe, adc_time, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
- underrun, tx_empty, debug, rssi, threshhold) ;
+ underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
input wire reset ;
input wire tx_clock ;
@@ -18,6 +18,7 @@ module chan_fifo_reader
output reg tx_empty ; //cause 0 to be the output
input wire [31:0] rssi;
input wire [31:0] threshhold;
+ input wire [31:0] rssi_wait;
output wire [14:0] debug;
assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]};
@@ -41,18 +42,19 @@ module chan_fifo_reader
`define PAYLOAD 8:2
`define ENDOFBURST 27
`define STARTOFBURST 28
- `define RSSI_FLAG 15
+ `define RSSI_FLAG 26
/* State registers */
reg [2:0] reader_state;
-
+ /* Local registers */
reg [6:0] payload_len;
reg [6:0] read_len;
reg [31:0] timestamp;
reg burst;
reg trash;
reg rssi_flag;
+ reg [31:0] time_wait;
always @(posedge tx_clock)
begin
@@ -68,6 +70,7 @@ module chan_fifo_reader
tx_i <= 0;
trash <= 0;
rssi_flag <= 0;
+ time_wait <= 0;
end
else
begin
@@ -81,13 +84,14 @@ module chan_fifo_reader
* is already available to this fifo_reader when pkt_waiting is on
*/
skip <=0;
+ time_wait <= 0;
if (pkt_waiting == 1)
begin
reader_state <= HEADER;
rdreq <= 1;
underrun <= 0;
end
- else if (burst == 1)
+ if (burst == 1 && pkt_waiting == 0)
underrun <= 1;
if (tx_strobe == 1)
@@ -139,9 +143,18 @@ module chan_fifo_reader
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
-
- // Let's send it
- if ((timestamp <= adc_time + `JITTER
+
+ time_wait <= time_wait + 32'd1;
+ // Outdated
+ if ((timestamp < adc_time) ||
+ (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
+ begin
+ trash <= 1;
+ reader_state <= IDLE;
+ skip <= 1;
+ end
+ // Let's send it
+ else if ((timestamp <= adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
begin
@@ -153,16 +166,11 @@ module chan_fifo_reader
else
reader_state <= WAIT;
end
+ else
+ reader_state <= WAIT;
// Wait a little bit more
- else if (timestamp > adc_time + `JITTER)
- reader_state <= WAIT;
- // Outdated
- else if (timestamp < adc_time)
- begin
- trash <= 1;
- reader_state <= IDLE;
- skip <= 1;
- end
+ //else if (timestamp > adc_time + `JITTER)
+ // reader_state <= WAIT;
end
// Wait for the transmit chain to be ready
@@ -183,7 +191,7 @@ module chan_fifo_reader
end
end
- // Send the samples to the tx_chain
+ // Send the samples to the tx_chain
SEND:
begin
reader_state <= WAITSTROBE;
diff --git a/inband_lib/channel_ram.v b/inband_lib/channel_ram.v
index 40e0efc01..60450f02d 100755
--- a/inband_lib/channel_ram.v
+++ b/inband_lib/channel_ram.v
@@ -101,8 +101,8 @@ module channel_ram
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
- assign packet_waiting = (nb_packets != 0) & (~rd_done_int);
-
+ //assign packet_waiting = (nb_packets != 0) & (~rd_done_int);
+ assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
diff --git a/inband_lib/packet_builder.v b/inband_lib/packet_builder.v
index 205293479..fbf0a656e 100755
--- a/inband_lib/packet_builder.v
+++ b/inband_lib/packet_builder.v
@@ -15,7 +15,8 @@ module packet_builder #(parameter NUM_CHAN = 1)(
output reg [15:0]fifodata,
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
- input wire [31:0]rssi_3, output wire [7:0] debugbus);
+ input wire [31:0]rssi_3, output wire [7:0] debugbus,
+ input [NUM_CHAN:0] overrun, input [NUM_CHAN:0] underrun);
// States
@@ -45,12 +46,14 @@ module packet_builder #(parameter NUM_CHAN = 1)(
reg [3:0] check_next;
wire [8:0] chan_used;
wire [31:0] true_rssi;
+ wire [4:0] true_channel;
- assign debugbus = {state, chan_empty[0], chan_empty[1], check_next[0],
+ assign debugbus = {state, chan_empty[0], underrun[0], check_next[0],
have_space, rd_select[0]};
assign chan_used = chan_usedw[8:0];
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
- ((rd_select[0]) ? rssi_1:rssi_0);
+ ((rd_select[0]) ? rssi_1:rssi_0);
+ assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
always @(posedge rxclk)
begin
if (reset)
@@ -64,6 +67,7 @@ module packet_builder #(parameter NUM_CHAN = 1)(
end
else case (state)
`IDLE: begin
+ chan_rdreq <= #1 0;
if (have_space)
begin
if(~chan_empty[check_next])
@@ -89,13 +93,12 @@ module packet_builder #(parameter NUM_CHAN = 1)(
end
`HEADER2: begin
- fifodata[`CHAN] <= #1 (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
+ fifodata[`CHAN] <= #1 true_channel;
fifodata[`RSSI] <= #1 true_rssi[5:0];
fifodata[`BURST] <= #1 0;
fifodata[`DROPPED] <= #1 0;
- fifodata[`UNDERRUN] <= #1 0;
- fifodata[`OVERRUN] <= #1 0;
-
+ fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
+ fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
state <= #1 `TIMESTAMP;
end
@@ -117,6 +120,7 @@ module packet_builder #(parameter NUM_CHAN = 1)(
begin
WR <= #1 0;
state <= #1 `IDLE;
+ chan_rdreq <= #1 0;
end
else if (read_length == payload_len - 4)
chan_rdreq <= #1 0;
diff --git a/inband_lib/register_io.v b/inband_lib/register_io.v
index 63a26549c..b116b3ace 100755
--- a/inband_lib/register_io.v
+++ b/inband_lib/register_io.v
@@ -2,12 +2,14 @@ module register_io
(input clk, input reset, input wire [1:0] enable, input wire [6:0] addr,
input wire [31:0] datain, output reg [31:0] dataout, output wire [15:0] debugbus,
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3, output wire [31:0] threshhold);
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+ output wire [31:0] threshhold, output wire [31:0] rssi_wait);
reg strobe;
wire [31:0] out[7:0];
assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
assign threshhold = out[1];
+ assign rssi_wait = out[2];
always @(*)
if (reset | ~enable[1])
diff --git a/inband_lib/rx_buffer_inband.v b/inband_lib/rx_buffer_inband.v
index c23ce09b7..1eaecabed 100755
--- a/inband_lib/rx_buffer_inband.v
+++ b/inband_lib/rx_buffer_inband.v
@@ -1,175 +1,179 @@
-//`include "../../firmware/include/fpga_regs_common.v"
-//`include "../../firmware/include/fpga_regs_standard.v"
-module rx_buffer_inband
- ( input usbclk,
- input bus_reset,
- input reset, // DSP side reset (used here), do not reset registers
- input reset_regs, //Only reset registers
- output [15:0] usbdata,
- input RD,
- output wire have_pkt_rdy,
- output reg rx_overrun,
- input wire [3:0] channels,
- input wire [15:0] ch_0,
- input wire [15:0] ch_1,
- input wire [15:0] ch_2,
- input wire [15:0] ch_3,
- input wire [15:0] ch_4,
- input wire [15:0] ch_5,
- input wire [15:0] ch_6,
- input wire [15:0] ch_7,
- input rxclk,
- input rxstrobe,
- input clear_status,
- input [6:0] serial_addr,
- input [31:0] serial_data,
- input serial_strobe,
- output wire [15:0] debugbus,
-
- //Connection with tx_inband
- input rx_WR,
- input [15:0] rx_databus,
- input rx_WR_done,
- output reg rx_WR_enabled,
- //signal strength
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3
- );
-
- parameter NUM_CHAN = 1;
- genvar i ;
-
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
-
- // Time counter
- reg [31:0] adctime;
- always @(posedge rxclk)
- if (reset)
- adctime <= 0;
- else if (rxstrobe)
- adctime <= adctime + 1;
-
- // USB side fifo
- wire [11:0] rdusedw;
- wire [11:0] wrusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
-
- fifo_4kx16_dc rx_usb_fifo (
- .aclr ( reset ),
- .data ( fifodata ),
- .rdclk ( ~usbclk ),
- .rdreq ( RD & ~read_count[8] ),
- .wrclk ( rxclk ),
- .wrreq ( WR ),
- .q ( usbdata ),
- .rdempty ( ),
- .rdusedw ( rdusedw ),
- .wrfull ( ),
- .wrusedw ( wrusedw ) );
-
- assign have_pkt_rdy = (rdusedw >= 12'd256);
- assign have_space = (wrusedw < 12'd760);
-
- // Rx side fifos
- wire chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [3:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
-
- packet_builder #(NUM_CHAN) rx_pkt_builer (
- .rxclk ( rxclk ),
- .reset ( reset ),
- .adctime ( adctime ),
- .channels ( 4'd1 ),
- .chan_rdreq ( chan_rdreq ),
- .chan_fifodata ( chan_fifodata ),
- .chan_empty ( chan_empty ),
- .rd_select ( rd_select ),
- .chan_usedw ( chan_usedw ),
- .WR ( WR ),
- .fifodata ( fifodata ),
- .have_space ( have_space ),
- .rssi_0(rssi_0), .rssi_1(rssi_1),
- .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug));
-
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
-
- reg [6:0] test;
- always @(posedge rxclk)
- if (reset)
- test <= 0;
- else
- test <= test + 7'd1;
-
- // TODO write this genericly
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
-
- wire cmd_empty;
- always @(posedge rxclk)
- if(reset)
- rx_WR_enabled <= 1;
- else if(cmd_empty)
- rx_WR_enabled <= 1;
- else if(rx_WR_done)
- rx_WR_enabled <= 0;
-
- wire [15:0] dataout [0:NUM_CHAN];
- wire [9:0] usedw [0:NUM_CHAN];
-
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
- wire rdreq;
-
- assign rdreq = (rd_select == i) & chan_rdreq;
- assign chan_empty[i] = usedw[i] < 10'd126;
-
- fifo_2kx16 rx_chan_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( ch[i] ),
- .rdreq ( rdreq ),
- .wrreq ( ~rx_full[i] & rxstrobe),
- .empty ( ),
- .full ( rx_full[i] ),
- .q ( dataout[i]),
- .usedw ( usedw[i] )
- );
- end
- endgenerate
- wire [7:0] debug;
- fifo_2kx16 rx_cmd_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( rx_databus ),
- .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
- .wrreq ( rx_WR & rx_WR_enabled),
- .empty ( cmd_empty),
- .full ( rx_full[NUM_CHAN] ),
- .q ( dataout[NUM_CHAN]),
- .usedw ( usedw[NUM_CHAN] )
- );
- assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
- assign chan_fifodata = dataout[rd_select];
- assign chan_usedw = usedw[rd_select];
- assign debugbus = {wrusedw, have_space, RD, read_count[8], rxclk};
-endmodule
+//`include "../../firmware/include/fpga_regs_common.v"
+//`include "../../firmware/include/fpga_regs_standard.v"
+module rx_buffer_inband
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output wire [15:0] debugbus,
+
+ //Connection with tx_inband
+ input rx_WR,
+ input [15:0] rx_databus,
+ input rx_WR_done,
+ output reg rx_WR_enabled,
+ //signal strength
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+ input wire [1:0] tx_overrun, input wire [1:0] tx_underrun
+ );
+
+ parameter NUM_CHAN = 1;
+ genvar i ;
+
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
+
+ // USB side fifo
+ wire [11:0] rdusedw;
+ wire [11:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
+
+ fifo_4kx16_dc rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
+
+ assign have_pkt_rdy = (rdusedw >= 12'd256);
+ assign have_space = (wrusedw < 12'd760);
+
+ // Rx side fifos
+ wire chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [3:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
+
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+ .adctime ( adctime ),
+ .channels ( 4'd1 ),
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
+ .WR ( WR ),
+ .fifodata ( fifodata ),
+ .have_space ( have_space ),
+ .rssi_0(rssi_0), .rssi_1(rssi_1),
+ .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+ .overrun(tx_overrun), .underrun(tx_underrun));
+
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ reg [6:0] test;
+ always @(posedge rxclk)
+ if (reset)
+ test <= 0;
+ else
+ test <= test + 7'd1;
+
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
+
+ wire cmd_empty;
+ always @(posedge rxclk)
+ if(reset)
+ rx_WR_enabled <= 1;
+ else if(cmd_empty)
+ rx_WR_enabled <= 1;
+ else if(rx_WR_done)
+ rx_WR_enabled <= 0;
+
+ wire [15:0] dataout [0:NUM_CHAN];
+ wire [9:0] usedw [0:NUM_CHAN];
+ wire empty[0:NUM_CHAN];
+
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+ wire rdreq;
+
+ assign rdreq = (rd_select == i) & chan_rdreq;
+ //assign chan_empty[i] = usedw[i] < 10'd126;
+ fifo_1kx16 rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( ch[i] ),
+ .rdreq ( rdreq ),
+ .wrreq ( ~rx_full[i] & rxstrobe),
+ .empty (empty[i]),
+ .full (rx_full[i]),
+ .q ( dataout[i]),
+ .usedw ( usedw[i]),
+ .almost_empty(chan_empty[i])
+ );
+ end
+ endgenerate
+ wire [7:0] debug;
+ fifo_1kx16 rx_cmd_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( rx_databus ),
+ .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+ .wrreq ( rx_WR & rx_WR_enabled),
+ .empty ( cmd_empty),
+ .full ( rx_full[NUM_CHAN] ),
+ .q ( dataout[NUM_CHAN]),
+ .usedw ( usedw[NUM_CHAN] )
+ );
+ assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+ assign chan_fifodata = dataout[rd_select];
+ assign chan_usedw = usedw[rd_select];
+ assign debugbus = {rxstrobe, chan_rdreq, debug,
+ rx_full[0], chan_empty[0], empty[0], have_space, RD, rxclk};
+endmodule
diff --git a/inband_lib/tx_buffer_inband.v b/inband_lib/tx_buffer_inband.v
index af7ed394a..fec9dbe31 100755
--- a/inband_lib/tx_buffer_inband.v
+++ b/inband_lib/tx_buffer_inband.v
@@ -1,18 +1,13 @@
module tx_buffer_inband
( usbclk, bus_reset, reset, usbdata, WR, have_space,
- tx_underrun, channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1,
+ channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1,
tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe,
clear_status, tx_empty, debugbus,
rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable,
reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2,
- rssi_3, threshhold
+ rssi_3, rssi_wait, threshhold, tx_underrun
);
-
- //CHAN_WIDTH is the width of the channel
- //NUM_CHAN is the number of data channel (index from 0 to NUM_CHAN-1)
- //index NUM_CHAN is reserved for command
- parameter CHAN_WIDTH = 2 ;
parameter NUM_CHAN = 2 ;
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
@@ -37,9 +32,9 @@ module tx_buffer_inband
input wire [31:0]rssi_2;
input wire [31:0]rssi_3;
input wire [31:0]threshhold;
-
+ input wire [31:0]rssi_wait;
+
output wire have_space ;
- output wire tx_underrun ;
output wire tx_empty ;
output wire [15:0] tx_i_0 ;
output wire [15:0] tx_q_0 ;
@@ -59,13 +54,14 @@ module tx_buffer_inband
output wire [31:0] reg_data_in;
output wire [6:0] reg_addr;
output wire [1:0] reg_io_enable;
+ output wire [NUM_CHAN-1:0] tx_underrun;
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
reg [31:0] adc_time ;
- wire [7:0] txstrobe_rate [CHAN_WIDTH-1:0] ;
+ wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
@@ -82,33 +78,32 @@ module tx_buffer_inband
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
- wire [CHAN_WIDTH:0] chan_WR ;
- wire [CHAN_WIDTH:0] chan_done ;
+ wire [NUM_CHAN:0] chan_WR ;
+ wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
- wire [CHAN_WIDTH:0] chan_underrun ;
- wire [CHAN_WIDTH:0] chan_txempty ;
+ wire [NUM_CHAN:0] chan_underrun ;
+ wire [NUM_CHAN:0] chan_txempty ;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
- wire [31:0] chan_fifodata [CHAN_WIDTH:0] ;
- wire chan_pkt_waiting [CHAN_WIDTH:0] ;
- wire chan_rdreq [CHAN_WIDTH:0] ;
- wire chan_skip [CHAN_WIDTH:0] ;
- wire [CHAN_WIDTH:0] chan_have_space ;
- wire chan_txstrobe [CHAN_WIDTH-1:0] ;
+ wire [31:0] chan_fifodata [NUM_CHAN:0] ;
+ wire chan_pkt_waiting [NUM_CHAN:0] ;
+ wire chan_rdreq [NUM_CHAN:0] ;
+ wire chan_skip [NUM_CHAN:0] ;
+ wire [NUM_CHAN:0] chan_have_space ;
+ wire chan_txstrobe [NUM_CHAN-1:0] ;
wire [14:0] debug;
/* Outputs to transmit chains */
- wire [15:0] tx_i [CHAN_WIDTH-1:0] ;
- wire [15:0] tx_q [CHAN_WIDTH-1:0] ;
+ wire [15:0] tx_i [NUM_CHAN-1:0] ;
+ wire [15:0] tx_q [NUM_CHAN-1:0] ;
/* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0] & chan_have_space[1];
assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
- assign tx_underrun = chan_underrun[0] | chan_underrun[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
@@ -153,6 +148,7 @@ module tx_buffer_inband
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
+ assign tx_underrun[i] = chan_underrun[i];
channel_ram tx_data_packet_fifo
( .reset (reset),
.txclk (txclk),
@@ -181,7 +177,8 @@ module tx_buffer_inband
.pkt_waiting (chan_pkt_waiting[i]),
.tx_empty (chan_txempty[i]),
.rssi (rssi[i]),
- .threshhold (threshhold)
+ .threshhold (threshhold),
+ .rssi_wait (rssi_wait)
);
end
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 16:56:21 +0000