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-rw-r--r--images/image_package_mapping.py60
1 files changed, 14 insertions, 46 deletions
diff --git a/images/image_package_mapping.py b/images/image_package_mapping.py
index ee5361aea..eeea4e777 100644
--- a/images/image_package_mapping.py
+++ b/images/image_package_mapping.py
@@ -36,12 +36,8 @@ PACKAGE_MAPPING = {
'usrp_e320_fpga_XG.bit.md5',
'usrp_e320_fpga_XG.dts',
'usrp_e320_fpga_XG.dts.md5',
- 'usrp_e320_fpga_XG.rpt']
- },
- "e320_aa": {
- "type": "e3xx",
- "package_name": "e3xx_e320_fpga_aurora-g{}.zip",
- "files": ['usrp_e320_fpga_AA.bit',
+ 'usrp_e320_fpga_XG.rpt',
+ 'usrp_e320_fpga_AA.bit',
'usrp_e320_fpga_AA.bit.md5',
'usrp_e320_fpga_AA.dts',
'usrp_e320_fpga_AA.dts.md5',
@@ -84,7 +80,12 @@ PACKAGE_MAPPING = {
'usrp_n310_fpga_WX.bit.md5',
'usrp_n310_fpga_WX.dts',
'usrp_n310_fpga_WX.dts.md5',
- 'usrp_n310_fpga_WX.rpt',],
+ 'usrp_n310_fpga_WX.rpt',
+ 'usrp_n310_fpga_AA.bit',
+ 'usrp_n310_fpga_AA.bit.md5',
+ 'usrp_n310_fpga_AA.dts',
+ 'usrp_n310_fpga_AA.dts.md5',
+ 'usrp_n310_fpga_AA.rpt'],
},
"n300": {
"type": "n3xx",
@@ -103,7 +104,12 @@ PACKAGE_MAPPING = {
'usrp_n300_fpga_WX.bit.md5',
'usrp_n300_fpga_WX.dts',
'usrp_n300_fpga_WX.dts.md5',
- 'usrp_n300_fpga_WX.rpt',],
+ 'usrp_n300_fpga_WX.rpt',
+ 'usrp_n300_fpga_AA.bit',
+ 'usrp_n300_fpga_AA.bit.md5',
+ 'usrp_n300_fpga_AA.dts',
+ 'usrp_n300_fpga_AA.dts.md5',
+ 'usrp_n300_fpga_AA.rpt'],
},
"n320": {
"type": "n3xx",
@@ -129,44 +135,6 @@ PACKAGE_MAPPING = {
'usrp_n320_fpga_AQ.dts.md5',
'usrp_n320_fpga_AQ.rpt',],
},
- "n310_aa": {
- "type": "n3xx",
- "package_name": "n3xx_n310_fpga_aurora-g{}.zip",
- "files": ['usrp_n310_fpga_AA.bit',
- 'usrp_n310_fpga_AA.bit.md5',
- 'usrp_n310_fpga_AA.dts',
- 'usrp_n310_fpga_AA.dts.md5',
- 'usrp_n310_fpga_AA.rpt',
- 'usrp_n310_fpga_HA.bit',
- 'usrp_n310_fpga_HA.bit.md5',
- 'usrp_n310_fpga_HA.dts',
- 'usrp_n310_fpga_HA.dts.md5',
- 'usrp_n310_fpga_HA.rpt',
- 'usrp_n310_fpga_XA.bit',
- 'usrp_n310_fpga_XA.bit.md5',
- 'usrp_n310_fpga_XA.dts',
- 'usrp_n310_fpga_XA.dts.md5',
- 'usrp_n310_fpga_XA.rpt']
- },
- "n300_aa": {
- "type": "n3xx",
- "package_name": "n3xx_n300_fpga_aurora-g{}.zip",
- "files": ['usrp_n300_fpga_AA.bit',
- 'usrp_n300_fpga_AA.bit.md5',
- 'usrp_n300_fpga_AA.dts',
- 'usrp_n300_fpga_AA.dts.md5',
- 'usrp_n300_fpga_AA.rpt',
- 'usrp_n300_fpga_HA.bit',
- 'usrp_n300_fpga_HA.bit.md5',
- 'usrp_n300_fpga_HA.dts',
- 'usrp_n300_fpga_HA.dts.md5',
- 'usrp_n300_fpga_HA.rpt',
- 'usrp_n300_fpga_XA.bit',
- 'usrp_n300_fpga_XA.bit.md5',
- 'usrp_n300_fpga_XA.dts',
- 'usrp_n300_fpga_XA.dts.md5',
- 'usrp_n300_fpga_XA.rpt']
- },
"n320_cpld": {
"type": "n3xx",
"package_name": "n3xx_n320_cpld_default-g{}.zip",