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-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.cpp186
1 files changed, 90 insertions, 96 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp
index 23b66087f..57ae36857 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.cpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.cpp
@@ -19,6 +19,20 @@
#include "usrp2_iface.hpp"
////////////////////////////////////////////////////////////////////////
+// Define slave bases
+////////////////////////////////////////////////////////////////////////
+#define ROUTER_RAM_BASE 0x4000
+#define SPI_BASE 0x5000
+#define I2C_BASE 0x5400
+#define GPIO_BASE 0x5800
+#define READBACK_BASE 0x5C00
+#define ETH_BASE 0x6000
+#define SETTING_REGS_BASE 0x7000
+#define PIC_BASE 0x8000
+#define UART_BASE 0x8800
+#define ATR_BASE 0x8C00
+
+////////////////////////////////////////////////////////////////////////
// Setting register offsets
////////////////////////////////////////////////////////////////////////
#define SR_MISC 0 // 7 regs
@@ -38,105 +52,85 @@
#define SR_UDP_SM 192 // 64
-int sr_addr(int misc_output_base, int sr) {
- return misc_output_base + 4 * sr;
+int sr_addr(int sr) {
+ return SETTING_REGS_BASE + (4 * sr);
}
-////////////////////////////////////////////////////////////////////////
-// Slave bases
-////////////////////////////////////////////////////////////////////////
-#define USRP2_MISC_OUTPUT_BASE 0xD400
-#define USRP2_GPIO_BASE 0xC800
-#define USRP2_ATR_BASE 0xE400
-#define USRP2_BP_STATUS_BASE 0xCC00
-
-#define USRP2P_MISC_OUTPUT_BASE 0x5000
-#define USRP2P_GPIO_BASE 0x6200
-#define USRP2P_ATR_BASE 0x6800
-#define USRP2P_BP_STATUS_BASE 0x6300
-
-usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
-
- //how about you just make this dependent on hw_rev instead of doing the init before main, and give up the const globals, since the application won't ever need both.
- const int misc_output_base = (use_n2xx_map) ? USRP2P_MISC_OUTPUT_BASE : USRP2_MISC_OUTPUT_BASE,
- gpio_base = (use_n2xx_map) ? USRP2P_GPIO_BASE : USRP2_GPIO_BASE,
- atr_base = (use_n2xx_map) ? USRP2P_ATR_BASE : USRP2_ATR_BASE,
- bp_base = (use_n2xx_map) ? USRP2P_BP_STATUS_BASE : USRP2_BP_STATUS_BASE;
-
+usrp2_regs_t usrp2_get_regs(bool) {
usrp2_regs_t x;
- x.misc_ctrl_clock = sr_addr(misc_output_base, 0);
- x.misc_ctrl_serdes = sr_addr(misc_output_base, 1);
- x.misc_ctrl_adc = sr_addr(misc_output_base, 2);
- x.misc_ctrl_leds = sr_addr(misc_output_base, 3);
- x.misc_ctrl_phy = sr_addr(misc_output_base, 4);
- x.misc_ctrl_dbg_mux = sr_addr(misc_output_base, 5);
- x.misc_ctrl_ram_page = sr_addr(misc_output_base, 6);
- x.misc_ctrl_flush_icache = sr_addr(misc_output_base, 7);
- x.misc_ctrl_led_src = sr_addr(misc_output_base, 8);
- x.time64_secs = sr_addr(misc_output_base, SR_TIME64 + 0);
- x.time64_ticks = sr_addr(misc_output_base, SR_TIME64 + 1);
- x.time64_flags = sr_addr(misc_output_base, SR_TIME64 + 2);
- x.time64_imm = sr_addr(misc_output_base, SR_TIME64 + 3);
- x.time64_tps = sr_addr(misc_output_base, SR_TIME64 + 4);
- x.time64_mimo_sync = sr_addr(misc_output_base, SR_TIME64 + 5);
- x.status = bp_base + 4*8;
- x.time64_secs_rb_imm = bp_base + 4*10;
- x.time64_ticks_rb_imm = bp_base + 4*11;
- x.compat_num_rb = bp_base + 4*12;
- x.time64_secs_rb_pps = bp_base + 4*14;
- x.time64_ticks_rb_pps = bp_base + 4*15;
- x.dsp_tx_freq = sr_addr(misc_output_base, SR_TX_DSP + 0);
- x.dsp_tx_scale_iq = sr_addr(misc_output_base, SR_TX_DSP + 1);
- x.dsp_tx_interp_rate = sr_addr(misc_output_base, SR_TX_DSP + 2);
- x.dsp_tx_mux = sr_addr(misc_output_base, SR_TX_DSP + 4);
- x.dsp_rx[0].freq = sr_addr(misc_output_base, SR_RX_DSP0 + 0);
- x.dsp_rx[0].scale_iq = sr_addr(misc_output_base, SR_RX_DSP0 + 1);
- x.dsp_rx[0].decim_rate = sr_addr(misc_output_base, SR_RX_DSP0 + 2);
- x.dsp_rx[0].dcoffset_i = sr_addr(misc_output_base, SR_RX_DSP0 + 3);
- x.dsp_rx[0].dcoffset_q = sr_addr(misc_output_base, SR_RX_DSP0 + 4);
- x.dsp_rx[0].mux = sr_addr(misc_output_base, SR_RX_DSP0 + 5);
- x.dsp_rx[1].freq = sr_addr(misc_output_base, SR_RX_DSP1 + 0);
- x.dsp_rx[1].scale_iq = sr_addr(misc_output_base, SR_RX_DSP1 + 1);
- x.dsp_rx[1].decim_rate = sr_addr(misc_output_base, SR_RX_DSP1 + 2);
- x.dsp_rx[1].dcoffset_i = sr_addr(misc_output_base, SR_RX_DSP1 + 3);
- x.dsp_rx[1].dcoffset_q = sr_addr(misc_output_base, SR_RX_DSP1 + 4);
- x.dsp_rx[1].mux = sr_addr(misc_output_base, SR_RX_DSP1 + 5);
- x.gpio_io = gpio_base + 0;
- x.gpio_ddr = gpio_base + 4;
- x.gpio_tx_sel = gpio_base + 8;
- x.gpio_rx_sel = gpio_base + 12;
- x.atr_idle_txside = atr_base + 0;
- x.atr_idle_rxside = atr_base + 2;
- x.atr_intx_txside = atr_base + 4;
- x.atr_intx_rxside = atr_base + 6;
- x.atr_inrx_txside = atr_base + 8;
- x.atr_inrx_rxside = atr_base + 10;
- x.atr_full_txside = atr_base + 12;
- x.atr_full_rxside = atr_base + 14;
- x.rx_ctrl[0].stream_cmd = sr_addr(misc_output_base, SR_RX_CTRL0 + 0);
- x.rx_ctrl[0].time_secs = sr_addr(misc_output_base, SR_RX_CTRL0 + 1);
- x.rx_ctrl[0].time_ticks = sr_addr(misc_output_base, SR_RX_CTRL0 + 2);
- x.rx_ctrl[0].clear_overrun = sr_addr(misc_output_base, SR_RX_CTRL0 + 3);
- x.rx_ctrl[0].vrt_header = sr_addr(misc_output_base, SR_RX_CTRL0 + 4);
- x.rx_ctrl[0].vrt_stream_id = sr_addr(misc_output_base, SR_RX_CTRL0 + 5);
- x.rx_ctrl[0].vrt_trailer = sr_addr(misc_output_base, SR_RX_CTRL0 + 6);
- x.rx_ctrl[0].nsamps_per_pkt = sr_addr(misc_output_base, SR_RX_CTRL0 + 7);
- x.rx_ctrl[0].nchannels = sr_addr(misc_output_base, SR_RX_CTRL0 + 8);
- x.rx_ctrl[1].stream_cmd = sr_addr(misc_output_base, SR_RX_CTRL1 + 0);
- x.rx_ctrl[1].time_secs = sr_addr(misc_output_base, SR_RX_CTRL1 + 1);
- x.rx_ctrl[1].time_ticks = sr_addr(misc_output_base, SR_RX_CTRL1 + 2);
- x.rx_ctrl[1].clear_overrun = sr_addr(misc_output_base, SR_RX_CTRL1 + 3);
- x.rx_ctrl[1].vrt_header = sr_addr(misc_output_base, SR_RX_CTRL1 + 4);
- x.rx_ctrl[1].vrt_stream_id = sr_addr(misc_output_base, SR_RX_CTRL1 + 5);
- x.rx_ctrl[1].vrt_trailer = sr_addr(misc_output_base, SR_RX_CTRL1 + 6);
- x.rx_ctrl[1].nsamps_per_pkt = sr_addr(misc_output_base, SR_RX_CTRL1 + 7);
- x.rx_ctrl[1].nchannels = sr_addr(misc_output_base, SR_RX_CTRL1 + 8);
- x.tx_ctrl_num_chan = sr_addr(misc_output_base, SR_TX_CTRL + 0);
- x.tx_ctrl_clear_state = sr_addr(misc_output_base, SR_TX_CTRL + 1);
- x.tx_ctrl_report_sid = sr_addr(misc_output_base, SR_TX_CTRL + 2);
- x.tx_ctrl_policy = sr_addr(misc_output_base, SR_TX_CTRL + 3);
- x.tx_ctrl_cycles_per_up = sr_addr(misc_output_base, SR_TX_CTRL + 4);
- x.tx_ctrl_packets_per_up = sr_addr(misc_output_base, SR_TX_CTRL + 5);
+ x.misc_ctrl_clock = sr_addr(0);
+ x.misc_ctrl_serdes = sr_addr(1);
+ x.misc_ctrl_adc = sr_addr(2);
+ x.misc_ctrl_leds = sr_addr(3);
+ x.misc_ctrl_phy = sr_addr(4);
+ x.misc_ctrl_dbg_mux = sr_addr(5);
+ x.misc_ctrl_ram_page = sr_addr(6);
+ x.misc_ctrl_flush_icache = sr_addr(7);
+ x.misc_ctrl_led_src = sr_addr(8);
+ x.time64_secs = sr_addr(SR_TIME64 + 0);
+ x.time64_ticks = sr_addr(SR_TIME64 + 1);
+ x.time64_flags = sr_addr(SR_TIME64 + 2);
+ x.time64_imm = sr_addr(SR_TIME64 + 3);
+ x.time64_tps = sr_addr(SR_TIME64 + 4);
+ x.time64_mimo_sync = sr_addr(SR_TIME64 + 5);
+ x.status = READBACK_BASE + 4*8;
+ x.time64_secs_rb_imm = READBACK_BASE + 4*10;
+ x.time64_ticks_rb_imm = READBACK_BASE + 4*11;
+ x.compat_num_rb = READBACK_BASE + 4*12;
+ x.time64_secs_rb_pps = READBACK_BASE + 4*14;
+ x.time64_ticks_rb_pps = READBACK_BASE + 4*15;
+ x.dsp_tx_freq = sr_addr(SR_TX_DSP + 0);
+ x.dsp_tx_scale_iq = sr_addr(SR_TX_DSP + 1);
+ x.dsp_tx_interp_rate = sr_addr(SR_TX_DSP + 2);
+ x.dsp_tx_mux = sr_addr(SR_TX_DSP + 4);
+ x.dsp_rx[0].freq = sr_addr(SR_RX_DSP0 + 0);
+ x.dsp_rx[0].scale_iq = sr_addr(SR_RX_DSP0 + 1);
+ x.dsp_rx[0].decim_rate = sr_addr(SR_RX_DSP0 + 2);
+ x.dsp_rx[0].dcoffset_i = sr_addr(SR_RX_DSP0 + 3);
+ x.dsp_rx[0].dcoffset_q = sr_addr(SR_RX_DSP0 + 4);
+ x.dsp_rx[0].mux = sr_addr(SR_RX_DSP0 + 5);
+ x.dsp_rx[1].freq = sr_addr(SR_RX_DSP1 + 0);
+ x.dsp_rx[1].scale_iq = sr_addr(SR_RX_DSP1 + 1);
+ x.dsp_rx[1].decim_rate = sr_addr(SR_RX_DSP1 + 2);
+ x.dsp_rx[1].dcoffset_i = sr_addr(SR_RX_DSP1 + 3);
+ x.dsp_rx[1].dcoffset_q = sr_addr(SR_RX_DSP1 + 4);
+ x.dsp_rx[1].mux = sr_addr(SR_RX_DSP1 + 5);
+ x.gpio_io = GPIO_BASE + 0;
+ x.gpio_ddr = GPIO_BASE + 4;
+ x.gpio_tx_sel = GPIO_BASE + 8;
+ x.gpio_rx_sel = GPIO_BASE + 12;
+ x.atr_idle_txside = ATR_BASE + 0;
+ x.atr_idle_rxside = ATR_BASE + 2;
+ x.atr_intx_txside = ATR_BASE + 4;
+ x.atr_intx_rxside = ATR_BASE + 6;
+ x.atr_inrx_txside = ATR_BASE + 8;
+ x.atr_inrx_rxside = ATR_BASE + 10;
+ x.atr_full_txside = ATR_BASE + 12;
+ x.atr_full_rxside = ATR_BASE + 14;
+ x.rx_ctrl[0].stream_cmd = sr_addr(SR_RX_CTRL0 + 0);
+ x.rx_ctrl[0].time_secs = sr_addr(SR_RX_CTRL0 + 1);
+ x.rx_ctrl[0].time_ticks = sr_addr(SR_RX_CTRL0 + 2);
+ x.rx_ctrl[0].clear_overrun = sr_addr(SR_RX_CTRL0 + 3);
+ x.rx_ctrl[0].vrt_header = sr_addr(SR_RX_CTRL0 + 4);
+ x.rx_ctrl[0].vrt_stream_id = sr_addr(SR_RX_CTRL0 + 5);
+ x.rx_ctrl[0].vrt_trailer = sr_addr(SR_RX_CTRL0 + 6);
+ x.rx_ctrl[0].nsamps_per_pkt = sr_addr(SR_RX_CTRL0 + 7);
+ x.rx_ctrl[0].nchannels = sr_addr(SR_RX_CTRL0 + 8);
+ x.rx_ctrl[1].stream_cmd = sr_addr(SR_RX_CTRL1 + 0);
+ x.rx_ctrl[1].time_secs = sr_addr(SR_RX_CTRL1 + 1);
+ x.rx_ctrl[1].time_ticks = sr_addr(SR_RX_CTRL1 + 2);
+ x.rx_ctrl[1].clear_overrun = sr_addr(SR_RX_CTRL1 + 3);
+ x.rx_ctrl[1].vrt_header = sr_addr(SR_RX_CTRL1 + 4);
+ x.rx_ctrl[1].vrt_stream_id = sr_addr(SR_RX_CTRL1 + 5);
+ x.rx_ctrl[1].vrt_trailer = sr_addr(SR_RX_CTRL1 + 6);
+ x.rx_ctrl[1].nsamps_per_pkt = sr_addr(SR_RX_CTRL1 + 7);
+ x.rx_ctrl[1].nchannels = sr_addr(SR_RX_CTRL1 + 8);
+ x.tx_ctrl_num_chan = sr_addr(SR_TX_CTRL + 0);
+ x.tx_ctrl_clear_state = sr_addr(SR_TX_CTRL + 1);
+ x.tx_ctrl_report_sid = sr_addr(SR_TX_CTRL + 2);
+ x.tx_ctrl_policy = sr_addr(SR_TX_CTRL + 3);
+ x.tx_ctrl_cycles_per_up = sr_addr(SR_TX_CTRL + 4);
+ x.tx_ctrl_packets_per_up = sr_addr(SR_TX_CTRL + 5);
return x;
}
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