diff options
Diffstat (limited to 'host')
| -rw-r--r-- | host/lib/usrp/usrp2/dsp_impl.cpp | 6 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/mboard_impl.cpp | 46 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 23 |
3 files changed, 60 insertions, 15 deletions
diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp index 03cdeae42..d9cde3f13 100644 --- a/host/lib/usrp/usrp2/dsp_impl.cpp +++ b/host/lib/usrp/usrp2/dsp_impl.cpp @@ -173,12 +173,6 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_ //set the decimation _iface->poke32(U2_REG_DSP_RX_DECIM(which_dsp), dsp_type1::calc_cic_filter_word(_dsp_impl->ddc_decim[which_dsp])); - - //set the scaling - static const boost::int16_t default_rx_scale_iq = 1024; - _iface->poke32(U2_REG_DSP_RX_SCALE_IQ(which_dsp), - dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) - ); } _device.update_xport_channel_mapping(); //rate changed -> update return; diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 6bf412a3e..5315522f0 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -429,19 +429,51 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){ set_time_spec(val.as<time_spec_t>(), false); return; - case MBOARD_PROP_RX_SUBDEV_SPEC: + case MBOARD_PROP_RX_SUBDEV_SPEC:{ _rx_subdev_spec = val.as<subdev_spec_t>(); verify_rx_subdev_spec(_rx_subdev_spec, this->get_link()); //sanity check UHD_ASSERT_THROW(_rx_subdev_spec.size() <= NUM_RX_DSPS); - //set the mux + + //determine frontend swap IQ from the first channel + bool fe_swap_iq = false; + switch(_dboard_manager->get_rx_subdev(_rx_subdev_spec.at(0).sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()){ + case SUBDEV_CONN_COMPLEX_QI: + case SUBDEV_CONN_REAL_Q: + fe_swap_iq = true; + break; + default: fe_swap_iq = false; + } + _iface->poke32(U2_REG_RX_FE_SWAP_IQ, fe_swap_iq? 1 : 0); + + //set the dsp mux for each channel for (size_t i = 0; i < _rx_subdev_spec.size(); i++){ - _iface->poke32(U2_REG_DSP_RX_MUX(i), dsp_type1::calc_rx_mux_word( - _dboard_manager->get_rx_subdev(_rx_subdev_spec[i].sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>() - )); + bool iq_swap = false, real_mode = false; + switch(_dboard_manager->get_rx_subdev(_rx_subdev_spec.at(i).sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()){ + case SUBDEV_CONN_COMPLEX_IQ: + iq_swap = fe_swap_iq; + real_mode = false; + break; + case SUBDEV_CONN_COMPLEX_QI: + iq_swap = not fe_swap_iq; + real_mode = false; + break; + case SUBDEV_CONN_REAL_I: + iq_swap = fe_swap_iq; + real_mode = true; + break; + case SUBDEV_CONN_REAL_Q: + iq_swap = not fe_swap_iq; + real_mode = true; + break; + } + _iface->poke32(U2_REG_DSP_RX_MUX(i), + (iq_swap? U2_FLAG_DSP_RX_MUX_SWAP_IQ : 0) | + (real_mode? U2_FLAG_DSP_RX_MUX_REAL_MODE : 0) + ); } _device.update_xport_channel_mapping(); - return; + }return; case MBOARD_PROP_TX_SUBDEV_SPEC: _tx_subdev_spec = val.as<subdev_spec_t>(); @@ -450,7 +482,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){ UHD_ASSERT_THROW(_tx_subdev_spec.size() <= NUM_TX_DSPS); //set the mux for (size_t i = 0; i < _rx_subdev_spec.size(); i++){ - _iface->poke32(U2_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( + _iface->poke32(U2_REG_TX_FE_MUX, dsp_type1::calc_tx_mux_word( _dboard_manager->get_tx_subdev(_tx_subdev_spec[i].sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>() )); } diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index dbb78275b..d43dcc6bc 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -120,12 +120,29 @@ #define U2_REG_TIME64_TICKS_RB_PPS READBACK_BASE + 4*15 ///////////////////////////////////////////////// +// RX FE +//////////////////////////////////////////////// +#define U2_REG_RX_FE_SWAP_IQ U2_REG_SR_ADDR(SR_RX_FRONT + 0) //lower bit +#define U2_REG_RX_FE_MAG_CORRECTION U2_REG_SR_ADDR(SR_RX_FRONT + 1) //18 bits +#define U2_REG_RX_FE_PHASE_CORRECTION U2_REG_SR_ADDR(SR_RX_FRONT + 2) //18 bits +#define U2_REG_RX_FE_OFFSET_I U2_REG_SR_ADDR(SR_RX_FRONT + 3) //18 bits +#define U2_REG_RX_FE_OFFSET_Q U2_REG_SR_ADDR(SR_RX_FRONT + 4) //18 bits + +///////////////////////////////////////////////// +// TX FE +//////////////////////////////////////////////// +#define U2_REG_TX_FE_DC_OFFSET_I U2_REG_SR_ADDR(SR_TX_FRONT + 0) //24 bits +#define U2_REG_TX_FE_DC_OFFSET_Q U2_REG_SR_ADDR(SR_TX_FRONT + 1) //24 bits +#define U2_REG_TX_FE_MAC_CORRECTION U2_REG_SR_ADDR(SR_TX_FRONT + 2) //18 bits +#define U2_REG_TX_FE_PHASE_CORRECTION U2_REG_SR_ADDR(SR_TX_FRONT + 3) //18 bits +#define U2_REG_TX_FE_MUX U2_REG_SR_ADDR(SR_TX_FRONT + 4) //8 bits (std output = 0x10, reversed = 0x01) + +///////////////////////////////////////////////// // DSP TX Regs //////////////////////////////////////////////// #define U2_REG_DSP_TX_FREQ U2_REG_SR_ADDR(SR_TX_DSP + 0) #define U2_REG_DSP_TX_SCALE_IQ U2_REG_SR_ADDR(SR_TX_DSP + 1) #define U2_REG_DSP_TX_INTERP_RATE U2_REG_SR_ADDR(SR_TX_DSP + 2) -#define U2_REG_DSP_TX_MUX U2_REG_SR_ADDR(SR_TX_DSP + 4) ///////////////////////////////////////////////// // DSP RX Regs @@ -135,10 +152,12 @@ (U2_REG_SR_ADDR(SR_RX_DSP1 + offset))) #define U2_REG_DSP_RX_FREQ(which) U2_REG_DSP_RX_HELPER(which, 0) -#define U2_REG_DSP_RX_SCALE_IQ(which) U2_REG_DSP_RX_HELPER(which, 1) #define U2_REG_DSP_RX_DECIM(which) U2_REG_DSP_RX_HELPER(which, 2) #define U2_REG_DSP_RX_MUX(which) U2_REG_DSP_RX_HELPER(which, 5) +#define U2_FLAG_DSP_RX_MUX_SWAP_IQ (1 << 0) +#define U2_FLAG_DSP_RX_MUX_REAL_MODE (1 << 1) + //////////////////////////////////////////////// // GPIO //////////////////////////////////////////////// |