diff options
Diffstat (limited to 'host')
| -rw-r--r-- | host/lib/usrp/usrp2/clock_ctrl.cpp | 13 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/clock_ctrl.hpp | 6 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/mboard_impl.cpp | 4 | ||||
| -rwxr-xr-x | host/utils/usrp2p_fw_update.py | 12 |
4 files changed, 27 insertions, 8 deletions
diff --git a/host/lib/usrp/usrp2/clock_ctrl.cpp b/host/lib/usrp/usrp2/clock_ctrl.cpp index 72f92c081..c3dc4917e 100644 --- a/host/lib/usrp/usrp2/clock_ctrl.cpp +++ b/host/lib/usrp/usrp2/clock_ctrl.cpp @@ -212,6 +212,19 @@ public: std::vector<double> get_rates_tx_dboard_clock(void){ return get_rates_rx_dboard_clock(); //same master clock, same dividers... } + + void enable_test_clock(bool enb) { + _ad9510_regs.power_down_lvpecl_out0 = enb? + ad9510_regs_t::POWER_DOWN_LVPECL_OUT0_NORMAL : + ad9510_regs_t::POWER_DOWN_LVPECL_OUT0_SAFE_PD; + _ad9510_regs.output_level_lvpecl_out0 = ad9510_regs_t::OUTPUT_LEVEL_LVPECL_OUT0_810MV; + _ad9510_regs.divider_low_cycles_out0 = 0; + _ad9510_regs.divider_high_cycles_out0 = 0; + _ad9510_regs.bypass_divider_out0 = 1; + this->write_reg(0x3c); + this->write_reg(0x48); + this->write_reg(0x49); + } /*! * If we are to use an external reference, enable the charge pump. diff --git a/host/lib/usrp/usrp2/clock_ctrl.hpp b/host/lib/usrp/usrp2/clock_ctrl.hpp index 70a104a81..db6c52c83 100644 --- a/host/lib/usrp/usrp2/clock_ctrl.hpp +++ b/host/lib/usrp/usrp2/clock_ctrl.hpp @@ -83,6 +83,12 @@ public: * \param enb true to enable */ virtual void enable_external_ref(bool enb) = 0; + + /*! + * Enable/disable test clock output. + * \param enb true to enable + */ + virtual void enable_test_clock(bool enb) = 0; /*! * TODO other clock control api here.... diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 3ae21e621..8c5ef49ed 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -168,7 +168,6 @@ void usrp2_mboard_impl::update_clock_config(void){ default: throw std::runtime_error("usrp2: unhandled clock configuration reference source"); } } else { - switch(_clock_config.ref_source){ case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x10); break; case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break; @@ -178,7 +177,8 @@ void usrp2_mboard_impl::update_clock_config(void){ } //clock source ref 10mhz - bool use_external = _clock_config.ref_source != clock_config_t::REF_INT; + bool use_external = (_clock_config.ref_source != clock_config_t::REF_INT) + || (_iface->get_hw_rev() >= USRP2P_FIRST_HW_REV); //USRP2P has an internal 10MHz TCXO _clock_ctrl->enable_external_ref(use_external); } diff --git a/host/utils/usrp2p_fw_update.py b/host/utils/usrp2p_fw_update.py index ed3465c0e..1cd735796 100755 --- a/host/utils/usrp2p_fw_update.py +++ b/host/utils/usrp2p_fw_update.py @@ -40,12 +40,12 @@ USRP2_FW_PROTO_VERSION = 6 #from bootloader_utils.h -#define FPGA_IMAGE_SIZE_BYTES 1572864 -#define FW_IMAGE_SIZE_BYTES 31744 -#define SAFE_FPGA_IMAGE_LOCATION_ADDR 0x00000000 -#define SAFE_FW_IMAGE_LOCATION_ADDR 0x003F0000 -#define PROD_FPGA_IMAGE_LOCATION_ADDR 0x00180000 -#define PROD_FW_IMAGE_LOCATION_ADDR 0x00300000 +FPGA_IMAGE_SIZE_BYTES = 1572864 +FW_IMAGE_SIZE_BYTES = 31744 +SAFE_FPGA_IMAGE_LOCATION_ADDR = 0x00000000 +SAFE_FW_IMAGE_LOCATION_ADDR = 0x003F0000 +PROD_FPGA_IMAGE_LOCATION_ADDR = 0x00180000 +PROD_FW_IMAGE_LOCATION_ADDR = 0x00300000 FLASH_DATA_PACKET_SIZE = 256 |