diff options
Diffstat (limited to 'host')
| -rw-r--r-- | host/docs/dboards.rst | 1 | ||||
| -rw-r--r-- | host/docs/transport.rst | 2 | ||||
| -rw-r--r-- | host/examples/tx_timed_samples.cpp | 3 | ||||
| -rw-r--r-- | host/include/uhd/types/metadata.hpp | 2 | ||||
| -rwxr-xr-x | host/lib/transport/gen_vrt_if_packet.py | 1 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/mboard_impl.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/usrp_e100/clock_ctrl.cpp | 16 |
7 files changed, 20 insertions, 7 deletions
diff --git a/host/docs/dboards.rst b/host/docs/dboards.rst index 959a1b300..593dd3a42 100644 --- a/host/docs/dboards.rst +++ b/host/docs/dboards.rst @@ -265,6 +265,7 @@ The TVRX2 board has 2 real-mode subdevices. It is operated at a low IF. Receive Subdevices: + * **Subdevice RX1:** real signal on antenna J100 * **Subdevice RX2:** real signal on antenna J140 diff --git a/host/docs/transport.rst b/host/docs/transport.rst index 2371d2497..e7c2f1885 100644 --- a/host/docs/transport.rst +++ b/host/docs/transport.rst @@ -47,7 +47,7 @@ which allows the host to determine throttling conditions for the transmission of The following mechanisms affect the transmission of periodic update packets: * **ups_per_fifo:** The number of update packets for each FIFO's worth of bytes sent into the device -* **ups_per_sec:** The number of update packets per second (disabled by default) +* **ups_per_sec:** The number of update packets per second (defaults to 20 updates per second) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Resize socket buffers diff --git a/host/examples/tx_timed_samples.cpp b/host/examples/tx_timed_samples.cpp index 03f87122d..d33dc13c3 100644 --- a/host/examples/tx_timed_samples.cpp +++ b/host/examples/tx_timed_samples.cpp @@ -100,9 +100,6 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ uhd::device::SEND_MODE_ONE_PACKET, timeout ); - //use a small timeout for subsequent packets - timeout = 0.1; - //do not use time spec for subsequent packets md.has_time_spec = false; diff --git a/host/include/uhd/types/metadata.hpp b/host/include/uhd/types/metadata.hpp index f4e084430..269c77c7c 100644 --- a/host/include/uhd/types/metadata.hpp +++ b/host/include/uhd/types/metadata.hpp @@ -81,6 +81,8 @@ namespace uhd{ ERROR_CODE_BROKEN_CHAIN = 0x4, //! An internal receive buffer has filled. ERROR_CODE_OVERFLOW = 0x8, + //! Multi-channel alignment failed. + ERROR_CODE_ALIGNMENT = 0xc, //! The packet could not be parsed. ERROR_CODE_BAD_PACKET = 0xf } error_code; diff --git a/host/lib/transport/gen_vrt_if_packet.py b/host/lib/transport/gen_vrt_if_packet.py index 7df2092d8..7440def6a 100755 --- a/host/lib/transport/gen_vrt_if_packet.py +++ b/host/lib/transport/gen_vrt_if_packet.py @@ -140,6 +140,7 @@ void vrt::if_hdr_pack_$(suffix)( //fill in complete header word packet_buff[0] = $(XE_MACRO)(boost::uint32_t(0 + | (if_packet_info.packet_type << 29) | vrt_hdr_flags | ((if_packet_info.packet_count & 0xf) << 16) | (if_packet_info.num_packet_words32 & 0xffff) diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 16fbce4bd..bf1fd5cce 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -116,7 +116,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( dsp_init(); //setting the cycles per update (disabled by default) - const double ups_per_sec = device_addr.cast<double>("ups_per_sec", 0.0); + const double ups_per_sec = device_addr.cast<double>("ups_per_sec", 20); if (ups_per_sec > 0.0){ const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec); _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up); diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 49ce0c742..f1b29840a 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -180,7 +180,6 @@ public: _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC; - _ad9522_regs.divider0_ignore_sync = 1; // master FPGA clock ignores sync (always on, cannot be disabled by sync pulse) this->use_internal_ref(); @@ -438,6 +437,8 @@ private: } void calibrate_now(void){ + set_ignore_sync_fpga_plus_codec(false); //want vco cal to sync + //vco calibration routine: _ad9522_regs.vco_calibration_now = 0; this->send_reg(0x18); @@ -466,9 +467,20 @@ private: _ad9522_regs.get_read_reg(addr), 24 ); _ad9522_regs.set_reg(addr, reg); - if (_ad9522_regs.digital_lock_detect) return; + if (_ad9522_regs.digital_lock_detect) goto finalize; } UHD_MSG(error) << "USRP-E100 clock control: lock detection timeout" << std::endl; + finalize: + + set_ignore_sync_fpga_plus_codec(true); //never loose sync between these two + } + + void set_ignore_sync_fpga_plus_codec(bool enb){ + _ad9522_regs.divider0_ignore_sync = (enb)?1:0; // master FPGA clock ignores sync (always on, cannot be disabled by sync pulse) + _ad9522_regs.divider1_ignore_sync = (enb)?1:0; // codec clock ignores sync (always on, cannot be disabled by sync pulse) + this->send_reg(0x191); + this->send_reg(0x194); + this->latch_regs(); } void soft_sync(void){ |