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-rw-r--r--host/include/uhd/stream.hpp5
-rw-r--r--host/lib/usrp/b100/b100_impl.hpp2
-rw-r--r--host/lib/usrp/b100/io_impl.cpp2
-rw-r--r--host/lib/usrp/cores/rx_dsp_core_200.cpp33
-rw-r--r--host/lib/usrp/cores/tx_dsp_core_200.cpp4
-rw-r--r--host/lib/usrp/e100/e100_impl.hpp2
-rw-r--r--host/lib/usrp/e100/io_impl.cpp2
-rw-r--r--host/lib/usrp/usrp2/fw_common.h4
-rw-r--r--host/lib/usrp/usrp2/io_impl.cpp2
9 files changed, 35 insertions, 21 deletions
diff --git a/host/include/uhd/stream.hpp b/host/include/uhd/stream.hpp
index 352f63e4e..0c9282545 100644
--- a/host/include/uhd/stream.hpp
+++ b/host/include/uhd/stream.hpp
@@ -80,8 +80,9 @@ struct UHD_API stream_args_t{
* Possible keys used by args (depends on implementation):
*
* - scalar: an integer scaling factor used with the sc8 wire format.
- * The key/value pair scalar=1024 means that the sample in the DSP
- * was multiplied by 1024 before its upper 8 bits were harvested.
+ * Use scalar=1 to harvest the lower 8-bits.
+ * Use scalar=256 to harvest the upper 8-bits.
+ * Any scalar in-between is also a possibility.
*
* - underflow_policy: how the TX DSP should recover from underflow.
* Possible options are "next_burst" or "next_packet".
diff --git a/host/lib/usrp/b100/b100_impl.hpp b/host/lib/usrp/b100/b100_impl.hpp
index 96d90b14c..310daa842 100644
--- a/host/lib/usrp/b100/b100_impl.hpp
+++ b/host/lib/usrp/b100/b100_impl.hpp
@@ -47,7 +47,7 @@ static const double B100_LINK_RATE_BPS = 256e6/8; //pratical link rate
static const std::string B100_FW_FILE_NAME = "usrp_b100_fw.ihx";
static const std::string B100_FPGA_FILE_NAME = "usrp_b100_fpga.bin";
static const boost::uint16_t B100_FW_COMPAT_NUM = 0x02;
-static const boost::uint16_t B100_FPGA_COMPAT_NUM = 0x08;
+static const boost::uint16_t B100_FPGA_COMPAT_NUM = 0x09;
static const boost::uint32_t B100_RX_SID_BASE = 2;
static const boost::uint32_t B100_TX_ASYNC_SID = 1;
static const double B100_DEFAULT_TICK_RATE = 64e6;
diff --git a/host/lib/usrp/b100/io_impl.cpp b/host/lib/usrp/b100/io_impl.cpp
index 494d5d123..c98f71754 100644
--- a/host/lib/usrp/b100/io_impl.cpp
+++ b/host/lib/usrp/b100/io_impl.cpp
@@ -202,7 +202,7 @@ rx_streamer::sptr b100_impl::get_rx_stream(const uhd::stream_args_t &args_){
//setup defaults for unspecified values
args.otw_format = args.otw_format.empty()? "sc16" : args.otw_format;
args.channels = args.channels.empty()? std::vector<size_t>(1, 0) : args.channels;
- const unsigned sc8_scalar = unsigned(args.args.cast<double>("scalar", 0x400));
+ const unsigned sc8_scalar = unsigned(args.args.cast<double>("scalar", 1));
//calculate packet size
static const size_t hdr_size = 0
diff --git a/host/lib/usrp/cores/rx_dsp_core_200.cpp b/host/lib/usrp/cores/rx_dsp_core_200.cpp
index 2e21cc895..cbc732c9c 100644
--- a/host/lib/usrp/cores/rx_dsp_core_200.cpp
+++ b/host/lib/usrp/cores/rx_dsp_core_200.cpp
@@ -18,6 +18,7 @@
#include "rx_dsp_core_200.hpp"
#include <uhd/types/dict.hpp>
#include <uhd/exception.hpp>
+#include <uhd/utils/msg.hpp>
#include <uhd/utils/algorithm.hpp>
#include <boost/assign/list_of.hpp>
#include <boost/thread/thread.hpp> //thread sleep
@@ -27,7 +28,7 @@
#include <cmath>
#define REG_DSP_RX_FREQ _dsp_base + 0
-//skip one right here
+#define REG_DSP_RX_SCALE_IQ _dsp_base + 4
#define REG_DSP_RX_DECIM _dsp_base + 8
#define REG_DSP_RX_MUX _dsp_base + 12
@@ -60,6 +61,11 @@ public:
):
_iface(iface), _dsp_base(dsp_base), _ctrl_base(ctrl_base), _sid(sid)
{
+ //init to something so update method has reasonable defaults
+ _scaling_adjustment = 1.0;
+ _extra_scaling = 1.0;
+ _fxpt_scalar_correction = 1.0;
+
//This is a hack/fix for the lingering packet problem.
//The caller should also flush the recv transports
if (lingering_packet){
@@ -175,12 +181,20 @@ public:
// Calculate closest multiplier constant to reverse gain absent scale multipliers
const double rate_pow = std::pow(double(decim & 0xff), 4);
_scaling_adjustment = std::pow(2, ceil_log2(rate_pow))/(1.65*rate_pow);
+ this->update_scalar();
return _tick_rate/decim_rate;
}
+ void update_scalar(void){
+ const double target_scalar = (1 << 16)*_scaling_adjustment/_extra_scaling;
+ const boost::int32_t actual_scalar = boost::math::iround(target_scalar);
+ _fxpt_scalar_correction = target_scalar/actual_scalar; //should be small
+ _iface->poke32(REG_DSP_RX_SCALE_IQ, actual_scalar);
+ }
+
double get_scaling_adjustment(void){
- return _scaling_adjustment/_fxpt_scale_adj;
+ return _fxpt_scalar_correction*_extra_scaling/32767.;
}
double set_freq(const double freq_){
@@ -214,18 +228,17 @@ public:
unsigned format_word = 0;
if (format == "sc16"){
format_word = 0;
- _fxpt_scale_adj = 32767.;
+ _extra_scaling = 1.0;
}
else if (format == "sc8"){
- format_word = (1 << 18);
- _fxpt_scale_adj = 127. * scale;
- _fxpt_scale_adj /= 256; //engine 16to8 drops lower 8 bits
- _fxpt_scale_adj /= 4; //scale operation 2-bit pad
+ format_word = (1 << 0);
+ _extra_scaling = scale;
}
else throw uhd::value_error("USRP RX cannot handle requested wire format: " + format);
- const unsigned scale_word = scale & 0x3ffff; //18 bits;
- _iface->poke32(REG_RX_CTRL_FORMAT, format_word | scale_word);
+ this->update_scalar();
+
+ _iface->poke32(REG_RX_CTRL_FORMAT, format_word);
}
private:
@@ -233,7 +246,7 @@ private:
const size_t _dsp_base, _ctrl_base;
double _tick_rate, _link_rate;
bool _continuous_streaming;
- double _scaling_adjustment, _fxpt_scale_adj;
+ double _scaling_adjustment, _extra_scaling, _fxpt_scalar_correction;
const boost::uint32_t _sid;
};
diff --git a/host/lib/usrp/cores/tx_dsp_core_200.cpp b/host/lib/usrp/cores/tx_dsp_core_200.cpp
index c5de4e361..f4c303d05 100644
--- a/host/lib/usrp/cores/tx_dsp_core_200.cpp
+++ b/host/lib/usrp/cores/tx_dsp_core_200.cpp
@@ -122,8 +122,8 @@ public:
// Calculate CIC interpolation (i.e., without halfband interpolators)
// Calculate closest multiplier constant to reverse gain absent scale multipliers
double rate_cubed = std::pow(double(interp & 0xff), 3);
- const boost::int16_t scale = boost::math::iround((4096*std::pow(2, ceil_log2(rate_cubed)))/(1.65*rate_cubed));
- _iface->poke32(REG_DSP_TX_SCALE_IQ, (boost::uint32_t(scale) << 16) | (boost::uint32_t(scale) << 0));
+ const boost::int32_t scale = boost::math::iround((4096*std::pow(2, ceil_log2(rate_cubed)))/(1.65*rate_cubed));
+ _iface->poke32(REG_DSP_TX_SCALE_IQ, scale);
return _tick_rate/interp_rate;
}
diff --git a/host/lib/usrp/e100/e100_impl.hpp b/host/lib/usrp/e100/e100_impl.hpp
index 2ea890375..f94061a24 100644
--- a/host/lib/usrp/e100/e100_impl.hpp
+++ b/host/lib/usrp/e100/e100_impl.hpp
@@ -48,7 +48,7 @@ static const double E100_RX_LINK_RATE_BPS = 166e6/3/2*2;
static const double E100_TX_LINK_RATE_BPS = 166e6/3/1*2;
static const std::string E100_I2C_DEV_NODE = "/dev/i2c-3";
static const std::string E100_UART_DEV_NODE = "/dev/ttyO0";
-static const boost::uint16_t E100_FPGA_COMPAT_NUM = 0x08;
+static const boost::uint16_t E100_FPGA_COMPAT_NUM = 0x09;
static const boost::uint32_t E100_RX_SID_BASE = 2;
static const boost::uint32_t E100_TX_ASYNC_SID = 1;
static const double E100_DEFAULT_CLOCK_RATE = 64e6;
diff --git a/host/lib/usrp/e100/io_impl.cpp b/host/lib/usrp/e100/io_impl.cpp
index 441e32a8d..97f4db6f1 100644
--- a/host/lib/usrp/e100/io_impl.cpp
+++ b/host/lib/usrp/e100/io_impl.cpp
@@ -278,7 +278,7 @@ rx_streamer::sptr e100_impl::get_rx_stream(const uhd::stream_args_t &args_){
//setup defaults for unspecified values
args.otw_format = args.otw_format.empty()? "sc16" : args.otw_format;
args.channels = args.channels.empty()? std::vector<size_t>(1, 0) : args.channels;
- const unsigned sc8_scalar = unsigned(args.args.cast<double>("scalar", 0x400));
+ const unsigned sc8_scalar = unsigned(args.args.cast<double>("scalar", 1));
//calculate packet size
static const size_t hdr_size = 0
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index 1af1db860..0babf7445 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -30,9 +30,9 @@ extern "C" {
#endif
//fpga and firmware compatibility numbers
-#define USRP2_FPGA_COMPAT_NUM 8
+#define USRP2_FPGA_COMPAT_NUM 9
#define USRP2_FW_COMPAT_NUM 11
-#define USRP2_FW_VER_MINOR 1
+#define USRP2_FW_VER_MINOR 2
//used to differentiate control packets over data port
#define USRP2_INVALID_VRT_HEADER 0
diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp
index e3fa46920..5f5369f7d 100644
--- a/host/lib/usrp/usrp2/io_impl.cpp
+++ b/host/lib/usrp/usrp2/io_impl.cpp
@@ -380,7 +380,7 @@ rx_streamer::sptr usrp2_impl::get_rx_stream(const uhd::stream_args_t &args_){
//setup defaults for unspecified values
args.otw_format = args.otw_format.empty()? "sc16" : args.otw_format;
args.channels = args.channels.empty()? std::vector<size_t>(1, 0) : args.channels;
- const unsigned sc8_scalar = unsigned(args.args.cast<double>("scalar", 0x400));
+ const unsigned sc8_scalar = unsigned(args.args.cast<double>("scalar", 1));
//calculate packet size
static const size_t hdr_size = 0
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 12:04:35 +0000