diff options
Diffstat (limited to 'host/utils')
| -rw-r--r-- | host/utils/CMakeLists.txt | 24 | ||||
| -rw-r--r-- | host/utils/clkgen-config.cpp | 296 | ||||
| -rw-r--r-- | host/utils/fpga-downloader.cpp | 267 | ||||
| -rw-r--r-- | host/utils/usrp-e-debug-pins.c | 77 | ||||
| -rw-r--r-- | host/utils/usrp-e-i2c.c | 87 | ||||
| -rw-r--r-- | host/utils/usrp-e-loopback.c | 231 | ||||
| -rw-r--r-- | host/utils/usrp-e-spi.c | 54 | ||||
| -rw-r--r-- | host/utils/usrp_e_regs.hpp | 196 |
8 files changed, 1232 insertions, 0 deletions
diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index f0fa806c5..a9148de6d 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -24,9 +24,33 @@ TARGET_LINK_LIBRARIES(uhd_find_devices uhd) ADD_EXECUTABLE(uhd_usrp_probe uhd_usrp_probe.cpp) TARGET_LINK_LIBRARIES(uhd_usrp_probe uhd) +ADD_EXECUTABLE(fpga-downloader fpga-downloader.cpp) +TARGET_LINK_LIBRARIES(fpga-downloader) + +ADD_EXECUTABLE(clkgen-config clkgen-config.cpp) +TARGET_LINK_LIBRARIES(clkgen-config) + +ADD_EXECUTABLE(usrp-e-loopback usrp-e-loopback.c) +TARGET_LINK_LIBRARIES(usrp-e-loopback pthread) + +ADD_EXECUTABLE(usrp-e-debug-pins usrp-e-debug-pins.c) +TARGET_LINK_LIBRARIES(usrp-e-debug-pins) + +ADD_EXECUTABLE(usrp-e-i2c usrp-e-i2c.c) +TARGET_LINK_LIBRARIES(usrp-e-i2c) + +ADD_EXECUTABLE(usrp-e-spi usrp-e-spi.c) +TARGET_LINK_LIBRARIES(usrp-e-spi) + INSTALL(TARGETS uhd_find_devices uhd_usrp_probe + fpga-downloader + usrp-e-loopback + usrp-e-debug-pins + usrp-e-spi + usrp-e-i2c + clkgen-config RUNTIME DESTINATION ${RUNTIME_DIR} ) diff --git a/host/utils/clkgen-config.cpp b/host/utils/clkgen-config.cpp new file mode 100644 index 000000000..e8279b4ae --- /dev/null +++ b/host/utils/clkgen-config.cpp @@ -0,0 +1,296 @@ +/* -*- c++ -*- */ +/* + * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc. + * + * This file is part of UHD + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. +*/ + +#include <iostream> +#include <sstream> +#include <fstream> +#include <string> +#include <cstdlib> + +#include <fcntl.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/ioctl.h> + +#include <linux/spi/spidev.h> + + +// Programming data for clock gen chip +static const unsigned int config_data[] = { + 0x000024, + 0x023201, + 0x000081, + 0x000400, + 0x00104c, + 0x001101, + 0x001200, + 0x001300, + 0x001414, + 0x001500, + 0x001604, + 0x001704, + 0x001807, + 0x001900, + //0x001a00,//for debug + 0x001a32, + 0x001b12, + 0x001c44, + 0x001d00, + 0x001e00, + 0x00f062, + 0x00f162, + 0x00f262, + 0x00f362, + 0x00f462, + 0x00f562, + 0x00f662, + 0x00f762, + 0x00f862, + 0x00f962, + 0x00fa62, + 0x00fb62, + 0x00fc00, + 0x00fd00, + 0x019021, + 0x019100, + 0x019200, + 0x019333, + 0x019400, + 0x019500, + 0x019611, + 0x019700, + 0x019800, + 0x019900, + 0x019a00, + 0x019b00, + 0x01e003, + 0x01e102, + 0x023000, + 0x023201, + 0x0b0201, + 0x0b0300, + 0x001fff, + 0x0a0000, + 0x0a0100, + 0x0a0200, + 0x0a0302, + 0x0a0400, + 0x0a0504, + 0x0a060e, + 0x0a0700, + 0x0a0810, + 0x0a090e, + 0x0a0a00, + 0x0a0bf0, + 0x0a0c0b, + 0x0a0d01, + 0x0a0e90, + 0x0a0f01, + 0x0a1001, + 0x0a11e0, + 0x0a1201, + 0x0a1302, + 0x0a1430, + 0x0a1580, + 0x0a16ff, + 0x023201, + 0x0b0301, + 0x023201, +}; + + +const unsigned int CLKGEN_SELECT = 145; + + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action); + ~gpio(); + + bool get_value(); + void set_value(bool state); + + private: + + unsigned int gpio_num; + + std::stringstream base_path; + std::fstream value_file; + std::fstream direction_file; + bool close_action; // True set to input and release, false do nothing +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action) +{ + std::fstream export_file; + + gpio_num = _gpio_num; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +gpio::~gpio() +{ + if (close_action) { + std::fstream unexport_file; + + direction_file << "in" << std::endl; + + unexport_file.open("/sys/class/gpio/unexport", std::ios::out); + if (!unexport_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + unexport_file << gpio_num << std::endl; + + } + +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000; + int bits = 24; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 12000000; + tr.bits_per_word = 24; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_config_to_clkgen(gpio &chip_select, const unsigned int data[], unsigned int data_size) +{ + spidev spi("/dev/spidev1.0"); + unsigned int rbuf; + + for (unsigned int i = 0; i < data_size; i++) { + + std::cout << "sending " << std::hex << data[i] << std::endl; + chip_select.set_value(0); + spi.send((char *)&data[i], (char *)&rbuf, 4); + chip_select.set_value(1); + + }; +} + +int main(int argc, char *argv[]) +{ + + gpio clkgen_select(CLKGEN_SELECT, OUT, true); + + send_config_to_clkgen(clkgen_select, config_data, sizeof(config_data)/sizeof(unsigned int)); +} + diff --git a/host/utils/fpga-downloader.cpp b/host/utils/fpga-downloader.cpp new file mode 100644 index 000000000..80ee71600 --- /dev/null +++ b/host/utils/fpga-downloader.cpp @@ -0,0 +1,267 @@ +/* -*- c++ -*- */ +/* + * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. +*/ + +#include <iostream> +#include <sstream> +#include <fstream> +#include <string> +#include <cstdlib> + +#include <fcntl.h> +#include <errno.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/ioctl.h> + +#include <linux/spi/spidev.h> + +/* + * Configuration connections + * + * CCK - MCSPI1_CLK + * DIN - MCSPI1_MOSI + * PROG_B - GPIO_175 - output (change mux) + * DONE - GPIO_173 - input (change mux) + * INIT_B - GPIO_114 - input (change mux) + * +*/ + +const unsigned int PROG_B = 175; +const unsigned int DONE = 173; +const unsigned int INIT_B = 114; + +static std::string bit_file = "safe_u1e.bin"; + +const int BUF_SIZE = 4096; + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction); + + bool get_value(); + void set_value(bool state); + + private: + + std::stringstream base_path; + std::fstream value_file; +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) +{ + std::fstream export_file; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::fstream direction_file; + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +static void prepare_fpga_for_configuration(gpio &prog, gpio &init) +{ + + prog.set_value(true); + prog.set_value(false); + prog.set_value(true); + +#if 0 + bool ready_to_program(false); + unsigned int count(0); + do { + ready_to_program = init.get_value(); + count++; + + sleep(1); + } while (count < 10 && !ready_to_program); + + if (count == 10) { + std::cout << "FPGA not ready for programming." << std::endl; + exit(-1); + } +#endif +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000000; + int bits = 8; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 48000000; + tr.bits_per_word = 8; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_file_to_fpga(std::string &file_name, gpio &error, gpio &done) +{ + std::ifstream bitstream; + + std::cout << "File name - " << file_name.c_str() << std::endl; + + bitstream.open(file_name.c_str(), std::ios::binary); + if (!bitstream.is_open()) + std::cout << "File " << file_name << " not opened succesfully." << std::endl; + + spidev spi("/dev/spidev1.0"); + char buf[BUF_SIZE]; + char rbuf[BUF_SIZE]; + + do { + bitstream.read(buf, BUF_SIZE); + spi.send(buf, rbuf, bitstream.gcount()); + + if (error.get_value()) + std::cout << "INIT_B went high, error occured." << std::endl; + + if (!done.get_value()) + std::cout << "Configuration complete." << std::endl; + + } while (bitstream.gcount() == BUF_SIZE); +} + +int main(int argc, char *argv[]) +{ + + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + if (argc == 2) + bit_file = argv[1]; + + bool module_found(false); + std::ifstream mod_file("/proc/modules"); + while (!mod_file.eof()) { + std::string line; + getline(mod_file, line); + if (line.find("usrp_e") != std::string::npos) + module_found = true; + } + mod_file.close(); + + if (module_found) { + std::cout << "USRP Embedded kernel module loaded, not loading FPGA." << std::endl; + return -1; + } + + std::cout << "FPGA config file: " << bit_file << std::endl; + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "Done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bit_file, gpio_init_b, gpio_done); +} + diff --git a/host/utils/usrp-e-debug-pins.c b/host/utils/usrp-e-debug-pins.c new file mode 100644 index 000000000..1ed2c8983 --- /dev/null +++ b/host/utils/usrp-e-debug-pins.c @@ -0,0 +1,77 @@ +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <sys/types.h> +#include <fcntl.h> +#include <string.h> +#include <sys/ioctl.h> + +#include <linux/usrp_e.h> +#include "usrp_e_regs.hpp" + +// Usage: usrp_e_gpio <string> + +static int fp; + +static int read_reg(__u16 reg) +{ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + ret = ioctl(fp, USRP_E_READ_CTL16, &d); + return d.buf[0]; +} + +static void write_reg(__u16 reg, __u16 val) +{ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + d.buf[0] = val; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); +} + +int main(int argc, char *argv[]) +{ + int test; + + test = 0; + if (argc < 2) { + printf("%s 0|1|off\n", argv[0]); + } + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } + + if (strcmp(argv[1], "0") == 0) { + printf("Selected 0 based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_TX_SEL, 0x0); + write_reg(UE_REG_GPIO_RX_SEL, 0x0); + write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF); + } else if (strcmp(argv[1], "1") == 0) { + printf("Selected 1 based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_TX_SEL, 0xFFFF); + write_reg(UE_REG_GPIO_RX_SEL, 0xFFFF); + write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF); + } else { + printf("Selected off based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0x0); + write_reg(UE_REG_GPIO_RX_DDR, 0x0); + } + + return 0; +} diff --git a/host/utils/usrp-e-i2c.c b/host/utils/usrp-e-i2c.c new file mode 100644 index 000000000..c6fd4c632 --- /dev/null +++ b/host/utils/usrp-e-i2c.c @@ -0,0 +1,87 @@ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <sys/types.h> +#include <fcntl.h> +#include <sys/ioctl.h> + +#include <linux/usrp_e.h> + +// Usage: usrp_e_i2c w address data0 data1 data 2 .... +// Usage: usrp_e_i2c r address count + +int main(int argc, char *argv[]) +{ + int fp, ret, i, tmp; + struct usrp_e_i2c *i2c_msg; + int direction, address, count; + + if (argc < 3) { + printf("Usage: usrp-e-i2c w address data0 data1 data2 ...\n"); + printf("Usage: usrp-e-i2c r address count\n"); + printf("All addresses and data in hex.\n"); + exit(-1); + } + + if (strcmp(argv[1], "r") == 0) { + direction = 0; + } else if (strcmp(argv[1], "w") == 0) { + direction = 1; + } else { + return -1; + } + + sscanf(argv[2], "%X", &address); + printf("Address = %X\n", address); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } + +// sleep(1); + + if (direction) { + count = argc - 3; + } else { + sscanf(argv[3], "%X", &count); + } + printf("Count = %X\n", count); + + i2c_msg = malloc(sizeof(i2c_msg) + count * sizeof(char)); + + i2c_msg->addr = address; + i2c_msg->len = count; + + for (i = 0; i < count; i++) { + i2c_msg->data[i] = i; + } + + if (direction) { + // Write + + for (i=0; i<count; i++) { + sscanf(argv[3+i], "%X", &tmp); + i2c_msg->data[i] = tmp; + } + + ret = ioctl(fp, USRP_E_I2C_WRITE, i2c_msg); + printf("Return value from i2c_write ioctl: %d\n", ret); + } else { + // Read + + ret = ioctl(fp, USRP_E_I2C_READ, i2c_msg); + printf("Return value from i2c_read ioctl: %d\n", ret); + + printf("Ioctl: %d Data read :", ret); + for (i=0; i<count; i++) { + printf(" %X", i2c_msg->data[i]); + } + printf("\n"); + + } + return 0; +} diff --git a/host/utils/usrp-e-loopback.c b/host/utils/usrp-e-loopback.c new file mode 100644 index 000000000..454d81ba7 --- /dev/null +++ b/host/utils/usrp-e-loopback.c @@ -0,0 +1,231 @@ +#include <stdio.h> +#include <sys/types.h> +#include <fcntl.h> +#include <pthread.h> +#include <stdlib.h> +#include <unistd.h> +#include <stddef.h> +#include <sys/mman.h> +#include <linux/usrp_e.h> + +#define MAX_PACKET_SIZE 1016 +static int packet_data_length; +static int error; + +struct pkt { + int len; + int checksum; + int seq_num; + short data[]; +}; + +static int length_array[2048]; +static int length_array_tail = 0; +static int length_array_head = 0; + +pthread_mutex_t length_array_mutex; //gotta lock the index to keep it from getting hosed + +//yes this is a circular buffer that does not check empty +//no i don't want to hear about it +void push_length_array(int length) { + pthread_mutex_lock(&length_array_mutex); + if(length_array_tail > 2047) length_array_tail = 0; + length_array[length_array_tail++] = length; + pthread_mutex_unlock(&length_array_mutex); +} + +int pop_length_array(void) { + int retval; + pthread_mutex_lock(&length_array_mutex); + if(length_array_head > 2047) length_array_head = 0; + retval = length_array[length_array_head++]; + pthread_mutex_unlock(&length_array_mutex); + return retval; +} + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i < p->len; i++) + sum ^= p->data[i]; + + sum ^= p->seq_num; + sum ^= p->len; + + return sum; +} + +static void *read_thread(void *threadid) +{ + char *rx_data; + int cnt, prev_seq_num, pkt_count, seq_num_failure; + struct pkt *p; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; + int expected_count; + + printf("Greetings from the reading thread!\n"); + + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(2048); + p = (struct pkt *) ((void *)rx_data); + + prev_seq_num = 0; + pkt_count = 0; + seq_num_failure = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); + if (cnt < 0) + printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); + +// printf("p->seq_num = %d\n", p->seq_num); + + + pkt_count++; + + if (p->seq_num != prev_seq_num + 1) { + printf("Sequence number fail, current = %d, previous = %d, pkt_count = %d\n", + p->seq_num, prev_seq_num, pkt_count); + + seq_num_failure ++; + if (seq_num_failure > 2) + error = 1; + } + + expected_count = pop_length_array()*2+12; + if(cnt != expected_count) { + printf("Received %d bytes, expected %d\n", cnt, expected_count); + } + + prev_seq_num = p->seq_num; + + if (calc_checksum(p) != p->checksum) { + printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", + calc_checksum(p), p->checksum, pkt_count); + error = 1; + } + + bytes_transfered += cnt; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + + printf("RX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 4000); + + + start_time = finish_time; + bytes_transfered = 0; + } + + +// printf("."); +// fflush(stdout); +// printf("\n"); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt; + void *tx_data; + struct pkt *p; + + printf("Greetings from the write thread!\n"); + + tx_data = malloc(2048); + p = (struct pkt *) ((void *)tx_data); + + for (i=0; i < packet_data_length; i++) +// p->data[i] = random() >> 16; + p->data[i] = i; + + seq_number = 1; + + while (1) { + p->seq_num = seq_number++; + + if (packet_data_length > 0) + p->len = packet_data_length; + else + p->len = (random()<<1 & 0x1ff) + (1004 - 512); + + push_length_array(p->len); + + p->checksum = calc_checksum(p); + + cnt = write(fp, tx_data, p->len * 2 + 12); + if (cnt < 0) + printf("Error returned from write: %d\n", cnt); +// sleep(1); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + pthread_mutex_init(&length_array_mutex, 0); + long int t; + struct sched_param s = { + .sched_priority = 1 + }; + void *rb; + struct usrp_transfer_frame *tx_rb, *rx_rb; + + if (argc < 2) { + printf("%s data_size\n", argv[0]); + return -1; + } + + packet_data_length = atoi(argv[1]); + if(packet_data_length > MAX_PACKET_SIZE) { + printf("Packet size must be smaller than %i\n", MAX_PACKET_SIZE); + exit(-1); + } + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + rb = mmap(0, 202 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); + if (!rb) { + printf("mmap failed\n"); + exit; + } + + + sched_setscheduler(0, SCHED_RR, &s); + error = 0; + +#if 1 + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + + sleep(1); +#endif + + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + +// while (!error) + sleep(1000000000); + + printf("Done sleeping\n"); +} diff --git a/host/utils/usrp-e-spi.c b/host/utils/usrp-e-spi.c new file mode 100644 index 000000000..5203f56a8 --- /dev/null +++ b/host/utils/usrp-e-spi.c @@ -0,0 +1,54 @@ +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <sys/types.h> +#include <fcntl.h> +#include <sys/ioctl.h> + +#include <linux/usrp_e.h> + +// Usage: usrp_e_spi w|rb slave data + +int main(int argc, char *argv[]) +{ + int fp, slave, length, ret; + unsigned int data; + struct usrp_e_spi spi_dat; + + if (argc < 5) { + printf("Usage: usrp_e_spi w|rb slave transfer_length data\n"); + exit(-1); + } + + slave = atoi(argv[2]); + length = atoi(argv[3]); + data = atoll(argv[4]); + + printf("Data = %X\n", data); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } + +// sleep(1); + + + spi_dat.slave = slave; + spi_dat.data = data; + spi_dat.length = length; + spi_dat.flags = UE_SPI_PUSH_FALL | UE_SPI_LATCH_RISE; + + if (*argv[1] == 'r') { + spi_dat.readback = 1; + ret = ioctl(fp, USRP_E_SPI, &spi_dat); + printf("Ioctl returns: %d, Data returned = %d\n", ret, spi_dat.data); + } else { + spi_dat.readback = 0; + ioctl(fp, USRP_E_SPI, &spi_dat); + } + + return 0; +} diff --git a/host/utils/usrp_e_regs.hpp b/host/utils/usrp_e_regs.hpp new file mode 100644 index 000000000..a4f42093e --- /dev/null +++ b/host/utils/usrp_e_regs.hpp @@ -0,0 +1,196 @@ + + +//////////////////////////////////////////////////////////////// +// +// Memory map for embedded wishbone bus +// +//////////////////////////////////////////////////////////////// + +// All addresses are byte addresses. All accesses are word (16-bit) accesses. +// This means that address bit 0 is usually 0. +// There are 11 bits of address for the control. + +#ifndef __USRP_E_REGS_H +#define __USRP_E_REGS_H + +///////////////////////////////////////////////////// +// Slave pointers + +#define UE_REG_SLAVE(n) ((n)<<7) +#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) + +///////////////////////////////////////////////////// +// Slave 0 -- Misc Regs + +#define UE_REG_MISC_BASE UE_REG_SLAVE(0) + +#define UE_REG_MISC_LED UE_REG_MISC_BASE + 0 +#define UE_REG_MISC_SW UE_REG_MISC_BASE + 2 +#define UE_REG_MISC_CGEN_CTRL UE_REG_MISC_BASE + 4 +#define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 +#define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 +#define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 +#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 + +///////////////////////////////////////////////////// +// Slave 1 -- UART +// CLKDIV is 16 bits, others are only 8 + +#define UE_REG_UART_BASE UE_REG_SLAVE(1) + +#define UE_REG_UART_CLKDIV UE_REG_UART_BASE + 0 +#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2 +#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4 +#define UE_REG_UART_TXCHAR UE_REG_UART_BASE + 6 +#define UE_REG_UART_RXCHAR UE_REG_UART_BASE + 8 + +///////////////////////////////////////////////////// +// Slave 2 -- SPI Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_SPI_BASE UE_REG_SLAVE(2) + +//spi slave constants +#define UE_SPI_SS_AD9522 (1 << 3) +#define UE_SPI_SS_AD9862 (1 << 2) +#define UE_SPI_SS_TX_DB (1 << 1) +#define UE_SPI_SS_RX_DB (1 << 0) + +//////////////////////////////////////////////// +// Slave 3 -- I2C Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_I2C_BASE UE_REG_SLAVE(3) + + +//////////////////////////////////////////////// +// Slave 4 -- GPIO + +#define UE_REG_GPIO_BASE UE_REG_SLAVE(4) + +#define UE_REG_GPIO_RX_IO UE_REG_GPIO_BASE + 0 +#define UE_REG_GPIO_TX_IO UE_REG_GPIO_BASE + 2 +#define UE_REG_GPIO_RX_DDR UE_REG_GPIO_BASE + 4 +#define UE_REG_GPIO_TX_DDR UE_REG_GPIO_BASE + 6 +#define UE_REG_GPIO_RX_SEL UE_REG_GPIO_BASE + 8 +#define UE_REG_GPIO_TX_SEL UE_REG_GPIO_BASE + 10 +#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12 +#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14 + +//possible bit values for sel when dbg is 0: +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic + +//possible bit values for sel when dbg is 1: +#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric + + +//////////////////////////////////////////////////// +// Slave 5 -- Settings Bus +// +// Output-only, no readback, 32 registers total +// Each register must be written 32 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) + +/////////////////////////////////////////////////// +// Slave 6 -- ATR Controller +// 16 regs + +#define UE_REG_ATR_BASE UE_REG_SLAVE(6) + +#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 +#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 +#define UE_REG_ATR_INTX_RXSIDE UE_REG_ATR_BASE + 4 +#define UE_REG_ATR_INTX_TXSIDE UE_REG_ATR_BASE + 6 +#define UE_REG_ATR_INRX_RXSIDE UE_REG_ATR_BASE + 8 +#define UE_REG_ATR_INRX_TXSIDE UE_REG_ATR_BASE + 10 +#define UE_REG_ATR_FULL_RXSIDE UE_REG_ATR_BASE + 12 +#define UE_REG_ATR_FULL_TXSIDE UE_REG_ATR_BASE + 14 + +///////////////////////////////////////////////// +// DSP RX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) +#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate +#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) + +/////////////////////////////////////////////////// +// VITA RX CTRL regs +/////////////////////////////////////////////////// +// The following 3 are logically a single command register. +// They are clocked into the underlying fifo when time_ticks is written. +#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) +#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) +#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) +#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun +#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter +#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. +#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) +#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) +#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources + +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) +#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} +#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) +#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) +#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) + +///////////////////////////////////////////////// +// VITA TX CTRL regs +//////////////////////////////////////////////// +#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) +#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) +#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) +#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) + +#define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) + +///////////////////////////////////////////////// +// VITA49 64 bit time (write only) +//////////////////////////////////////////////// + /*! + * \brief Time 64 flags + * + * <pre> + * + * 3 2 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------------------------------------------------------+-+-+ + * | |S|P| + * +-----------------------------------------------------------+-+-+ + * + * P - PPS edge selection (0=negedge, 1=posedge, default=0) + * S - Source (0=sma, 1=mimo, 0=default) + * + * </pre> + */ +#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS +#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS +#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above +#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) + +//pps flags (see above) +#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) +#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0) +#define UE_FLAG_TIME64_PPS_SMA (0 << 1) +#define UE_FLAG_TIME64_PPS_MIMO (1 << 1) + +#define UE_FLAG_TIME64_LATCH_NOW 1 +#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0 + +#endif + |