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-rw-r--r--host/lib/CMakeLists.txt1
-rwxr-xr-xhost/lib/ic_reg_maps/gen_adf4350_regs.py36
-rw-r--r--host/lib/usrp/dboard/db_wbx.cpp332
3 files changed, 231 insertions, 138 deletions
diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt
index b603a9deb..a0b2d67fc 100644
--- a/host/lib/CMakeLists.txt
+++ b/host/lib/CMakeLists.txt
@@ -130,6 +130,7 @@ LIST(APPEND libuhd_sources
usrp/dboard/db_basic_and_lf.cpp
usrp/dboard/db_rfx.cpp
usrp/dboard/db_xcvr2450.cpp
+ usrp/dboard/db_wbx.cpp
)
########################################################################
diff --git a/host/lib/ic_reg_maps/gen_adf4350_regs.py b/host/lib/ic_reg_maps/gen_adf4350_regs.py
index 71178ff84..924139936 100755
--- a/host/lib/ic_reg_maps/gen_adf4350_regs.py
+++ b/host/lib/ic_reg_maps/gen_adf4350_regs.py
@@ -29,14 +29,14 @@ REGS_DATA_TMPL="""\
########################################################################
frac_12_bit 0[3:14] 0
int_16_bit 0[15:30] 23
-reserved 0[31] 0
+##reserved 0[31] 0
########################################################################
## address 1
########################################################################
-mod_12_bit 1[3:14] 4095
-phase_12_bit 1[15:26] 0
-prescaler 1[27] 0
-reserved 1[28:31] 0
+mod_12_bit 1[3:14] fff
+phase_12_bit 1[15:26] 1
+prescaler 1[27] 0 4_5, 8_9
+##reserved 1[28:31] 0
########################################################################
## address 2
########################################################################
@@ -53,16 +53,16 @@ r_counter_10_bit 2[14:23] 0
reference_divide_by_2 2[24] 1 disabled, enabled
reference_doubler 2[25] 0 disabled, enabled
muxout 2[26:28] 3 3state, dvdd, dgnd, rdiv, ndiv, analog_ld, dld, reserved
-low_noise_and_spur 2[29:30] 3 low_noise, reserved, reserved, low_spur
+low_noise_and_spur 2[29:30] 3 low_noise, reserved0, reserved1, low_spur
########################################################################
## address 3
########################################################################
clock_divider_12_bit 3[3:14] 0
clock_div_mode 3[15:16] 0 clock_divider_off, fast_lock, resync_enable, reserved
-reserved 3[17] 0
+##reserved 3[17] 0
cycle_slip_reduction 3[18] 0 disabled, enabled
-reserved 3[19:20] 0
-reserved 3[21:31] 0
+##reserved 3[19:20] 0
+##reserved 3[21:31] 0
########################################################################
## address 4
########################################################################
@@ -76,15 +76,15 @@ vco_power_down 4[11] 0 vco_powered_up, vco_powered_down
band_select_clock_div 4[12:19] 0
rf_divider_select 4[20:22] 0 div1, div2, div4, div8, div16
feedback_select 4[23] 1 divided, fundamental
-reserved 4[24:31] 0
+##reserved 4[24:31] 0
########################################################################
## address 5
########################################################################
-reserved 5[3:18] 0
-reserved 5[19:20] 0
-reserved 5[21] 0
-ld_pin_mode 5[22:23] 1 low, dld, low, high
-reserved 5[24:31] 0
+##reserved 5[3:18] 0
+##reserved 5[19:20] 0
+##reserved 5[21] 0
+ld_pin_mode 5[22:23] 1 low0, dld, low, high
+##reserved 5[24:31] 0
"""
########################################################################
@@ -131,10 +131,10 @@ struct adf4350_regs_t{
ADDR_R5 = 5
};
- boost::uint32_t get_reg(addr_t addr){
- boost::uint32_t reg = addr & 0x3;
+ boost::uint32_t get_reg(boost::uint8_t addr){
+ boost::uint32_t reg = addr & 0x7;
switch(addr){
- #for $addr in (0, 1, 2, 3, 4, 5)
+ #for $addr in range(5+1)
case $addr:
#for $reg in filter(lambda r: r.get_addr() == addr, $regs)
reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
diff --git a/host/lib/usrp/dboard/db_wbx.cpp b/host/lib/usrp/dboard/db_wbx.cpp
index 99f06eedc..c837a0d50 100644
--- a/host/lib/usrp/dboard/db_wbx.cpp
+++ b/host/lib/usrp/dboard/db_wbx.cpp
@@ -17,26 +17,54 @@
static const bool wbx_debug = false;
-// IO Pin functions
-#define POWER_IO (1 << 7) // Low enables power supply
-#define ANTSW_IO (1 << 6) // On TX DB, 0 = TX, 1 = RX, on RX DB 0 = main ant, 1 = RX2
-#define MIXER_IO (1 << 5) // Enable appropriate mixer
-#define LOCKDET_MASK (1 << 2) // Input pin
+// Common IO Pins
+#define ANTSW_IO ((1 << 5)|(1 << 15)) // on UNIT_TX, 0 = TX, 1 = RX, on UNIT_RX 0 = main ant, 1 = RX2
+#define ADF4350_CE (1 << 3)
+#define ADF4350_PDBRF (1 << 2)
+#define ADF4350_MUXOUT (1 << 1) // INPUT!!!
+#define LOCKDET_MASK (1 << 0) // INPUT!!!
-// Mixer constants
-#define MIXER_ENB MIXER_IO
-#define MIXER_DIS 0
+// TX IO Pins
+#define TX_PUP_5V (1 << 7) // enables 5.0V power supply
+#define TX_PUP_3V (1 << 6) // enables 3.3V supply
+#define TXMOD_EN (1 << 4) // on UNIT_TX, 1 enables TX Modulator
-// Power constants
-#define POWER_UP 0
-#define POWER_DOWN POWER_IO
+// RX IO Pins
+#define RX_PUP_5V (1 << 7) // enables 5.0V power supply
+#define RX_PUP_3V (1 << 6) // enables 3.3V supply
+#define RXBB_PDB (1 << 4) // on UNIT_RX, 1 powers up RX baseband
+
+// RX Attenuator Pins
+#define RX_ATTN_SHIFT 8 // lsb of RX Attenuator Control
+#define RX_ATTN_MASK (63 << RX_ATTN_SHIFT) // valid bits of RX Attenuator Control
+
+// Mixer functions
+#define TX_MIXER_ENB (TXMOD_EN|ADF4350_PDBRF)
+#define TX_MIXER_DIS 0
+
+#define RX_MIXER_ENB (RXBB_PDB|ADF4350_PDBRF)
+#define RX_MIXER_DIS 0
+
+// Pin functions
+#define TX_POWER_IO (TX_PUP_5V|TX_PUP_3V) // high enables power supply
+#define TXIO_MASK (TX_POWER_IO|ANTSW_IO|ADF4350_CE|ADF4350_PDBRF|TXMOD_EN)
+
+#define RX_POWER_IO (RX_PUP_5V|RX_PUP_3V) // high enables power supply
+#define RXIO_MASK (RX_POWER_IO|ANTSW_IO|ADF4350_CE|ADF4350_PDBRF|RXBB_PDB|RX_ATTN_MASK)
+
+// Power functions
+#define TX_POWER_UP (TX_POWER_IO|ADF4350_CE)
+#define TX_POWER_DOWN 0
+
+#define RX_POWER_UP (RX_POWER_IO|ADF4350_CE)
+#define RX_POWER_DOWN 0
// Antenna constants
-#define ANT_TX 0 //the tx line is transmitting
-#define ANT_RX ANTSW_IO //the tx line is receiving
-#define ANT_TXRX 0 //the rx line is on txrx
-#define ANT_RX2 ANTSW_IO //the rx line in on rx2
-#define ANT_XX 0 //dont care how the antenna is set
+#define ANT_TX 0 //the tx line is transmitting
+#define ANT_RX ANTSW_IO //the tx line is receiving
+#define ANT_TXRX 0 //the rx line is on txrx
+#define ANT_RX2 ANTSW_IO //the rx line in on rx2
+#define ANT_XX 0 //dont care how the antenna is set
#include "adf4350_regs.hpp"
#include <uhd/types/dict.hpp>
@@ -58,14 +86,14 @@ using namespace boost::assign;
/***********************************************************************
* The WBX dboard
**********************************************************************/
-static const float _max_rx_pga0_gain = 45;
+static const float _max_rx_pga0_gain = 31.5;
+static const float _max_tx_pga0_gain = 25;
class wbx_xcvr : public xcvr_dboard_base{
public:
wbx_xcvr(
ctor_args_t const& args,
- const freq_range_t &freq_range,
- bool rx_div2, bool tx_div2
+ const freq_range_t &freq_range
);
~wbx_xcvr(void);
@@ -80,12 +108,18 @@ private:
uhd::dict<dboard_iface::unit_t, bool> _div2;
double _rx_lo_freq, _tx_lo_freq;
std::string _rx_ant;
+ int _rx_pga0_attn_iobits;
float _rx_pga0_gain;
+ float _tx_pga0_gain;
void set_rx_lo_freq(double freq);
void set_tx_lo_freq(double freq);
void set_rx_ant(const std::string &ant);
void set_rx_pga0_gain(float gain);
+ void set_rx_pga0_attn(float attn);
+ void set_tx_pga0_gain(float gain);
+
+ void update_atr(void);
/*!
* Set the LO frequency for the particular dboard unit.
@@ -109,7 +143,7 @@ private:
* Register the WBX dboard (min freq, max freq, rx div2, tx div2)
**********************************************************************/
static dboard_base::sptr make_wbx(dboard_base::ctor_args_t const& args){
- return dboard_base::sptr(new wbx_xcvr(args, freq_range_t(50e6, 2200e6), false, false));
+ return dboard_base::sptr(new wbx_xcvr(args, freq_range_t(50e6, 2220e6)));
}
UHD_STATIC_BLOCK(reg_wbx_dboards){
@@ -122,38 +156,24 @@ UHD_STATIC_BLOCK(reg_wbx_dboards){
**********************************************************************/
wbx_xcvr::wbx_xcvr(
ctor_args_t const& args,
- const freq_range_t &freq_range,
- bool rx_div2, bool tx_div2
+ const freq_range_t &freq_range
) : xcvr_dboard_base(args){
_freq_range = freq_range;
- _div2[dboard_iface::UNIT_RX] = rx_div2;
- _div2[dboard_iface::UNIT_TX] = tx_div2;
//enable the clocks that we need
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true);
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true);
//set the gpio directions
- boost::uint16_t output_enables = POWER_IO | ANTSW_IO | MIXER_IO;
- this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, output_enables);
- this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, output_enables);
-
- //setup the tx atr (this does not change with antenna)
- this->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_IDLE, POWER_UP | ANT_XX | MIXER_DIS);
- this->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_RX_ONLY, POWER_UP | ANT_RX | MIXER_DIS);
- this->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_TX_ONLY, POWER_UP | ANT_TX | MIXER_ENB);
- this->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_FULL_DUPLEX, POWER_UP | ANT_TX | MIXER_ENB);
-
- //setup the rx atr (this does not change with antenna)
- this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE, POWER_UP | ANT_XX | MIXER_DIS);
- this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY, POWER_UP | ANT_XX | MIXER_DIS);
- this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, POWER_UP | ANT_RX2| MIXER_ENB);
+ this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, TXIO_MASK);
+ this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, RXIO_MASK);
//set some default values
set_rx_lo_freq((_freq_range.min + _freq_range.max)/2.0);
set_tx_lo_freq((_freq_range.min + _freq_range.max)/2.0);
set_rx_ant("RX2");
set_rx_pga0_gain(0);
+ set_tx_pga0_gain(0);
}
wbx_xcvr::~wbx_xcvr(void){
@@ -163,6 +183,28 @@ wbx_xcvr::~wbx_xcvr(void){
/***********************************************************************
* Helper Methods
**********************************************************************/
+void wbx_xcvr::update_atr(void){
+ //calculate atr pins
+
+ //setup the tx atr (this does not change with antenna)
+ this->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_IDLE, TX_POWER_UP | ANT_XX | TX_MIXER_DIS);
+ this->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_RX_ONLY, TX_POWER_UP | ANT_RX | TX_MIXER_DIS);
+ this->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_TX_ONLY, TX_POWER_UP | ANT_TX | TX_MIXER_ENB);
+ this->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_FULL_DUPLEX, TX_POWER_UP | ANT_TX | TX_MIXER_ENB);
+
+ //setup the rx atr (this does not change with antenna)
+ this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE,
+ _rx_pga0_attn_iobits | RX_POWER_UP | ANT_XX | RX_MIXER_DIS);
+ this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY,
+ _rx_pga0_attn_iobits | RX_POWER_UP | ANT_XX | RX_MIXER_DIS);
+ this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX,
+ _rx_pga0_attn_iobits | RX_POWER_UP | ANT_RX2| RX_MIXER_ENB);
+
+ //set the rx atr regs that change with antenna setting
+ this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY,
+ _rx_pga0_attn_iobits | RX_POWER_UP | RX_MIXER_ENB | ((_rx_ant == "TX/RX")? ANT_TXRX : ANT_RX2));
+}
+
void wbx_xcvr::set_rx_lo_freq(double freq){
_rx_lo_freq = set_lo_freq(dboard_iface::UNIT_RX, freq);
}
@@ -175,32 +217,52 @@ void wbx_xcvr::set_rx_ant(const std::string &ant){
//validate input
UHD_ASSERT_THROW(ant == "TX/RX" or ant == "RX2");
- //set the rx atr regs that change with antenna setting
- this->get_iface()->set_atr_reg(
- dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY,
- POWER_UP | MIXER_ENB | ((ant == "TX/RX")? ANT_TXRX : ANT_RX2)
- );
-
//shadow the setting
_rx_ant = ant;
+
+ //write the new antenna setting to atr regs
+ update_atr();
}
void wbx_xcvr::set_rx_pga0_gain(float gain){
//clip the input
gain = std::clip<float>(gain, 0, _max_rx_pga0_gain);
+ //shadow the setting (does not account for precision loss)
+ _rx_pga0_gain = gain;
+
+ //convert to attenuation and update iobits for atr
+ set_rx_pga0_attn(_max_rx_pga0_gain - gain);
+
+ //write the new gain to atr regs
+ update_atr();
+}
+
+void wbx_xcvr::set_rx_pga0_attn(float attn)
+{
+ int attn_code = int(floor(attn/0.5));
+ _rx_pga0_attn_iobits = ((~attn_code) << RX_ATTN_SHIFT) | RX_ATTN_MASK;
+ if (wbx_debug) std::cerr << boost::format(
+ "Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x"
+ ) % attn % attn_code % (_rx_pga0_attn_iobits & RX_ATTN_MASK) % RX_ATTN_MASK << std::endl;
+}
+
+void wbx_xcvr::set_tx_pga0_gain(float gain){
+ //clip the input
+ gain = std::clip<float>(gain, 0, _max_tx_pga0_gain);
+
//voltage level constants
- static const float max_volts = float(.2), min_volts = float(1.2);
+ static const float max_volts = float(0.5), min_volts = float(1.4);
static const float slope = (max_volts-min_volts)/_max_rx_pga0_gain;
//calculate the voltage for the aux dac
float dac_volts = gain*slope + min_volts;
//write the new voltage to the aux dac
- this->get_iface()->write_aux_dac(dboard_iface::UNIT_RX, 1, dac_volts);
+ this->get_iface()->write_aux_dac(dboard_iface::UNIT_TX, 0, dac_volts);
//shadow the setting (does not account for precision loss)
- _rx_pga0_gain = gain;
+ _tx_pga0_gain = gain;
}
double wbx_xcvr::set_lo_freq(
@@ -213,92 +275,120 @@ double wbx_xcvr::set_lo_freq(
//clip the input
target_freq = std::clip(target_freq, _freq_range.min, _freq_range.max);
- if (_div2[unit]) target_freq *= 2;
- //map prescalers to the register enums
- static const uhd::dict<int, adf4350_regs_t::prescaler_value_t> prescaler_to_enum = map_list_of
- (8, adf4350_regs_t::PRESCALER_VALUE_8_9)
- (16, adf4350_regs_t::PRESCALER_VALUE_16_17)
- (32, adf4350_regs_t::PRESCALER_VALUE_32_33)
+ //map prescaler setting to mininmum integer divider (N) values (pg.18 prescaler)
+ static const uhd::dict<int, int> prescaler_to_min_int_div = map_list_of
+ (0,23) //adf4350_regs_t::PRESCALER_4_5
+ (1,75) //adf4350_regs_t::PRESCALER_8_9
;
- //map band select clock dividers to enums
- static const uhd::dict<int, adf4350_regs_t::band_select_clock_div_t> bandsel_to_enum = map_list_of
- (1, adf4350_regs_t::BAND_SELECT_CLOCK_DIV_1)
- (2, adf4350_regs_t::BAND_SELECT_CLOCK_DIV_2)
- (4, adf4350_regs_t::BAND_SELECT_CLOCK_DIV_4)
- (8, adf4350_regs_t::BAND_SELECT_CLOCK_DIV_8)
+ //map rf divider select output dividers to enums
+ static const uhd::dict<int, adf4350_regs_t::rf_divider_select_t> rfdivsel_to_enum = map_list_of
+ (1, adf4350_regs_t::RF_DIVIDER_SELECT_DIV1)
+ (2, adf4350_regs_t::RF_DIVIDER_SELECT_DIV2)
+ (4, adf4350_regs_t::RF_DIVIDER_SELECT_DIV4)
+ (8, adf4350_regs_t::RF_DIVIDER_SELECT_DIV8)
+ (16, adf4350_regs_t::RF_DIVIDER_SELECT_DIV16)
;
- double actual_freq, ref_freq = this->get_iface()->get_clock_rate(unit);
- int R, BS, P, B, A;
+ double actual_freq, pfd_freq;
+ double ref_freq = this->get_iface()->get_clock_rate(unit);
+ int R, BS, N, FRAC, MOD;
+ int RFdiv = 1;
+ adf4350_regs_t::reference_divide_by_2_t T = adf4350_regs_t::REFERENCE_DIVIDE_BY_2_DISABLED;
+ adf4350_regs_t::reference_doubler_t D = adf4350_regs_t::REFERENCE_DOUBLER_DISABLED;
+
+ //Reference doubler for 50% duty cycle
+ // if ref_freq < 12.5MHz enable regs.reference_divide_by_2
+ if(ref_freq <= 12.5e6) D = adf4350_regs_t::REFERENCE_DOUBLER_ENABLED;
+
+ //increase RF divider until acceptable VCO frequency
+ //start with target_freq*2 because mixer has divide by 2
+ double vco_freq = target_freq*2;
+ while (vco_freq < 2.2e9) {
+ vco_freq *= 2;
+ RFdiv *= 2;
+ }
+
+ //use 8/9 prescaler for vco_freq > 3 GHz (pg.18 prescaler)
+ adf4350_regs_t::prescaler_t prescaler = vco_freq > 3e9 ? adf4350_regs_t::PRESCALER_4_5 : adf4350_regs_t::PRESCALER_8_9;
/*
- * The goal here to to loop though possible R dividers,
- * band select clock dividers, and prescaler values.
- * Calculate the A and B counters for each set of values.
+ * The goal here is to loop though possible R dividers,
+ * band select clock dividers, N (int) dividers, and FRAC
+ * (frac) dividers.
+ *
+ * Calculate the N and F dividers for each set of values.
* The loop exists when it meets all of the constraints.
* The resulting loop values are loaded into the registers.
*
- * fvco = [P*B + A] * fref/R
- * fvco*R/fref = P*B + A = N
+ * from pg.21
+ *
+ * f_pfd = f_ref*(1+D)/(R*(1+T))
+ * f_vco = (N + (FRAC/MOD))*f_pfd
+ * N = f_vco/f_pfd - FRAC/MOD = f_vco*((R*(T+1))/(f_ref*(1+D))) - FRAC/MOD
+ * f_rf = f_vco/RFdiv)
+ * f_actual = f_rf/2
*/
- for(R = 2; R <= 32; R+=2){
- BOOST_FOREACH(BS, bandsel_to_enum.keys()){
- if (ref_freq/R/BS > 1e6) continue; //constraint on band select clock
- BOOST_FOREACH(P, prescaler_to_enum.keys()){
- //calculate B and A from N
- double N = target_freq*R/ref_freq;
- B = int(std::floor(N/P));
- A = boost::math::iround(N - P*B);
- if (B < A or B > 8191 or B < 3 or A > 31) continue; //constraints on A, B
- //calculate the actual frequency
- actual_freq = double(P*B + A)*ref_freq/R;
- if (actual_freq/P > 300e6) continue; //constraint on prescaler output
- //constraints met: exit loop
- goto done_loop;
- }
+ for(R = 1; R <= 1023; R+=1){
+ //PFD input frequency = f_ref/R ... ignoring Reference doubler/divide-by-2 (D & T)
+ pfd_freq = ref_freq*(1+D)/(R*(1+T));
+
+ //keep the PFD frequency at or below 25MHz (Loop Filter Bandwidth)
+ if (pfd_freq > 25e6) continue;
+
+ //ignore fractional part of tuning
+ N = int(std::ceil(vco_freq/pfd_freq));
+
+ //keep N > minimum int divider requirement
+ if (N < prescaler_to_min_int_div[prescaler]) continue;
+
+ for(BS=1; BS <= 255; BS+=1){
+ //keep the band select frequency at or below 125KHz
+ //constraint on band select clock
+ if (pfd_freq/BS > 125e3) continue;
+ goto done_loop;
}
} done_loop:
- if (wbx_debug) std::cerr << boost::format(
- "RFX tune: R=%d, BS=%d, P=%d, B=%d, A=%d"
- ) % R % BS % P % B % A << std::endl;
+ //Fractional-N calculation
+ MOD = 4095; //max fractional accuracy
+ FRAC = int((N - vco_freq/pfd_freq)*MOD);
+
+ //Reference divide-by-2 for 50% duty cycle
+ // if R even, move one divide by 2 to to regs.reference_divide_by_2
+ if(R % 2 > 0){
+ T = adf4350_regs_t::REFERENCE_DIVIDE_BY_2_ENABLED;
+ R /= 2;
+ }
+
+ //actual frequency calculation
+ actual_freq = double(N + double(FRAC/MOD))*ref_freq*(1+D)/(R*(1+T))/RFdiv/2;
+
+ if (wbx_debug) std::cerr
+ << boost::format("WBX tune: R=%d, BS=%d, N=%d, FRAC=%d, MOD=%d, T=%d, D=%d"
+ ) % R % BS % N % FRAC % MOD % T % D << std::endl
+ << boost::format("WBX Frequencies (MHz): REQ=%0.2f, ACT=%0.2f, VCO=%0.2f, PFD=%0.2f, BAND=%0.2f"
+ ) % (target_freq*2/1e6) % (actual_freq/1e6) % (vco_freq/1e6) % (pfd_freq/1e6) % (pfd_freq/BS/1e6) << std::endl;
//load the register values
adf4350_regs_t regs;
- regs.core_power_level = adf4350_regs_t::CORE_POWER_LEVEL_10MA;
- regs.counter_operation = adf4350_regs_t::COUNTER_OPERATION_NORMAL;
- regs.muxout_control = adf4350_regs_t::MUXOUT_CONTROL_DLD;
- regs.phase_detector_polarity = adf4350_regs_t::PHASE_DETECTOR_POLARITY_POS;
- regs.charge_pump_output = adf4350_regs_t::CHARGE_PUMP_OUTPUT_NORMAL;
- regs.cp_gain_0 = adf4350_regs_t::CP_GAIN_0_SET1;
- regs.mute_till_ld = adf4350_regs_t::MUTE_TILL_LD_ENB;
- regs.output_power_level = adf4350_regs_t::OUTPUT_POWER_LEVEL_3_5MA;
- regs.current_setting1 = adf4350_regs_t::CURRENT_SETTING1_0_31MA;
- regs.current_setting2 = adf4350_regs_t::CURRENT_SETTING2_0_31MA;
- regs.power_down = adf4350_regs_t::POWER_DOWN_NORMAL_OP;
- regs.prescaler_value = prescaler_to_enum[P];
- regs.a_counter = A;
- regs.b_counter = B;
- regs.cp_gain_1 = adf4350_regs_t::CP_GAIN_1_SET1;
- regs.divide_by_2_output = (_div2[unit])?
- adf4350_regs_t::DIVIDE_BY_2_OUTPUT_DIV2 :
- adf4350_regs_t::DIVIDE_BY_2_OUTPUT_FUND ;
- regs.divide_by_2_prescaler = adf4350_regs_t::DIVIDE_BY_2_PRESCALER_FUND;
- regs.r_counter = R;
- regs.ablpw = adf4350_regs_t::ABLPW_3_0NS;
- regs.lock_detect_precision = adf4350_regs_t::LOCK_DETECT_PRECISION_5CYCLES;
- regs.test_mode_bit = 0;
- regs.band_select_clock_div = bandsel_to_enum[BS];
+
+ regs.frac_12_bit = FRAC;
+ regs.int_16_bit = N;
+ regs.mod_12_bit = MOD;
+ regs.prescaler = prescaler;
+ regs.r_counter_10_bit = R;
+ regs.reference_divide_by_2 = T;
+ regs.reference_doubler = D;
+ regs.band_select_clock_div = BS;
+ regs.rf_divider_select = rfdivsel_to_enum[RFdiv];
//write the registers
- std::vector<adf4350_regs_t::addr_t> addrs = list_of //correct power-up sequence to write registers (R, C, N)
- (adf4350_regs_t::ADDR_RCOUNTER)
- (adf4350_regs_t::ADDR_CONTROL)
- (adf4350_regs_t::ADDR_NCOUNTER)
- ;
- BOOST_FOREACH(adf4350_regs_t::addr_t addr, addrs){
+ //correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
+ int addr;
+
+ for(addr=5; addr>=0; addr--){
this->get_iface()->write_spi(
unit, spi_config_t::EDGE_RISE,
regs.get_reg(addr), 24
@@ -306,7 +396,6 @@ double wbx_xcvr::set_lo_freq(
}
//return the actual frequency
- if (_div2[unit]) actual_freq /= 2;
if (wbx_debug) std::cerr << boost::format(
"RFX tune: actual frequency %f Mhz"
) % (actual_freq/1e6) << std::endl;
@@ -337,7 +426,7 @@ void wbx_xcvr::rx_get(const wax::obj &key_, wax::obj &val){
case SUBDEV_PROP_GAIN_RANGE:
UHD_ASSERT_THROW(name == "PGA0");
- val = gain_range_t(0, _max_rx_pga0_gain, float(0.022));
+ val = gain_range_t(0, _max_rx_pga0_gain, float(0.5));
return;
case SUBDEV_PROP_GAIN_NAMES:
@@ -428,15 +517,17 @@ void wbx_xcvr::tx_get(const wax::obj &key_, wax::obj &val){
return;
case SUBDEV_PROP_GAIN:
- val = float(0);
+ UHD_ASSERT_THROW(name == "PGA0");
+ val = _tx_pga0_gain;
return;
case SUBDEV_PROP_GAIN_RANGE:
- val = gain_range_t(0, 0, 0);
+ UHD_ASSERT_THROW(name == "PGA0");
+ val = gain_range_t(0, _max_tx_pga0_gain, float(0.05));
return;
case SUBDEV_PROP_GAIN_NAMES:
- val = prop_names_t(); //empty
+ val = prop_names_t(1, "PGA0");
return;
case SUBDEV_PROP_FREQ:
@@ -491,7 +582,8 @@ void wbx_xcvr::tx_set(const wax::obj &key_, const wax::obj &val){
return;
case SUBDEV_PROP_GAIN:
- //no gains to set!
+ UHD_ASSERT_THROW(name == "PGA0");
+ set_tx_pga0_gain(val.as<float>());
return;
case SUBDEV_PROP_ANTENNA:
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 16:41:11 +0000