diff options
Diffstat (limited to 'host/lib')
| -rw-r--r-- | host/lib/ic_reg_maps/common.py | 53 | ||||
| -rwxr-xr-x | host/lib/ic_reg_maps/gen_ad9777_regs.py | 2 |
2 files changed, 53 insertions, 2 deletions
diff --git a/host/lib/ic_reg_maps/common.py b/host/lib/ic_reg_maps/common.py index e27c2816d..173186eb1 100644 --- a/host/lib/ic_reg_maps/common.py +++ b/host/lib/ic_reg_maps/common.py @@ -80,6 +80,26 @@ $body return addrs; } + #for $mreg in $mregs + $mreg.get_type() get_$(mreg.get_name())(void){ + return + #set $shift = 0 + #for $reg in $mreg.get_regs() + ($(mreg.get_type())($reg.get_name() & $reg.get_mask()) << $shift) | + #set $shift = $shift + $reg.get_bit_width() + #end for + 0; + } + + void set_$(mreg.get_name())($mreg.get_type() reg){ + #set $shift = 0 + #for $reg in $mreg.get_regs() + $reg.get_name() = (reg >> $shift) & $reg.get_mask(); + #set $shift = $shift + $reg.get_bit_width() + #end for + } + + #end for private: $(name)_t *_state; }; @@ -90,7 +110,7 @@ private: def parse_tmpl(_tmpl_text, **kwargs): return str(Template(_tmpl_text, kwargs)) -def to_num(arg): return eval(arg) +def to_num(arg): return int(eval(arg)) class reg: def __init__(self, reg_des): @@ -135,13 +155,42 @@ class reg: def get_mask(self): return hex(int('1'*self.get_bit_width(), 2)) def get_bit_width(self): return self._addr_spec[1] - self._addr_spec[0] + 1 +class mreg: + def __init__(self, mreg_des, regs): + try: self.parse(mreg_des, regs) + except Exception, e: + raise Exception, 'Error parsing meta register description: "%s"\nWhat: %s'%(mreg_des, e) + + def parse(self, mreg_des, regs): + x = re.match('^~(\w*)\s+(.*)\s*$', mreg_des) + self._name, reg_names = x.groups() + regs_dict = dict([(reg.get_name(), reg) for reg in regs]) + self._regs = [regs_dict[reg_name] for reg_name in map(str.strip, reg_names.split(','))] + + def get_name(self): return self._name + def get_regs(self): return self._regs + def get_bit_width(self): return sum(map(reg.get_bit_width, self._regs)) + def get_type(self): + return 'boost::uint%d_t'%max(2**math.ceil(math.log(self.get_bit_width(), 2)), 8) + def generate(name, regs_tmpl, body_tmpl='', file=__file__): - regs = map(reg, parse_tmpl(regs_tmpl).splitlines()) + #evaluate the regs template and parse each line into a register + regs = list(); mregs = list() + for entry in parse_tmpl(regs_tmpl).splitlines(): + if entry.startswith('~'): mregs.append(mreg(entry, regs)) + else: regs.append(reg(entry)) + + #evaluate the body template with the list of registers body = parse_tmpl(body_tmpl, regs=regs).replace('\n', '\n ').strip() + + #evaluate the code template with the parsed registers and arguments code = parse_tmpl(COMMON_TMPL, name=name, regs=regs, + mregs=mregs, body=body, file=file, ) + + #write the generated code to file specified by argv1 open(sys.argv[1], 'w').write(code) diff --git a/host/lib/ic_reg_maps/gen_ad9777_regs.py b/host/lib/ic_reg_maps/gen_ad9777_regs.py index 690b15e24..47b61cf44 100755 --- a/host/lib/ic_reg_maps/gen_ad9777_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9777_regs.py @@ -76,9 +76,11 @@ qdac_coarse_gain_adjust 0xA[0:3] 0 ######################################################################## idac_offset_adjust_msb 7[0:7] 0 idac_offset_adjust_lsb 8[0:1] 0 +~idac_offset_adjust idac_offset_adjust_lsb, idac_offset_adjust_msb idac_ioffset_direction 8[7] 0 out_a, out_b qdac_offset_adjust_msb 0xB[0:7] 0 qdac_offset_adjust_lsb 0xC[0:1] 0 +~qdac_offset_adjust qdac_offset_adjust_lsb, qdac_offset_adjust_msb qdac_ioffset_direction 0xC[7] 0 out_a, out_b """ |