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-rw-r--r--host/lib/usrp/usrp2/fw_common.h25
-rw-r--r--host/lib/usrp/usrp2/mboard_impl.cpp3
-rw-r--r--host/lib/usrp/usrp2/usrp2_iface.cpp120
-rw-r--r--host/lib/usrp/usrp2/usrp2_iface.hpp6
-rw-r--r--host/lib/usrp/usrp2/usrp2_impl.cpp8
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.cpp206
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.hpp28
7 files changed, 211 insertions, 185 deletions
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index 68c49cafc..e5c60f27c 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -30,8 +30,8 @@ extern "C" {
#endif
//fpga and firmware compatibility numbers
-#define USRP2_FPGA_COMPAT_NUM 5
-#define USRP2_FW_COMPAT_NUM 9
+#define USRP2_FPGA_COMPAT_NUM 6
+#define USRP2_FW_COMPAT_NUM 10
//used to differentiate control packets over data port
#define USRP2_INVALID_VRT_HEADER 0
@@ -77,11 +77,8 @@ typedef enum{
USRP2_CTRL_ID_WRITE_THESE_I2C_VALUES_BRO = 'h',
USRP2_CTRL_ID_COOL_IM_DONE_I2C_WRITE_DUDE = 'H',
- USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO = 'p',
- USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE = 'P',
-
- USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO = 'r',
- USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE = 'R',
+ USRP2_CTRL_ID_GET_THIS_REGISTER_FOR_ME_BRO = 'r',
+ USRP2_CTRL_ID_OMG_GOT_REGISTER_SO_BAD_DUDE = 'R',
USRP2_CTRL_ID_HEY_WRITE_THIS_UART_FOR_ME_BRO = 'u',
USRP2_CTRL_ID_MAN_I_TOTALLY_WROTE_THAT_UART_DUDE = 'U',
@@ -106,6 +103,15 @@ typedef enum{
USRP2_CLK_EDGE_FALL = 'f'
} usrp2_clk_edge_t;
+typedef enum{
+ USRP2_REG_ACTION_FPGA_PEEK32 = 1,
+ USRP2_REG_ACTION_FPGA_PEEK16 = 2,
+ USRP2_REG_ACTION_FPGA_POKE32 = 3,
+ USRP2_REG_ACTION_FPGA_POKE16 = 4,
+ USRP2_REG_ACTION_FW_PEEK32 = 5,
+ USRP2_REG_ACTION_FW_POKE32 = 6
+} usrp2_reg_action_t;
+
typedef struct{
uint32_t proto_ver;
uint32_t id;
@@ -128,9 +134,8 @@ typedef struct{
struct {
uint32_t addr;
uint32_t data;
- uint32_t _pad[2];
- uint8_t num_bytes; //1, 2, 4
- } poke_args;
+ uint8_t action;
+ } reg_args;
struct {
uint8_t dev;
uint8_t bytes;
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index c9931be45..bb4d90dd6 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -81,6 +81,9 @@ usrp2_mboard_impl::usrp2_mboard_impl(
) % int(USRP2_FPGA_COMPAT_NUM) % fpga_compat_num));
}
+ //lock the device/motherboard to this process
+ _iface->lock_device(true);
+
//construct transports for dsp and async errors
UHD_LOG << "Making transport for DSP0..." << std::endl;
device.dsp_xports.push_back(udp_zero_copy::make(
diff --git a/host/lib/usrp/usrp2/usrp2_iface.cpp b/host/lib/usrp/usrp2/usrp2_iface.cpp
index d88d31765..4bcc61444 100644
--- a/host/lib/usrp/usrp2/usrp2_iface.cpp
+++ b/host/lib/usrp/usrp2/usrp2_iface.cpp
@@ -26,7 +26,10 @@
#include <boost/assign/list_of.hpp>
#include <boost/format.hpp>
#include <boost/tokenizer.hpp>
+#include <boost/thread/thread.hpp>
+#include <boost/thread/barrier.hpp>
#include <algorithm>
+#include <iostream>
using namespace uhd;
using namespace uhd::usrp;
@@ -41,6 +44,9 @@ static const boost::uint32_t MIN_PROTO_COMPAT_I2C = 7;
static const boost::uint32_t MIN_PROTO_COMPAT_REG = USRP2_FW_COMPAT_NUM;
static const boost::uint32_t MIN_PROTO_COMPAT_UART = 7;
+// Map for virtual firmware regs (not very big so we can keep it here for now)
+#define U2_FW_REG_LOCK_TIME 0
+
class usrp2_iface_impl : public usrp2_iface{
public:
/***********************************************************************
@@ -62,40 +68,84 @@ public:
_protocol_compat = ntohl(ctrl_data.proto_ver);
mb_eeprom = mboard_eeprom_t(*this, mboard_eeprom_t::MAP_N100);
- switch(this->get_rev()){
- case USRP2_REV3:
- case USRP2_REV4:
- regs = usrp2_get_regs(false);
- break;
-
- case USRP_N200:
- case USRP_N210:
- regs = usrp2_get_regs(true);
- break;
-
- case USRP_NXXX: //fallthough case is old register map (USRP2)
- regs = usrp2_get_regs(false);
- break;
+ regs = usrp2_get_regs(); //reg map identical across all boards
+ }
+
+ ~usrp2_iface_impl(void){
+ this->lock_device(false);
+ }
+
+/***********************************************************************
+ * Device locking
+ **********************************************************************/
+
+ void lock_device(bool lock){
+ if (lock){
+ boost::barrier spawn_barrier(2);
+ _lock_thread_group.create_thread(boost::bind(&usrp2_iface_impl::lock_loop, this, boost::ref(spawn_barrier)));
+ spawn_barrier.wait();
+ }
+ else{
+ _lock_thread_group.interrupt_all();
+ _lock_thread_group.join_all();
}
}
+ bool is_device_locked(void){
+ boost::uint32_t lock_secs = this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FW_PEEK32>(U2_FW_REG_LOCK_TIME);
+ boost::uint32_t curr_secs = this->peek32(this->regs.time64_secs_rb_imm);
+ return (curr_secs - lock_secs < 3); //if the difference is larger, assume not locked anymore
+ }
+
+ void lock_loop(boost::barrier &spawn_barrier){
+ spawn_barrier.wait();
+
+ try{
+ while(true){
+ //re-lock in loop
+ boost::uint32_t curr_secs = this->peek32(this->regs.time64_secs_rb_imm);
+ this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FW_POKE32>(U2_FW_REG_LOCK_TIME, curr_secs);
+ //sleep for a bit
+ boost::this_thread::sleep(boost::posix_time::milliseconds(1500));
+ }
+ } catch(const boost::thread_interrupted &){}
+
+ //unlock on exit
+ this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FW_POKE32>(U2_FW_REG_LOCK_TIME, 0);
+ }
+
/***********************************************************************
* Peek and Poke
**********************************************************************/
void poke32(boost::uint32_t addr, boost::uint32_t data){
- return this->poke<boost::uint32_t>(addr, data);
+ this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FPGA_POKE32>(addr, data);
}
boost::uint32_t peek32(boost::uint32_t addr){
- return this->peek<boost::uint32_t>(addr);
+ return this->get_reg<boost::uint32_t, USRP2_REG_ACTION_FPGA_PEEK32>(addr);
}
void poke16(boost::uint32_t addr, boost::uint16_t data){
- return this->poke<boost::uint16_t>(addr, data);
+ this->get_reg<boost::uint16_t, USRP2_REG_ACTION_FPGA_POKE16>(addr, data);
}
boost::uint16_t peek16(boost::uint32_t addr){
- return this->peek<boost::uint16_t>(addr);
+ return this->get_reg<boost::uint16_t, USRP2_REG_ACTION_FPGA_PEEK16>(addr);
+ }
+
+ template <class T, usrp2_reg_action_t action>
+ T get_reg(boost::uint32_t addr, T data = 0){
+ //setup the out data
+ usrp2_ctrl_data_t out_data;
+ out_data.id = htonl(USRP2_CTRL_ID_GET_THIS_REGISTER_FOR_ME_BRO);
+ out_data.data.reg_args.addr = htonl(addr);
+ out_data.data.reg_args.data = htonl(boost::uint32_t(data));
+ out_data.data.reg_args.action = action;
+
+ //send and recv
+ usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data, MIN_PROTO_COMPAT_REG);
+ UHD_ASSERT_THROW(ntohl(in_data.id) == USRP2_CTRL_ID_OMG_GOT_REGISTER_SO_BAD_DUDE);
+ return T(ntohl(in_data.data.reg_args.data));
}
/***********************************************************************
@@ -201,9 +251,9 @@ public:
}
std::string read_uart(boost::uint8_t dev){
- int readlen = 20;
+ int readlen = 20;
std::string result;
- while(readlen == 20) { //while we keep receiving full packets
+ while(readlen == 20) { //while we keep receiving full packets
//setup the out data
usrp2_ctrl_data_t out_data;
out_data.id = htonl(USRP2_CTRL_ID_SO_LIKE_CAN_YOU_READ_THIS_UART_BRO);
@@ -302,34 +352,8 @@ private:
boost::uint32_t _ctrl_seq_num;
boost::uint32_t _protocol_compat;
-/***********************************************************************
- * Private Templated Peek and Poke
- **********************************************************************/
- template <class T> void poke(boost::uint32_t addr, T data){
- //setup the out data
- usrp2_ctrl_data_t out_data;
- out_data.id = htonl(USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO);
- out_data.data.poke_args.addr = htonl(addr);
- out_data.data.poke_args.data = htonl(boost::uint32_t(data));
- out_data.data.poke_args.num_bytes = sizeof(T);
-
- //send and recv
- usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data, MIN_PROTO_COMPAT_REG);
- UHD_ASSERT_THROW(ntohl(in_data.id) == USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE);
- }
-
- template <class T> T peek(boost::uint32_t addr){
- //setup the out data
- usrp2_ctrl_data_t out_data;
- out_data.id = htonl(USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO);
- out_data.data.poke_args.addr = htonl(addr);
- out_data.data.poke_args.num_bytes = sizeof(T);
-
- //send and recv
- usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data, MIN_PROTO_COMPAT_REG);
- UHD_ASSERT_THROW(ntohl(in_data.id) == USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE);
- return T(ntohl(in_data.data.poke_args.data));
- }
+ //lock thread stuff
+ boost::thread_group _lock_thread_group;
};
/***********************************************************************
diff --git a/host/lib/usrp/usrp2/usrp2_iface.hpp b/host/lib/usrp/usrp2/usrp2_iface.hpp
index 08f3955f1..e4d1a166b 100644
--- a/host/lib/usrp/usrp2/usrp2_iface.hpp
+++ b/host/lib/usrp/usrp2/usrp2_iface.hpp
@@ -66,6 +66,12 @@ public:
//! Get the canonical name for this device
virtual const std::string get_cname(void) = 0;
+ //! Lock the device to this iface
+ virtual void lock_device(bool lock) = 0;
+
+ //! Is this device locked?
+ virtual bool is_device_locked(void) = 0;
+
/*!
* Register map selected from USRP2/USRP2+.
*/
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index 2bc259657..9947e71e7 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -114,9 +114,11 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
//Attempt to read the name from the EEPROM and perform filtering.
//This operation can throw due to compatibility mismatch.
try{
- mboard_eeprom_t mb_eeprom = usrp2_iface::make(udp_simple::make_connected(
- new_addr["addr"], boost::lexical_cast<std::string>(USRP2_UDP_CTRL_PORT)
- ))->mb_eeprom;
+ usrp2_iface::sptr iface = usrp2_iface::make(udp_simple::make_connected(
+ new_addr["addr"], BOOST_STRINGIZE(USRP2_UDP_CTRL_PORT)
+ ));
+ if (iface->is_device_locked()) continue; //ignore locked devices
+ mboard_eeprom_t mb_eeprom = iface->mb_eeprom;
new_addr["name"] = mb_eeprom["name"];
new_addr["serial"] = mb_eeprom["serial"];
}
diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp
index 65236396c..240bc3bab 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.cpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.cpp
@@ -18,107 +18,119 @@
#include "usrp2_regs.hpp"
#include "usrp2_iface.hpp"
-int sr_addr(int misc_output_base, int sr) {
- return misc_output_base + 4 * sr;
-}
+////////////////////////////////////////////////////////////////////////
+// Define slave bases
+////////////////////////////////////////////////////////////////////////
+#define ROUTER_RAM_BASE 0x4000
+#define SPI_BASE 0x5000
+#define I2C_BASE 0x5400
+#define GPIO_BASE 0x5800
+#define READBACK_BASE 0x5C00
+#define ETH_BASE 0x6000
+#define SETTING_REGS_BASE 0x7000
+#define PIC_BASE 0x8000
+#define UART_BASE 0x8800
+#define ATR_BASE 0x8C00
+
+////////////////////////////////////////////////////////////////////////
+// Setting register offsets
+////////////////////////////////////////////////////////////////////////
+#define SR_MISC 0 // 7 regs
+#define SR_SIMTIMER 8 // 2
+#define SR_TIME64 10 // 6
+#define SR_BUF_POOL 16 // 4
+
+#define SR_RX_FRONT 24 // 5
+#define SR_RX_CTRL0 32 // 9
+#define SR_RX_DSP0 48 // 7
+#define SR_RX_CTRL1 80 // 9
+#define SR_RX_DSP1 96 // 7
-usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
+#define SR_TX_FRONT 128 // ?
+#define SR_TX_CTRL 144 // 6
+#define SR_TX_DSP 160 // 5
- //how about you just make this dependent on hw_rev instead of doing the init before main, and give up the const globals, since the application won't ever need both.
- const int misc_output_base = (use_n2xx_map) ? USRP2P_MISC_OUTPUT_BASE : USRP2_MISC_OUTPUT_BASE,
- gpio_base = (use_n2xx_map) ? USRP2P_GPIO_BASE : USRP2_GPIO_BASE,
- atr_base = (use_n2xx_map) ? USRP2P_ATR_BASE : USRP2_ATR_BASE,
- bp_base = (use_n2xx_map) ? USRP2P_BP_STATUS_BASE : USRP2_BP_STATUS_BASE;
+#define SR_UDP_SM 192 // 64
+
+int sr_addr(int sr) {
+ return SETTING_REGS_BASE + (4 * sr);
+}
+usrp2_regs_t usrp2_get_regs(void) {
usrp2_regs_t x;
- x.sr_misc = 0;
- x.sr_tx_prot_eng = 32;
- x.sr_rx_prot_eng = 48;
- x.sr_buffer_pool_ctrl = 64;
- x.sr_udp_sm = 96;
- x.sr_tx_dsp = 208;
- x.sr_tx_ctrl = 224;
- x.sr_rx_dsp0 = 160;
- x.sr_rx_ctrl0 = 176;
- x.sr_rx_dsp1 = 240;
- x.sr_rx_ctrl1 = 32;
- x.sr_time64 = 192;
- x.sr_simtimer = 198;
- x.sr_last = 255;
- x.misc_ctrl_clock = sr_addr(misc_output_base, 0);
- x.misc_ctrl_serdes = sr_addr(misc_output_base, 1);
- x.misc_ctrl_adc = sr_addr(misc_output_base, 2);
- x.misc_ctrl_leds = sr_addr(misc_output_base, 3);
- x.misc_ctrl_phy = sr_addr(misc_output_base, 4);
- x.misc_ctrl_dbg_mux = sr_addr(misc_output_base, 5);
- x.misc_ctrl_ram_page = sr_addr(misc_output_base, 6);
- x.misc_ctrl_flush_icache = sr_addr(misc_output_base, 7);
- x.misc_ctrl_led_src = sr_addr(misc_output_base, 8);
- x.time64_secs = sr_addr(misc_output_base, x.sr_time64 + 0);
- x.time64_ticks = sr_addr(misc_output_base, x.sr_time64 + 1);
- x.time64_flags = sr_addr(misc_output_base, x.sr_time64 + 2);
- x.time64_imm = sr_addr(misc_output_base, x.sr_time64 + 3);
- x.time64_tps = sr_addr(misc_output_base, x.sr_time64 + 4);
- x.time64_mimo_sync = sr_addr(misc_output_base, x.sr_time64 + 5);
- x.status = bp_base + 4*8;
- x.time64_secs_rb_imm = bp_base + 4*10;
- x.time64_ticks_rb_imm = bp_base + 4*11;
- x.compat_num_rb = bp_base + 4*12;
- x.irq_rb = bp_base + 4*13;
- x.time64_secs_rb_pps = bp_base + 4*14;
- x.time64_ticks_rb_pps = bp_base + 4*15;
- x.dsp_tx_freq = sr_addr(misc_output_base, x.sr_tx_dsp + 0);
- x.dsp_tx_scale_iq = sr_addr(misc_output_base, x.sr_tx_dsp + 1);
- x.dsp_tx_interp_rate = sr_addr(misc_output_base, x.sr_tx_dsp + 2);
- x.dsp_tx_mux = sr_addr(misc_output_base, x.sr_tx_dsp + 4);
- x.dsp_rx[0].freq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 0);
- x.dsp_rx[0].scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 1);
- x.dsp_rx[0].decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp0 + 2);
- x.dsp_rx[0].dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp0 + 3);
- x.dsp_rx[0].dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp0 + 4);
- x.dsp_rx[0].mux = sr_addr(misc_output_base, x.sr_rx_dsp0 + 5);
- x.dsp_rx[1].freq = sr_addr(misc_output_base, x.sr_rx_dsp1 + 0);
- x.dsp_rx[1].scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp1 + 1);
- x.dsp_rx[1].decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp1 + 2);
- x.dsp_rx[1].dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp1 + 3);
- x.dsp_rx[1].dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp1 + 4);
- x.dsp_rx[1].mux = sr_addr(misc_output_base, x.sr_rx_dsp1 + 5);
- x.gpio_io = gpio_base + 0;
- x.gpio_ddr = gpio_base + 4;
- x.gpio_tx_sel = gpio_base + 8;
- x.gpio_rx_sel = gpio_base + 12;
- x.atr_idle_txside = atr_base + 0;
- x.atr_idle_rxside = atr_base + 2;
- x.atr_intx_txside = atr_base + 4;
- x.atr_intx_rxside = atr_base + 6;
- x.atr_inrx_txside = atr_base + 8;
- x.atr_inrx_rxside = atr_base + 10;
- x.atr_full_txside = atr_base + 12;
- x.atr_full_rxside = atr_base + 14;
- x.rx_ctrl[0].stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 0);
- x.rx_ctrl[0].time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 1);
- x.rx_ctrl[0].time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 2);
- x.rx_ctrl[0].clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 3);
- x.rx_ctrl[0].vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 4);
- x.rx_ctrl[0].vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 5);
- x.rx_ctrl[0].vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 6);
- x.rx_ctrl[0].nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 7);
- x.rx_ctrl[0].nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 8);
- x.rx_ctrl[1].stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 0);
- x.rx_ctrl[1].time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 1);
- x.rx_ctrl[1].time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 2);
- x.rx_ctrl[1].clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 3);
- x.rx_ctrl[1].vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 4);
- x.rx_ctrl[1].vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 5);
- x.rx_ctrl[1].vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 6);
- x.rx_ctrl[1].nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 7);
- x.rx_ctrl[1].nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 8);
- x.tx_ctrl_num_chan = sr_addr(misc_output_base, x.sr_tx_ctrl + 0);
- x.tx_ctrl_clear_state = sr_addr(misc_output_base, x.sr_tx_ctrl + 1);
- x.tx_ctrl_report_sid = sr_addr(misc_output_base, x.sr_tx_ctrl + 2);
- x.tx_ctrl_policy = sr_addr(misc_output_base, x.sr_tx_ctrl + 3);
- x.tx_ctrl_cycles_per_up = sr_addr(misc_output_base, x.sr_tx_ctrl + 4);
- x.tx_ctrl_packets_per_up = sr_addr(misc_output_base, x.sr_tx_ctrl + 5);
+ x.misc_ctrl_clock = sr_addr(0);
+ x.misc_ctrl_serdes = sr_addr(1);
+ x.misc_ctrl_adc = sr_addr(2);
+ x.misc_ctrl_leds = sr_addr(3);
+ x.misc_ctrl_phy = sr_addr(4);
+ x.misc_ctrl_dbg_mux = sr_addr(5);
+ x.misc_ctrl_ram_page = sr_addr(6);
+ x.misc_ctrl_flush_icache = sr_addr(7);
+ x.misc_ctrl_led_src = sr_addr(8);
+ x.time64_secs = sr_addr(SR_TIME64 + 0);
+ x.time64_ticks = sr_addr(SR_TIME64 + 1);
+ x.time64_flags = sr_addr(SR_TIME64 + 2);
+ x.time64_imm = sr_addr(SR_TIME64 + 3);
+ x.time64_tps = sr_addr(SR_TIME64 + 4);
+ x.time64_mimo_sync = sr_addr(SR_TIME64 + 5);
+ x.status = READBACK_BASE + 4*8;
+ x.time64_secs_rb_imm = READBACK_BASE + 4*10;
+ x.time64_ticks_rb_imm = READBACK_BASE + 4*11;
+ x.compat_num_rb = READBACK_BASE + 4*12;
+ x.time64_secs_rb_pps = READBACK_BASE + 4*14;
+ x.time64_ticks_rb_pps = READBACK_BASE + 4*15;
+ x.dsp_tx_freq = sr_addr(SR_TX_DSP + 0);
+ x.dsp_tx_scale_iq = sr_addr(SR_TX_DSP + 1);
+ x.dsp_tx_interp_rate = sr_addr(SR_TX_DSP + 2);
+ x.dsp_tx_mux = sr_addr(SR_TX_DSP + 4);
+ x.dsp_rx[0].freq = sr_addr(SR_RX_DSP0 + 0);
+ x.dsp_rx[0].scale_iq = sr_addr(SR_RX_DSP0 + 1);
+ x.dsp_rx[0].decim_rate = sr_addr(SR_RX_DSP0 + 2);
+ x.dsp_rx[0].dcoffset_i = sr_addr(SR_RX_DSP0 + 3);
+ x.dsp_rx[0].dcoffset_q = sr_addr(SR_RX_DSP0 + 4);
+ x.dsp_rx[0].mux = sr_addr(SR_RX_DSP0 + 5);
+ x.dsp_rx[1].freq = sr_addr(SR_RX_DSP1 + 0);
+ x.dsp_rx[1].scale_iq = sr_addr(SR_RX_DSP1 + 1);
+ x.dsp_rx[1].decim_rate = sr_addr(SR_RX_DSP1 + 2);
+ x.dsp_rx[1].dcoffset_i = sr_addr(SR_RX_DSP1 + 3);
+ x.dsp_rx[1].dcoffset_q = sr_addr(SR_RX_DSP1 + 4);
+ x.dsp_rx[1].mux = sr_addr(SR_RX_DSP1 + 5);
+ x.gpio_io = GPIO_BASE + 0;
+ x.gpio_ddr = GPIO_BASE + 4;
+ x.gpio_tx_sel = GPIO_BASE + 8;
+ x.gpio_rx_sel = GPIO_BASE + 12;
+ x.atr_idle_txside = ATR_BASE + 0;
+ x.atr_idle_rxside = ATR_BASE + 2;
+ x.atr_intx_txside = ATR_BASE + 4;
+ x.atr_intx_rxside = ATR_BASE + 6;
+ x.atr_inrx_txside = ATR_BASE + 8;
+ x.atr_inrx_rxside = ATR_BASE + 10;
+ x.atr_full_txside = ATR_BASE + 12;
+ x.atr_full_rxside = ATR_BASE + 14;
+ x.rx_ctrl[0].stream_cmd = sr_addr(SR_RX_CTRL0 + 0);
+ x.rx_ctrl[0].time_secs = sr_addr(SR_RX_CTRL0 + 1);
+ x.rx_ctrl[0].time_ticks = sr_addr(SR_RX_CTRL0 + 2);
+ x.rx_ctrl[0].clear_overrun = sr_addr(SR_RX_CTRL0 + 3);
+ x.rx_ctrl[0].vrt_header = sr_addr(SR_RX_CTRL0 + 4);
+ x.rx_ctrl[0].vrt_stream_id = sr_addr(SR_RX_CTRL0 + 5);
+ x.rx_ctrl[0].vrt_trailer = sr_addr(SR_RX_CTRL0 + 6);
+ x.rx_ctrl[0].nsamps_per_pkt = sr_addr(SR_RX_CTRL0 + 7);
+ x.rx_ctrl[0].nchannels = sr_addr(SR_RX_CTRL0 + 8);
+ x.rx_ctrl[1].stream_cmd = sr_addr(SR_RX_CTRL1 + 0);
+ x.rx_ctrl[1].time_secs = sr_addr(SR_RX_CTRL1 + 1);
+ x.rx_ctrl[1].time_ticks = sr_addr(SR_RX_CTRL1 + 2);
+ x.rx_ctrl[1].clear_overrun = sr_addr(SR_RX_CTRL1 + 3);
+ x.rx_ctrl[1].vrt_header = sr_addr(SR_RX_CTRL1 + 4);
+ x.rx_ctrl[1].vrt_stream_id = sr_addr(SR_RX_CTRL1 + 5);
+ x.rx_ctrl[1].vrt_trailer = sr_addr(SR_RX_CTRL1 + 6);
+ x.rx_ctrl[1].nsamps_per_pkt = sr_addr(SR_RX_CTRL1 + 7);
+ x.rx_ctrl[1].nchannels = sr_addr(SR_RX_CTRL1 + 8);
+ x.tx_ctrl_num_chan = sr_addr(SR_TX_CTRL + 0);
+ x.tx_ctrl_clear_state = sr_addr(SR_TX_CTRL + 1);
+ x.tx_ctrl_report_sid = sr_addr(SR_TX_CTRL + 2);
+ x.tx_ctrl_policy = sr_addr(SR_TX_CTRL + 3);
+ x.tx_ctrl_cycles_per_up = sr_addr(SR_TX_CTRL + 4);
+ x.tx_ctrl_packets_per_up = sr_addr(SR_TX_CTRL + 5);
return x;
}
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index d1fbf3401..8390f065d 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -18,33 +18,7 @@
#ifndef INCLUDED_USRP2_REGS_HPP
#define INCLUDED_USRP2_REGS_HPP
-#include <boost/cstdint.hpp>
-
-#define USRP2_MISC_OUTPUT_BASE 0xD400
-#define USRP2_GPIO_BASE 0xC800
-#define USRP2_ATR_BASE 0xE400
-#define USRP2_BP_STATUS_BASE 0xCC00
-
-#define USRP2P_MISC_OUTPUT_BASE 0x5000
-#define USRP2P_GPIO_BASE 0x6200
-#define USRP2P_ATR_BASE 0x6800
-#define USRP2P_BP_STATUS_BASE 0x6300
-
typedef struct {
- int sr_misc;
- int sr_tx_prot_eng;
- int sr_rx_prot_eng;
- int sr_buffer_pool_ctrl;
- int sr_udp_sm;
- int sr_tx_dsp;
- int sr_tx_ctrl;
- int sr_rx_dsp0;
- int sr_rx_ctrl0;
- int sr_rx_dsp1;
- int sr_rx_ctrl1;
- int sr_time64;
- int sr_simtimer;
- int sr_last;
int misc_ctrl_clock;
int misc_ctrl_serdes;
int misc_ctrl_adc;
@@ -114,7 +88,7 @@ typedef struct {
extern const usrp2_regs_t usrp2_regs; //the register definitions, set in usrp2_regs.cpp and usrp2p_regs.cpp
-usrp2_regs_t usrp2_get_regs(bool);
+usrp2_regs_t usrp2_get_regs(void);
////////////////////////////////////////////////////
// Settings Bus, Slave #7, Not Byte Addressable!
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 22:38:22 +0000