38 files changed, 4017 insertions, 409 deletions

diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt
index 4ca06af9a..eed8b642c 100644
--- a/host/lib/CMakeLists.txt
+++ b/host/lib/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright 2010-2013 Ettus Research LLC
+# Copyright 2010-2014 Ettus Research LLC
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -72,6 +72,7 @@ INCLUDE_SUBDIRECTORY(types)
 INCLUDE_SUBDIRECTORY(convert)
 INCLUDE_SUBDIRECTORY(transport)
 INCLUDE_SUBDIRECTORY(usrp)
+INCLUDE_SUBDIRECTORY(usrp_clock)
 INCLUDE_SUBDIRECTORY(utils)
 
 ########################################################################
diff --git a/host/lib/device.cpp b/host/lib/device.cpp
index ff5163f2d..bd7bf5637 100644
--- a/host/lib/device.cpp
+++ b/host/lib/device.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2011 Ettus Research LLC
+// Copyright 2010-2011,2014 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -57,35 +57,38 @@ static size_t hash_device_addr(
 /***********************************************************************
  * Registration
  **********************************************************************/
-typedef boost::tuple<device::find_t, device::make_t> dev_fcn_reg_t;
+typedef boost::tuple<device::find_t, device::make_t, device::device_filter_t> dev_fcn_reg_t;
 
 // instantiate the device function registry container
 UHD_SINGLETON_FCN(std::vector<dev_fcn_reg_t>, get_dev_fcn_regs)
 
 void device::register_device(
     const find_t &find,
-    const make_t &make
+    const make_t &make,
+    const device_filter_t filter
 ){
     UHD_LOGV(always) << "registering device" << std::endl;
-    get_dev_fcn_regs().push_back(dev_fcn_reg_t(find, make));
+    get_dev_fcn_regs().push_back(dev_fcn_reg_t(find, make, filter));
 }
 
 /***********************************************************************
  * Discover
  **********************************************************************/
-device_addrs_t device::find(const device_addr_t &hint){
+device_addrs_t device::find(const device_addr_t &hint, device_filter_t filter){
     boost::mutex::scoped_lock lock(_device_mutex);
 
     device_addrs_t device_addrs;
 
     BOOST_FOREACH(const dev_fcn_reg_t &fcn, get_dev_fcn_regs()){
         try{
-            device_addrs_t discovered_addrs = fcn.get<0>()(hint);
-            device_addrs.insert(
-                device_addrs.begin(),
-                discovered_addrs.begin(),
-                discovered_addrs.end()
-            );
+            if(filter == ANY or fcn.get<2>() == filter){
+                device_addrs_t discovered_addrs = fcn.get<0>()(hint);
+                device_addrs.insert(
+                    device_addrs.begin(),
+                    discovered_addrs.begin(),
+                    discovered_addrs.end()
+                );
+            }
         }
         catch(const std::exception &e){
             UHD_MSG(error) << "Device discovery error: " << e.what() << std::endl;
@@ -98,16 +101,18 @@ device_addrs_t device::find(const device_addr_t &hint){
 /***********************************************************************
  * Make
  **********************************************************************/
-device::sptr device::make(const device_addr_t &hint, size_t which){
+device::sptr device::make(const device_addr_t &hint, device_filter_t filter, size_t which){
     boost::mutex::scoped_lock lock(_device_mutex);
 
     typedef boost::tuple<device_addr_t, make_t> dev_addr_make_t;
     std::vector<dev_addr_make_t> dev_addr_makers;
 
     BOOST_FOREACH(const dev_fcn_reg_t &fcn, get_dev_fcn_regs()){
-        BOOST_FOREACH(device_addr_t dev_addr, fcn.get<0>()(hint)){
-            //append the discovered address and its factory function
-            dev_addr_makers.push_back(dev_addr_make_t(dev_addr, fcn.get<1>()));
+        if(filter == ANY or fcn.get<2>() == filter){
+            BOOST_FOREACH(device_addr_t dev_addr, fcn.get<0>()(hint)){
+                //append the discovered address and its factory function
+                dev_addr_makers.push_back(dev_addr_make_t(dev_addr, fcn.get<1>()));
+            }
         }
     }
 
@@ -159,3 +164,7 @@ device::get_tree(void) const
 {
     return _tree;
 }
+
+device::device_filter_t device::get_device_type() const {
+    return _type;
+}
diff --git a/host/lib/usrp/b100/b100_impl.cpp b/host/lib/usrp/b100/b100_impl.cpp
index baf2b6ae3..26b0a5aea 100644
--- a/host/lib/usrp/b100/b100_impl.cpp
+++ b/host/lib/usrp/b100/b100_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2012-2013 Ettus Research LLC
+// Copyright 2012-2014 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -137,7 +137,7 @@ static device::sptr b100_make(const device_addr_t &device_addr){
 }
 
 UHD_STATIC_BLOCK(register_b100_device){
-    device::register_device(&b100_find, &b100_make);
+    device::register_device(&b100_find, &b100_make, device::USRP);
 }
 
 /***********************************************************************
@@ -148,6 +148,7 @@ b100_impl::b100_impl(const device_addr_t &device_addr){
     b100_impl_constructor_begin:
     initialization_count++;
 
+    _type = device::USRP;
     _tree = property_tree::make();
 
     //extract the FPGA path for the B100
diff --git a/host/lib/usrp/b100/usb_zero_copy_wrapper.cpp b/host/lib/usrp/b100/usb_zero_copy_wrapper.cpp
index 451cdae50..d646fcc94 100644
--- a/host/lib/usrp/b100/usb_zero_copy_wrapper.cpp
+++ b/host/lib/usrp/b100/usb_zero_copy_wrapper.cpp
@@ -55,6 +55,7 @@ public:
         index++; //advances the caller's buffer
 
         //hold a copy of the buffer shared pointer
+        UHD_ASSERT_THROW(not _mrb);
         _mrb = mrb;
 
         //extract this packet's memory address and length in bytes
@@ -199,7 +200,7 @@ public:
     }
 
     size_t get_num_recv_frames(void) const{
-        return _internal_zc->get_num_recv_frames();
+        return (_internal_zc->get_num_recv_frames()*_internal_zc->get_recv_frame_size())/this->get_recv_frame_size();
     }
 
     size_t get_recv_frame_size(void) const{
diff --git a/host/lib/usrp/b200/CMakeLists.txt b/host/lib/usrp/b200/CMakeLists.txt
index 3d8aad052..a08c4bd03 100644
--- a/host/lib/usrp/b200/CMakeLists.txt
+++ b/host/lib/usrp/b200/CMakeLists.txt
@@ -30,5 +30,6 @@ IF(ENABLE_B200)
         ${CMAKE_CURRENT_SOURCE_DIR}/b200_iface.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/b200_io_impl.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/b200_uart.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/b200_cores.cpp
     )
 ENDIF(ENABLE_B200)
diff --git a/host/lib/usrp/b200/b200_cores.cpp b/host/lib/usrp/b200/b200_cores.cpp
new file mode 100644
index 000000000..19e637ef4
--- /dev/null
+++ b/host/lib/usrp/b200/b200_cores.cpp
@@ -0,0 +1,83 @@
+//
+// Copyright 2013-2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "b200_cores.hpp"
+#include "b200_regs.hpp"
+#include "b200_impl.hpp"
+
+b200_local_spi_core::b200_local_spi_core(
+    uhd::wb_iface::sptr iface,
+    perif_t default_perif) :
+    _spi_core(spi_core_3000::make(iface, TOREG(SR_CORE_SPI), RB32_CORE_SPI)),
+    _current_perif(default_perif),
+    _last_perif(default_perif)
+{
+    change_perif(default_perif);
+}
+
+boost::uint32_t b200_local_spi_core::transact_spi(
+    int which_slave,
+    const uhd::spi_config_t &config,
+    boost::uint32_t data,
+    size_t num_bits,
+    bool readback)
+{
+    boost::mutex::scoped_lock lock(_mutex);
+    return _spi_core->transact_spi(which_slave, config, data, num_bits, readback);
+}
+
+void b200_local_spi_core::change_perif(perif_t perif)
+{
+    boost::mutex::scoped_lock lock(_mutex);
+    _last_perif = _current_perif;
+    _current_perif = perif;
+
+    switch (_current_perif) {
+        case CODEC:
+            _spi_core->set_divider(B200_BUS_CLOCK_RATE/AD9361_SPI_RATE);
+            break;
+        case PLL:
+            _spi_core->set_divider(B200_BUS_CLOCK_RATE/ADF4001_SPI_RATE);
+            break;
+    }
+}
+
+void b200_local_spi_core::restore_perif()
+{
+    change_perif(_last_perif);
+}
+
+b200_ref_pll_ctrl::b200_ref_pll_ctrl(b200_local_spi_core::sptr spi) :
+    uhd::usrp::adf4001_ctrl(spi, ADF4001_SLAVENO),
+    _spi(spi)
+{
+}
+
+void b200_ref_pll_ctrl::set_lock_to_ext_ref(bool external)
+{
+    _spi->change_perif(b200_local_spi_core::PLL);
+    adf4001_ctrl::set_lock_to_ext_ref(external);
+    _spi->restore_perif();
+}
+
+
+b200_local_spi_core::sptr b200_local_spi_core::make(
+    uhd::wb_iface::sptr iface, b200_local_spi_core::perif_t default_perif)
+{
+    return sptr(new b200_local_spi_core(iface, default_perif));
+}
+
diff --git a/host/lib/usrp/b200/b200_cores.hpp b/host/lib/usrp/b200/b200_cores.hpp
new file mode 100644
index 000000000..8a8900412
--- /dev/null
+++ b/host/lib/usrp/b200/b200_cores.hpp
@@ -0,0 +1,66 @@
+//
+// Copyright 2013-2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_B200_CORES_HPP
+#define INCLUDED_B200_CORES_HPP
+
+#include "spi_core_3000.hpp"
+#include "adf4001_ctrl.hpp"
+#include <boost/thread/mutex.hpp>
+
+class b200_local_spi_core : boost::noncopyable, public uhd::spi_iface {
+
+public:
+    typedef boost::shared_ptr<b200_local_spi_core> sptr;
+
+    enum perif_t {
+        CODEC, PLL
+    };
+
+    b200_local_spi_core(uhd::wb_iface::sptr iface, perif_t default_perif);
+
+    virtual boost::uint32_t transact_spi(
+        int which_slave,
+        const uhd::spi_config_t &config,
+        boost::uint32_t data,
+        size_t num_bits,
+        bool readback);
+
+    void change_perif(perif_t perif);
+    void restore_perif();
+
+    static sptr make(uhd::wb_iface::sptr iface, perif_t default_perif = CODEC);
+
+private:
+    spi_core_3000::sptr     _spi_core;
+    perif_t                 _current_perif;
+    perif_t                 _last_perif;
+    boost::mutex            _mutex;
+};
+
+class b200_ref_pll_ctrl : public uhd::usrp::adf4001_ctrl {
+public:
+    typedef boost::shared_ptr<b200_ref_pll_ctrl> sptr;
+
+    b200_ref_pll_ctrl(b200_local_spi_core::sptr spi);
+    void set_lock_to_ext_ref(bool external);
+
+private:
+    b200_local_spi_core::sptr _spi;
+};
+
+#endif /* INCLUDED_B200_CORES_HPP */
diff --git a/host/lib/usrp/b200/b200_iface.cpp b/host/lib/usrp/b200/b200_iface.cpp
index efb9b3a35..820090959 100644
--- a/host/lib/usrp/b200/b200_iface.cpp
+++ b/host/lib/usrp/b200/b200_iface.cpp
@@ -57,15 +57,11 @@ const static boost::uint8_t B200_VREQ_GET_FPGA_HASH = 0x1D;
 const static boost::uint8_t B200_VREQ_SET_FW_HASH = 0x1E;
 const static boost::uint8_t B200_VREQ_GET_FW_HASH = 0x1F;
 const static boost::uint8_t B200_VREQ_LOOP = 0x22;
-const static boost::uint8_t B200_VREQ_SPI_WRITE = 0x32;
-const static boost::uint8_t B200_VREQ_SPI_READ = 0x42;
 const static boost::uint8_t B200_VREQ_FPGA_CONFIG = 0x55;
 const static boost::uint8_t B200_VREQ_FPGA_RESET = 0x62;
 const static boost::uint8_t B200_VREQ_GPIF_RESET = 0x72;
 const static boost::uint8_t B200_VREQ_GET_USB = 0x80;
 const static boost::uint8_t B200_VREQ_GET_STATUS = 0x83;
-const static boost::uint8_t B200_VREQ_AD9361_CTRL_WRITE = 0x90;
-const static boost::uint8_t B200_VREQ_AD9361_CTRL_READ = 0x91;
 const static boost::uint8_t B200_VREQ_FX3_RESET = 0x99;
 const static boost::uint8_t B200_VREQ_EEPROM_WRITE = 0xBA;
 const static boost::uint8_t B200_VREQ_EEPROM_READ = 0xBB;
@@ -270,82 +266,6 @@ public:
         return recv_bytes;
     }
 
-    void transact_spi(
-        unsigned char *tx_data,
-        size_t num_tx_bits,
-        unsigned char *rx_data,
-        size_t num_rx_bits) {
-        int ret = 0;
-        boost::uint16_t tx_length = num_tx_bits / 8;
-
-        if(tx_data[0] & 0x80) {
-            ret = fx3_control_write(B200_VREQ_SPI_WRITE, 0x00, \
-                    0x00, tx_data, tx_length);
-        } else {
-            ret = fx3_control_write(B200_VREQ_SPI_READ, 0x00, \
-                    0x00, tx_data, tx_length);
-        }
-
-        if (ret < 0)
-            throw uhd::io_error((boost::format("Failed to write SPI (%d: %s)") % ret % libusb_error_name(ret)).str());
-        else if (ret != tx_length)
-            throw uhd::io_error((boost::format("Short write on write SPI (expecting: %d, returned: %d)") % tx_length % ret).str());
-
-
-        if(num_rx_bits) {
-            boost::uint16_t total_length = num_rx_bits / 8;
-
-            ret = fx3_control_read(B200_VREQ_LOOP, 0x00, \
-                    0x00, rx_data, total_length);
-
-            if (ret < 0)
-                throw uhd::io_error((boost::format("Failed to readback (%d: %s)") % ret % libusb_error_name(ret)).str());
-            else if (ret != total_length)
-                throw uhd::io_error((boost::format("Short read on readback (expecting: %d, returned: %d)") % total_length % ret).str());
-        }
-    }
-
-    void ad9361_transact(const unsigned char in_buff[AD9361_DISPATCH_PACKET_SIZE], unsigned char out_buff[AD9361_DISPATCH_PACKET_SIZE]) {
-        const int bytes_to_write = AD9361_DISPATCH_PACKET_SIZE;
-        const int bytes_to_read = AD9361_DISPATCH_PACKET_SIZE;
-        const size_t read_retries = 5;
-
-        int ret = fx3_control_write(B200_VREQ_AD9361_CTRL_WRITE, 0x00, 0x00, (unsigned char *)in_buff, bytes_to_write);
-        if (ret < 0)
-            throw uhd::io_error((boost::format("Failed to write AD9361 (%d: %s)") % ret % libusb_error_name(ret)).str());
-        else if (ret != bytes_to_write)
-            throw uhd::io_error((boost::format("Short write on write AD9361 (expecting: %d, returned: %d)") % bytes_to_write % ret).str());
-
-        for (size_t i = 0; i < read_retries; i++)
-        {
-            ret = fx3_control_read(B200_VREQ_AD9361_CTRL_READ, 0x00, 0x00, out_buff, bytes_to_read, 3000);
-            if (ret < 0)
-            {
-                if (ret == LIBUSB_ERROR_TIMEOUT)
-                {
-                    UHD_LOG << (boost::format("Failed to read AD9361 (%d: %s). Retrying (%d of %d)...")
-                            % ret
-                            % libusb_error_name(ret)
-                            % (i+1)
-                            % read_retries
-                        ) << std::endl;
-                }
-                else
-                {
-                    throw uhd::io_error((boost::format("Failed to read AD9361 (%d: %s)")
-                        % ret
-                        % libusb_error_name(ret)
-                    ).str());
-                }
-            }
-
-            if (ret == bytes_to_read)
-                return;
-        }
-
-        throw uhd::io_error(str(boost::format("Failed to read complete AD9361 (expecting: %d, last read: %d)") % bytes_to_read % ret));
-    }
-
     void load_firmware(const std::string filestring, UHD_UNUSED(bool force) = false)
     {
         const char *filename = filestring.c_str();
diff --git a/host/lib/usrp/b200/b200_iface.hpp b/host/lib/usrp/b200/b200_iface.hpp
index 20b4a7a89..83adfdd64 100644
--- a/host/lib/usrp/b200/b200_iface.hpp
+++ b/host/lib/usrp/b200/b200_iface.hpp
@@ -35,8 +35,7 @@ static const std::string     B200_FW_FILE_NAME = "usrp_b200_fw.hex";
 static const std::string     B200_FPGA_FILE_NAME = "usrp_b200_fpga.bin";
 static const std::string     B210_FPGA_FILE_NAME = "usrp_b210_fpga.bin";
 
-class UHD_API b200_iface: boost::noncopyable, public virtual uhd::i2c_iface,
-                  public ad9361_ctrl_iface_type {
+class UHD_API b200_iface: boost::noncopyable, public virtual uhd::i2c_iface {
 public:
     typedef boost::shared_ptr<b200_iface> sptr;
 
@@ -71,10 +70,6 @@ public:
     //! load an FPGA image
     virtual boost::uint32_t load_fpga(const std::string filestring) = 0;
 
-    //! send SPI through the FX3
-    virtual void transact_spi( unsigned char *tx_data, size_t num_tx_bits, \
-            unsigned char *rx_data, size_t num_rx_bits) = 0;
-
     virtual void write_eeprom(boost::uint16_t addr, boost::uint16_t offset, const uhd::byte_vector_t &bytes) = 0;
 
     virtual uhd::byte_vector_t read_eeprom(boost::uint16_t addr, boost::uint16_t offset, size_t num_bytes) = 0;
diff --git a/host/lib/usrp/b200/b200_impl.cpp b/host/lib/usrp/b200/b200_impl.cpp
index bf5fdd251..5c9324cb9 100644
--- a/host/lib/usrp/b200/b200_impl.cpp
+++ b/host/lib/usrp/b200/b200_impl.cpp
@@ -31,6 +31,7 @@
 #include <boost/thread/thread.hpp>
 #include <boost/lexical_cast.hpp>
 #include <boost/functional/hash.hpp>
+#include <boost/make_shared.hpp>
 #include <cstdio>
 #include <ctime>
 #include <cmath>
@@ -45,6 +46,33 @@ static const boost::posix_time::milliseconds REENUMERATION_TIMEOUT_MS(3000);
 static const size_t FE1 = 1;
 static const size_t FE2 = 0;
 
+class b200_ad9361_client_t : public ad9361_params {
+public:
+    ~b200_ad9361_client_t() {}
+    double get_band_edge(frequency_band_t band) {
+        switch (band) {
+        case AD9361_RX_BAND0:   return 2.2e9;
+        case AD9361_RX_BAND1:   return 4.0e9;
+        case AD9361_TX_BAND0:   return 2.5e9;
+        default:                return 0;
+        }
+    }
+    clocking_mode_t get_clocking_mode() {
+        return AD9361_XTAL_N_CLK_PATH;
+    }
+    digital_interface_mode_t get_digital_interface_mode() {
+        return AD9361_DDR_FDD_LVCMOS;
+    }
+    digital_interface_delays_t get_digital_interface_timing() {
+        digital_interface_delays_t delays;
+        delays.rx_clk_delay = 0;
+        delays.rx_data_delay = 0xF;
+        delays.tx_clk_delay = 0;
+        delays.tx_data_delay = 0xF;
+        return delays;
+    }
+};
+
 /***********************************************************************
  * Discovery
  **********************************************************************/
@@ -146,7 +174,7 @@ static device::sptr b200_make(const device_addr_t &device_addr)
 
 UHD_STATIC_BLOCK(register_b200_device)
 {
-    device::register_device(&b200_find, &b200_make);
+    device::register_device(&b200_find, &b200_make, device::USRP);
 }
 
 /***********************************************************************
@@ -155,6 +183,7 @@ UHD_STATIC_BLOCK(register_b200_device)
 b200_impl::b200_impl(const device_addr_t &device_addr)
 {
     _tree = property_tree::make();
+    _type = device::USRP;
     const fs_path mb_path = "/mboards/0";
 
     //try to match the given device address with something on the USB bus
@@ -338,10 +367,17 @@ b200_impl::b200_impl(const device_addr_t &device_addr)
     _demux = recv_packet_demuxer_3000::make(_data_transport);
 
     ////////////////////////////////////////////////////////////////////
+    // create time and clock control objects
+    ////////////////////////////////////////////////////////////////////
+    _spi_iface = b200_local_spi_core::make(_local_ctrl);
+    _adf4001_iface = boost::make_shared<b200_ref_pll_ctrl>(_spi_iface);
+
+    ////////////////////////////////////////////////////////////////////
     // Init codec - turns on clocks
     ////////////////////////////////////////////////////////////////////
     UHD_MSG(status) << "Initialize CODEC control..." << std::endl;
-    _codec_ctrl = ad9361_ctrl::make(_iface);
+    ad9361_params::sptr client_settings = boost::make_shared<b200_ad9361_client_t>();
+    _codec_ctrl = ad9361_ctrl::make_spi(client_settings, _spi_iface, AD9361_SLAVENO);
     this->reset_codec_dcm();
 
     ////////////////////////////////////////////////////////////////////
@@ -404,13 +440,6 @@ b200_impl::b200_impl(const device_addr_t &device_addr)
     }
     _codec_ctrl->data_port_loopback(false);
 
-    ////////////////////////////////////////////////////////////////////
-    // create time and clock control objects
-    ////////////////////////////////////////////////////////////////////
-    _spi_iface = spi_core_3000::make(_local_ctrl, TOREG(SR_CORE_SPI), RB32_CORE_SPI);
-    _spi_iface->set_divider(B200_BUS_CLOCK_RATE/ADF4001_SPI_RATE);
-    _adf4001_iface = boost::shared_ptr<adf4001_ctrl>(new adf4001_ctrl(_spi_iface, ADF4001_SLAVENO));
-
     //register time now and pps onto available radio cores
     _tree->create<time_spec_t>(mb_path / "time" / "now")
         .publish(boost::bind(&time_core_3000::get_time_now, _radio_perifs[0].time64));
@@ -680,7 +709,7 @@ void b200_impl::enforce_tick_rate_limits(size_t chan_count, double tick_rate, co
     }
     else
     {
-        const double max_tick_rate = ((chan_count <= 1) ? AD9361_1_CHAN_CLOCK_RATE_MAX : AD9361_2_CHAN_CLOCK_RATE_MAX);
+        const double max_tick_rate = ad9361_device_t::AD9361_MAX_CLOCK_RATE / ((chan_count <= 1) ? 1 : 2);
         if (tick_rate - max_tick_rate >= 1.0)
         {
             throw uhd::value_error(boost::str(
diff --git a/host/lib/usrp/b200/b200_impl.hpp b/host/lib/usrp/b200/b200_impl.hpp
index c3508c550..155ff699c 100644
--- a/host/lib/usrp/b200/b200_impl.hpp
+++ b/host/lib/usrp/b200/b200_impl.hpp
@@ -20,6 +20,7 @@
 
 #include "b200_iface.hpp"
 #include "b200_uart.hpp"
+#include "b200_cores.hpp"
 #include "ad9361_ctrl.hpp"
 #include "adf4001_ctrl.hpp"
 #include "rx_vita_core_3000.hpp"
@@ -44,9 +45,9 @@
 #include <uhd/transport/bounded_buffer.hpp>
 #include <boost/weak_ptr.hpp>
 #include "recv_packet_demuxer_3000.hpp"
-static const boost::uint8_t  B200_FW_COMPAT_NUM_MAJOR = 0x04;
+static const boost::uint8_t  B200_FW_COMPAT_NUM_MAJOR = 0x06;
 static const boost::uint8_t  B200_FW_COMPAT_NUM_MINOR = 0x00;
-static const boost::uint16_t B200_FPGA_COMPAT_NUM = 0x03;
+static const boost::uint16_t B200_FPGA_COMPAT_NUM = 0x04;
 static const double          B200_BUS_CLOCK_RATE = 100e6;
 static const double          B200_DEFAULT_TICK_RATE = 32e6;
 static const boost::uint32_t B200_GPSDO_ST_NONE = 0x83;
@@ -99,8 +100,8 @@ private:
     //controllers
     b200_iface::sptr _iface;
     radio_ctrl_core_3000::sptr _local_ctrl;
-    ad9361_ctrl::sptr _codec_ctrl;
-    spi_core_3000::sptr _spi_iface;
+    uhd::usrp::ad9361_ctrl::sptr _codec_ctrl;
+    b200_local_spi_core::sptr _spi_iface;
     boost::shared_ptr<uhd::usrp::adf4001_ctrl> _adf4001_iface;
     uhd::gps_ctrl::sptr _gps;
 
diff --git a/host/lib/usrp/b200/b200_regs.hpp b/host/lib/usrp/b200/b200_regs.hpp
index c64066b27..dc8a6b0dc 100644
--- a/host/lib/usrp/b200/b200_regs.hpp
+++ b/host/lib/usrp/b200/b200_regs.hpp
@@ -52,7 +52,9 @@ localparam RB64_TIME_PPS        = 16;
 localparam RB64_CODEC_READBACK  = 24;
 
 //pll constants
+static const int AD9361_SLAVENO = (1 << 0);
 static const int ADF4001_SLAVENO = (1 << 1);
+static const double AD9361_SPI_RATE = 1e6;
 static const double ADF4001_SPI_RATE = 10e3; //slow for large time constant on spi lines
 
 /* ATR Control Bits */
diff --git a/host/lib/usrp/common/CMakeLists.txt b/host/lib/usrp/common/CMakeLists.txt
index b99464873..129cc569b 100644
--- a/host/lib/usrp/common/CMakeLists.txt
+++ b/host/lib/usrp/common/CMakeLists.txt
@@ -27,11 +27,13 @@ IF(ENABLE_USB)
 ENDIF(ENABLE_USB)
 
 INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR})
+INCLUDE_DIRECTORIES("${CMAKE_CURRENT_SOURCE_DIR}/ad9361_driver")
 
 LIBUHD_APPEND_SOURCES(
     ${CMAKE_CURRENT_SOURCE_DIR}/adf4001_ctrl.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/adf435x_common.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/ad9361_ctrl.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/ad9361_driver/ad9361_device.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/apply_corrections.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/validate_subdev_spec.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/recv_packet_demuxer.cpp
diff --git a/host/lib/usrp/common/ad9361_ctrl.cpp b/host/lib/usrp/common/ad9361_ctrl.cpp
index 10496f2a9..dea18ff06 100644
--- a/host/lib/usrp/common/ad9361_ctrl.cpp
+++ b/host/lib/usrp/common/ad9361_ctrl.cpp
@@ -1,70 +1,105 @@
 //
-// Copyright 2012-2013 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+// Copyright 2014 Ettus Research LLC
 //
 
 #include "ad9361_ctrl.hpp"
-#include "ad9361_transaction.h"
 #include <uhd/exception.hpp>
 #include <uhd/types/ranges.hpp>
 #include <uhd/utils/msg.hpp>
-#include <boost/thread/mutex.hpp>
-#include <boost/format.hpp>
+#include <uhd/types/serial.hpp>
 #include <cstring>
-
-//! compat strnlen for platforms that dont have it
-static size_t my_strnlen(const char *str, size_t max)
-{
-    const char *end = (const char *)std::memchr((const void *)str, 0, max);
-    if (end == NULL) return max;
-    return (size_t)(end - str);
-}
+#include <boost/format.hpp>
+#include <boost/utility.hpp>
+#include <boost/function.hpp>
+#include <boost/make_shared.hpp>
+#include <boost/thread.hpp>
 
 using namespace uhd;
+using namespace uhd::usrp;
+
+/***********************************************************************
+ * AD9361 IO Implementation Classes
+ **********************************************************************/
 
-struct ad9361_ctrl_impl : public ad9361_ctrl
+class ad9361_io_spi : public ad9361_io
 {
-    ad9361_ctrl_impl(ad9361_ctrl_iface_sptr iface):
-        _iface(iface), _seq(0)
+public:
+    ad9361_io_spi(uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num) :
+        _spi_iface(spi_iface), _slave_num(slave_num) { }
+
+    virtual ~ad9361_io_spi() { }
+
+    virtual boost::uint8_t peek8(boost::uint32_t reg)
     {
-        ad9361_transaction_t request;
+        boost::lock_guard<boost::mutex> lock(_mutex);
+
+        uhd::spi_config_t config;
+        config.mosi_edge = uhd::spi_config_t::EDGE_FALL;
+        config.miso_edge = uhd::spi_config_t::EDGE_FALL;    //TODO (Ashish): FPGA SPI workaround. This should be EDGE_RISE
 
-        request.action = AD9361_ACTION_ECHO;
-        this->do_transaction(request);
+        boost::uint32_t rd_word = AD9361_SPI_READ_CMD |
+                           ((boost::uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK);
 
-        request.action = AD9361_ACTION_INIT;
-        this->do_transaction(request);
+        boost::uint32_t val = (_spi_iface->read_spi(_slave_num, config, rd_word, AD9361_SPI_NUM_BITS));
+        val &= 0xFF;
+
+        return static_cast<boost::uint8_t>(val);
     }
 
-    double set_gain(const std::string &which, const double value)
+    virtual void poke8(boost::uint32_t reg, boost::uint8_t val)
+    {
+        boost::lock_guard<boost::mutex> lock(_mutex);
+
+        uhd::spi_config_t config;
+        config.mosi_edge = uhd::spi_config_t::EDGE_FALL;
+        config.miso_edge = uhd::spi_config_t::EDGE_FALL;    //TODO (Ashish): FPGA SPI workaround. This should be EDGE_RISE
+
+        boost::uint32_t wr_word = AD9361_SPI_WRITE_CMD |
+                           ((boost::uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK) |
+                           ((boost::uint32_t(val) << AD9361_SPI_DATA_SHIFT) & AD9361_SPI_DATA_MASK);
+        _spi_iface->write_spi(_slave_num, config, wr_word, AD9361_SPI_NUM_BITS);
+    }
+
+private:
+    uhd::spi_iface::sptr    _spi_iface;
+    boost::uint32_t         _slave_num;
+    boost::mutex            _mutex;
+
+    static const boost::uint32_t AD9361_SPI_WRITE_CMD  = 0x00800000;
+    static const boost::uint32_t AD9361_SPI_READ_CMD   = 0x00000000;
+    static const boost::uint32_t AD9361_SPI_ADDR_MASK  = 0x003FFF00;
+    static const boost::uint32_t AD9361_SPI_ADDR_SHIFT = 8;
+    static const boost::uint32_t AD9361_SPI_DATA_MASK  = 0x000000FF;
+    static const boost::uint32_t AD9361_SPI_DATA_SHIFT = 0;
+    static const boost::uint32_t AD9361_SPI_NUM_BITS   = 24;
+};
+
+/***********************************************************************
+ * AD9361 Control API Class
+ **********************************************************************/
+class ad9361_ctrl_impl : public ad9361_ctrl
+{
+public:
+    ad9361_ctrl_impl(ad9361_params::sptr client_settings, ad9361_io::sptr io_iface):
+        _device(client_settings, io_iface)
     {
-        ad9361_transaction_t request;
+        _device.initialize();
+    }
 
-        if (which == "RX1") request.action = AD9361_ACTION_SET_RX1_GAIN;
-        if (which == "RX2") request.action = AD9361_ACTION_SET_RX2_GAIN;
-        if (which == "TX1") request.action = AD9361_ACTION_SET_TX1_GAIN;
-        if (which == "TX2") request.action = AD9361_ACTION_SET_TX2_GAIN;
+    double set_gain(const std::string &which, const double value)
+    {
+        boost::lock_guard<boost::mutex> lock(_mutex);
 
-        ad9361_double_pack(value, request.value.gain);
-        const ad9361_transaction_t reply = this->do_transaction(request);
-        return ad9361_double_unpack(reply.value.gain);
+        ad9361_device_t::direction_t direction = _get_direction_from_antenna(which);
+        ad9361_device_t::chain_t chain =_get_chain_from_antenna(which);
+        return _device.set_gain(direction, chain, value);
     }
 
     //! set a new clock rate, return the exact value
     double set_clock_rate(const double rate)
     {
+        boost::lock_guard<boost::mutex> lock(_mutex);
+
         //warning for known trouble rates
         if (rate > 56e6) UHD_MSG(warning) << boost::format(
             "The requested clock rate %f MHz may cause slow configuration.\n"
@@ -75,99 +110,76 @@ struct ad9361_ctrl_impl : public ad9361_ctrl
         const meta_range_t clock_rate_range = ad9361_ctrl::get_clock_rate_range();
         const double clipped_rate = clock_rate_range.clip(rate);
 
-        ad9361_transaction_t request;
-        request.action = AD9361_ACTION_SET_CLOCK_RATE;
-        ad9361_double_pack(clipped_rate, request.value.rate);
-        const ad9361_transaction_t reply = this->do_transaction(request);
-        return ad9361_double_unpack(reply.value.rate);
+        return _device.set_clock_rate(clipped_rate);
     }
 
     //! set which RX and TX chains/antennas are active
     void set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2)
     {
-        boost::uint32_t mask = 0;
-        if (tx1) mask |= (1 << 0);
-        if (tx2) mask |= (1 << 1);
-        if (rx1) mask |= (1 << 2);
-        if (rx2) mask |= (1 << 3);
-
-        ad9361_transaction_t request;
-        request.action = AD9361_ACTION_SET_ACTIVE_CHAINS;
-        request.value.enable_mask = mask;
-        this->do_transaction(request);
+        boost::lock_guard<boost::mutex> lock(_mutex);
+
+        _device.set_active_chains(tx1, tx2, rx1, rx2);
     }
 
     //! tune the given frontend, return the exact value
     double tune(const std::string &which, const double freq)
     {
+        boost::lock_guard<boost::mutex> lock(_mutex);
+
         //clip to known bounds
         const meta_range_t freq_range = ad9361_ctrl::get_rf_freq_range();
         const double clipped_freq = freq_range.clip(freq);
-
-        ad9361_transaction_t request;
-
-        if (which[0] == 'R') request.action = AD9361_ACTION_SET_RX_FREQ;
-        if (which[0] == 'T') request.action = AD9361_ACTION_SET_TX_FREQ;
-
         const double value = ad9361_ctrl::get_rf_freq_range().clip(clipped_freq);
-        ad9361_double_pack(value, request.value.freq);
-        const ad9361_transaction_t reply = this->do_transaction(request);
-        return ad9361_double_unpack(reply.value.freq);
+
+        ad9361_device_t::direction_t direction = _get_direction_from_antenna(which);
+        return _device.tune(direction, value);
     }
 
     //! turn on/off Catalina's data port loopback
     void data_port_loopback(const bool on)
     {
-        ad9361_transaction_t request;
-        request.action = AD9361_ACTION_SET_CODEC_LOOP;
-        request.value.codec_loop = on? 1 : 0;
-        this->do_transaction(request);
+        boost::lock_guard<boost::mutex> lock(_mutex);
+
+        _device.data_port_loopback(on);
     }
 
-    ad9361_transaction_t do_transaction(const ad9361_transaction_t &request)
+private:
+    static ad9361_device_t::direction_t _get_direction_from_antenna(const std::string& antenna)
     {
-        boost::mutex::scoped_lock lock(_mutex);
-
-        //declare in/out buffers
-        unsigned char in_buff[64] = {};
-        unsigned char out_buff[64] = {};
-
-        //copy the input transaction
-        std::memcpy(in_buff, &request, sizeof(request));
-    
-        //fill in other goodies
-        ad9361_transaction_t *in = (ad9361_transaction_t *)in_buff;
-        in->version = AD9361_TRANSACTION_VERSION;
-        in->sequence = _seq++;
-
-        //transact
-        _iface->ad9361_transact(in_buff, out_buff);
-        ad9361_transaction_t *out = (ad9361_transaction_t *)out_buff;
-
-        //sanity checks
-        UHD_ASSERT_THROW(out->version == in->version);
-        UHD_ASSERT_THROW(out->sequence == in->sequence);
-
-        //handle errors
-        const size_t len = my_strnlen(out->error_msg, AD9361_TRANSACTION_MAX_ERROR_MSG);
-        const std::string error_msg(out->error_msg, len);
-        if (not error_msg.empty()) throw uhd::runtime_error("[ad9361_ctrl::do_transaction] firmware reported: \"" + error_msg + "\"");
-
-        //return result done!
-        return *out;
+        std::string sub = antenna.substr(0, 2);
+        if (sub == "RX") {
+            return ad9361_device_t::RX;
+        } else if (sub == "TX") {
+            return ad9361_device_t::TX;
+        } else {
+            throw uhd::runtime_error("ad9361_ctrl got an invalid channel string.");
+        }
+        return ad9361_device_t::RX;
     }
 
-    ad9361_ctrl_iface_sptr _iface;
-    size_t _seq;
-    boost::mutex _mutex;
+    static ad9361_device_t::chain_t _get_chain_from_antenna(const std::string& antenna)
+    {
+        std::string sub = antenna.substr(2, 1);
+        if (sub == "1") {
+            return ad9361_device_t::CHAIN_1;
+        } else if (sub == "2") {
+            return ad9361_device_t::CHAIN_2;
+        } else {
+            throw uhd::runtime_error("ad9361_ctrl::set_gain got an invalid channel string.");
+        }
+        return ad9361_device_t::CHAIN_1;
+    }
 
+    ad9361_device_t _device;
+    boost::mutex    _mutex;
 };
 
-
-/***********************************************************************
- * Make an instance of the implementation
- **********************************************************************/
-ad9361_ctrl::sptr ad9361_ctrl::make(ad9361_ctrl_iface_sptr iface)
+//----------------------------------------------------------------------
+// Make an instance of the AD9361 Control interface
+//----------------------------------------------------------------------
+ad9361_ctrl::sptr ad9361_ctrl::make_spi(
+    ad9361_params::sptr client_settings, uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num)
 {
-    return sptr(new ad9361_ctrl_impl(iface));
+    boost::shared_ptr<ad9361_io_spi> spi_io_iface = boost::make_shared<ad9361_io_spi>(spi_iface, slave_num);
+    return sptr(new ad9361_ctrl_impl(client_settings, spi_io_iface));
 }
diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp
index 098b5dae8..f1659f30e 100644
--- a/host/lib/usrp/common/ad9361_ctrl.hpp
+++ b/host/lib/usrp/common/ad9361_ctrl.hpp
@@ -1,79 +1,30 @@
 //
-// Copyright 2012-2013 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+// Copyright 2014 Ettus Research LLC
 //
 
 #ifndef INCLUDED_AD9361_CTRL_HPP
 #define INCLUDED_AD9361_CTRL_HPP
 
 #include <uhd/transport/zero_copy.hpp>
-#include <uhd/types/serial.hpp>
 #include <uhd/types/ranges.hpp>
+#include <uhd/types/serial.hpp>
 #include <boost/shared_ptr.hpp>
-#include <boost/utility.hpp>
-#include <boost/function.hpp>
-#include <vector>
+#include <ad9361_device.h>
 #include <string>
 
-#include "ad9361_transaction.h"
-
-
-static const double AD9361_CLOCK_RATE_MAX = 61.44e6;
-static const double AD9361_1_CHAN_CLOCK_RATE_MAX = AD9361_CLOCK_RATE_MAX;
-static const double AD9361_2_CHAN_CLOCK_RATE_MAX = (AD9361_1_CHAN_CLOCK_RATE_MAX / 2);
-
-
-struct ad9361_ctrl_iface_type
-{
-    virtual void ad9361_transact(const unsigned char in_buff[AD9361_DISPATCH_PACKET_SIZE], unsigned char out_buff[AD9361_DISPATCH_PACKET_SIZE]) = 0;
-};
-typedef boost::shared_ptr<ad9361_ctrl_iface_type> ad9361_ctrl_iface_sptr;
-
+namespace uhd { namespace usrp {
 
-struct ad9361_ctrl_over_zc : ad9361_ctrl_iface_type
+/***********************************************************************
+ * AD9361 Control Interface
+ **********************************************************************/
+class ad9361_ctrl : public boost::noncopyable
 {
-    ad9361_ctrl_over_zc(uhd::transport::zero_copy_if::sptr xport)
-    {
-        _xport = xport;
-    }
-
-    void ad9361_transact(const unsigned char in_buff[AD9361_DISPATCH_PACKET_SIZE], unsigned char out_buff[AD9361_DISPATCH_PACKET_SIZE])
-    {
-        {
-            uhd::transport::managed_send_buffer::sptr buff = _xport->get_send_buff(10.0);
-            if (not buff or buff->size() < AD9361_DISPATCH_PACKET_SIZE) throw std::runtime_error("ad9361_ctrl_over_zc send timeout");
-            std::memcpy(buff->cast<void *>(), in_buff, AD9361_DISPATCH_PACKET_SIZE);
-            buff->commit(AD9361_DISPATCH_PACKET_SIZE);
-        }
-        {
-            uhd::transport::managed_recv_buffer::sptr buff = _xport->get_recv_buff(10.0);
-            if (not buff or buff->size() < AD9361_DISPATCH_PACKET_SIZE) throw std::runtime_error("ad9361_ctrl_over_zc recv timeout");
-            std::memcpy(out_buff, buff->cast<const void *>(), AD9361_DISPATCH_PACKET_SIZE);
-        }
-    }
-
-    uhd::transport::zero_copy_if::sptr _xport;
-};
-
-
-class ad9361_ctrl : boost::noncopyable{
 public:
     typedef boost::shared_ptr<ad9361_ctrl> sptr;
 
     //! make a new codec control object
-    static sptr make(ad9361_ctrl_iface_sptr iface);
+    static sptr make_spi(
+        ad9361_params::sptr client_settings, uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num);
 
     //! Get a list of gain names for RX or TX
     static std::vector<std::string> get_gain_names(const std::string &/*which*/)
@@ -107,7 +58,7 @@ public:
     static uhd::meta_range_t get_clock_rate_range(void)
     {
         //return uhd::meta_range_t(220e3, 61.44e6);
-        return uhd::meta_range_t(5e6, AD9361_CLOCK_RATE_MAX); //5 MHz DCM low end
+        return uhd::meta_range_t(5e6, ad9361_device_t::AD9361_MAX_CLOCK_RATE); //5 MHz DCM low end
     }
 
     //! set the filter bandwidth for the frontend
@@ -132,4 +83,6 @@ public:
     virtual void data_port_loopback(const bool on) = 0;
 };
 
+}}
+
 #endif /* INCLUDED_AD9361_CTRL_HPP */
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_client.h b/host/lib/usrp/common/ad9361_driver/ad9361_client.h
new file mode 100644
index 000000000..5e848d4c0
--- /dev/null
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_client.h
@@ -0,0 +1,73 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+
+#ifndef INCLUDED_AD9361_CLIENT_H
+#define INCLUDED_AD9361_CLIENT_H
+
+#include <boost/shared_ptr.hpp>
+
+namespace uhd { namespace usrp {
+
+/*!
+ * Frequency band settings
+ */
+typedef enum {
+    AD9361_RX_BAND0,
+    AD9361_RX_BAND1,
+    AD9361_TX_BAND0
+} frequency_band_t;
+
+/*!
+ * Clocking mode
+ */
+typedef enum {
+    AD9361_XTAL_P_CLK_PATH,
+    AD9361_XTAL_N_CLK_PATH
+} clocking_mode_t;
+
+/*!
+ * Digital interface specific
+ */
+typedef enum {
+    AD9361_DDR_FDD_LVCMOS,
+    AD9361_DDR_FDD_LVDS
+} digital_interface_mode_t;
+
+/*!
+ * Interface timing
+ */
+typedef struct {
+    boost::uint8_t rx_clk_delay;
+    boost::uint8_t rx_data_delay;
+    boost::uint8_t tx_clk_delay;
+    boost::uint8_t tx_data_delay;
+} digital_interface_delays_t;
+
+class ad9361_params {
+public:
+    typedef boost::shared_ptr<ad9361_params> sptr;
+
+    virtual ~ad9361_params() {}
+
+    virtual digital_interface_delays_t get_digital_interface_timing() = 0;
+    virtual digital_interface_mode_t get_digital_interface_mode() = 0;
+    virtual clocking_mode_t get_clocking_mode() = 0;
+    virtual double get_band_edge(frequency_band_t band) = 0;
+};
+
+class ad9361_io
+{
+public:
+    typedef boost::shared_ptr<ad9361_io> sptr;
+
+    virtual ~ad9361_io() {}
+
+    virtual boost::uint8_t peek8(boost::uint32_t reg) = 0;
+    virtual void poke8(boost::uint32_t reg, boost::uint8_t val) = 0;
+};
+
+
+}}
+
+#endif /* INCLUDED_AD9361_CLIENT_H */
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
new file mode 100644
index 000000000..c0cc285e2
--- /dev/null
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
@@ -0,0 +1,1914 @@
+//

+// Copyright 2014 Ettus Research LLC

+//

+

+#include "ad9361_filter_taps.h"

+#include "ad9361_gain_tables.h"

+#include "ad9361_synth_lut.h"

+#include "ad9361_client.h"

+#include "ad9361_device.h"

+#define _USE_MATH_DEFINES

+#include <cmath>

+#include <uhd/exception.hpp>

+#include <uhd/utils/log.hpp>

+#include <boost/cstdint.hpp>

+#include <boost/date_time/posix_time/posix_time.hpp>

+#include <boost/thread/thread.hpp>

+#include <boost/scoped_array.hpp>

+#include <boost/format.hpp>

+#include <boost/math/special_functions.hpp>

+

+////////////////////////////////////////////////////////////

+// the following macros evaluate to a compile time constant

+// macros By Tom Torfs - donated to the public domain

+

+/* turn a numeric literal into a hex constant

+(avoids problems with leading zeroes)

+8-bit constants max value 0x11111111, always fits in unsigned long

+*/

+#define HEX__(n) 0x##n##LU

+

+/* 8-bit conversion function */

+#define B8__(x) ((x&0x0000000FLU)?1:0) \

++((x&0x000000F0LU)?2:0) \

++((x&0x00000F00LU)?4:0) \

++((x&0x0000F000LU)?8:0) \

++((x&0x000F0000LU)?16:0) \

++((x&0x00F00000LU)?32:0) \

++((x&0x0F000000LU)?64:0) \

++((x&0xF0000000LU)?128:0)

+

+/* for upto 8-bit binary constants */

+#define B8(d) ((unsigned char)B8__(HEX__(d)))

+////////////////////////////////////////////////////////////

+

+

+namespace uhd { namespace usrp {

+

+/* This is a simple comparison for very large double-precision floating

+ * point numbers. It is used to prevent re-tunes for frequencies that are

+ * the same but not 'exactly' because of data precision issues. */

+// TODO: see if we can avoid the need for this function

+int freq_is_nearly_equal(double a, double b) {

+    return std::max(a,b) - std::min(a,b) < 1;

+}

+

+/***********************************************************************

+ * Filter functions

+ **********************************************************************/

+

+/* This function takes in the calculated maximum number of FIR taps, and

+ * returns a number of taps that makes AD9361 happy. */

+int get_num_taps(int max_num_taps) {

+

+    int num_taps = 0;

+    int num_taps_list[] = {16, 32, 48, 64, 80, 96, 112, 128};

+    int i;

+    for(i = 1; i < 8; i++) {

+        if(max_num_taps >= num_taps_list[i]) {

+            continue;

+        } else {

+            num_taps = num_taps_list[i - 1];

+            break;

+        }

+    } if(num_taps == 0) { num_taps = 128; }

+

+    return num_taps;

+}

+

+const double ad9361_device_t::AD9361_MAX_GAIN        = 89.75;

+const double ad9361_device_t::AD9361_MAX_CLOCK_RATE  = 61.44e6;

+

+

+/* Program either the RX or TX FIR filter.

+ *

+ * The process is the same for both filters, but the function must be told

+ * how many taps are in the filter, and given a vector of the taps

+ * themselves.  */

+

+void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, boost::uint16_t *coeffs)

+{

+    boost::uint16_t base;

+

+    /* RX and TX filters use largely identical sets of programming registers.

+     Select the appropriate bank of registers here. */

+    if (direction == RX) {

+        base = 0x0f0;

+    } else {

+        base = 0x060;

+    }

+

+    /* Encode number of filter taps for programming register */

+    boost::uint8_t reg_numtaps = (((num_taps / 16) - 1) & 0x07) << 5;

+

+    /* Turn on the filter clock. */

+    _io_iface->poke8(base + 5, reg_numtaps | 0x1a);

+    boost::this_thread::sleep(boost::posix_time::milliseconds(1));

+

+    /* Zero the unused taps just in case they have stale data */

+    int addr;

+    for (addr = num_taps; addr < 128; addr++) {

+        _io_iface->poke8(base + 0, addr);

+        _io_iface->poke8(base + 1, 0x0);

+        _io_iface->poke8(base + 2, 0x0);

+        _io_iface->poke8(base + 5, reg_numtaps | 0x1e);

+        _io_iface->poke8(base + 4, 0x00);

+        _io_iface->poke8(base + 4, 0x00);

+    }

+

+    /* Iterate through indirect programming of filter coeffs using ADI recomended procedure */

+    for (addr = 0; addr < num_taps; addr++) {

+        _io_iface->poke8(base + 0, addr);

+        _io_iface->poke8(base + 1, (coeffs[addr]) & 0xff);

+        _io_iface->poke8(base + 2, (coeffs[addr] >> 8) & 0xff);

+        _io_iface->poke8(base + 5, reg_numtaps | 0x1e);

+        _io_iface->poke8(base + 4, 0x00);

+        _io_iface->poke8(base + 4, 0x00);

+    }

+

+    /* UG-671 states (page 25) (paraphrased and clarified):

+     " After the table has been programmed, write to register BASE+5 with the write bit D2 cleared and D1 high.

+     Then, write to register BASE+5 again with D1 clear, thus ensuring that the write bit resets internally

+     before the clock stops. Wait 4 sample clock periods after setting D2 high while that data writes into the table"

+     */

+

+    _io_iface->poke8(base + 5, reg_numtaps | 0x1A);

+    if (direction == RX) {

+        _io_iface->poke8(base + 5, reg_numtaps | 0x18);

+        _io_iface->poke8(base + 6, 0x02); /* Also turn on -6dB Rx gain here, to stop filter overfow.*/

+    } else {

+        _io_iface->poke8(base + 5, reg_numtaps | 0x19); /* Also turn on -6dB Tx gain here, to stop filter overfow.*/

+    }

+}

+

+

+/* Program the RX FIR Filter. */

+void ad9361_device_t::_setup_rx_fir(size_t num_taps)

+{

+    boost::scoped_array<boost::uint16_t> coeffs(new boost::uint16_t[num_taps]);

+    for (size_t i = 0; i < num_taps; i++) {

+        switch (num_taps) {

+        case 128:

+            coeffs[i] = boost::uint16_t(hb127_coeffs[i]);

+            break;

+        case 96:

+            coeffs[i] = boost::uint16_t(hb95_coeffs[i]);

+            break;

+        case 64:

+            coeffs[i] = boost::uint16_t(hb63_coeffs[i]);

+            break;

+        case 48:

+            coeffs[i] = boost::uint16_t(hb47_coeffs[i]);

+            break;

+        default:

+            throw uhd::runtime_error("[ad9361_device_t] Unsupported number of Rx FIR taps.");

+        }

+    }

+

+    _program_fir_filter(RX, num_taps, coeffs.get());

+}

+

+/* Program the TX FIR Filter. */

+void ad9361_device_t::_setup_tx_fir(size_t num_taps)

+{

+    boost::scoped_array<boost::uint16_t> coeffs(new boost::uint16_t[num_taps]);

+    for (size_t i = 0; i < num_taps; i++) {

+        switch (num_taps) {

+        case 128:

+            coeffs[i] = boost::uint16_t(hb127_coeffs[i]);

+            break;

+        case 96:

+            coeffs[i] = boost::uint16_t(hb95_coeffs[i]);

+            break;

+        case 64:

+            coeffs[i] = boost::uint16_t(hb63_coeffs[i]);

+            break;

+        case 48:

+            coeffs[i] = boost::uint16_t(hb47_coeffs[i]);

+            break;

+        default:

+            throw uhd::runtime_error("[ad9361_device_t] Unsupported number of Tx FIR taps.");

+        }

+    }

+

+    _program_fir_filter(TX, num_taps, coeffs.get());

+}

+

+/***********************************************************************

+ * Calibration functions

+ ***********************************************************************/

+

+/* Calibrate and lock the BBPLL.

+ *

+ * This function should be called anytime the BBPLL is tuned. */

+void ad9361_device_t::_calibrate_lock_bbpll()

+{

+    _io_iface->poke8(0x03F, 0x05); // Start the BBPLL calibration

+    _io_iface->poke8(0x03F, 0x01); // Clear the 'start' bit

+

+    /* Increase BBPLL KV and phase margin. */

+    _io_iface->poke8(0x04c, 0x86);

+    _io_iface->poke8(0x04d, 0x01);

+    _io_iface->poke8(0x04d, 0x05);

+

+    /* Wait for BBPLL lock. */

+    size_t count = 0;

+    while (!(_io_iface->peek8(0x05e) & 0x80)) {

+        if (count > 1000) {

+            throw uhd::runtime_error("[ad9361_device_t] BBPLL not locked");

+            break;

+        }

+        count++;

+        boost::this_thread::sleep(boost::posix_time::milliseconds(2));

+    }

+}

+

+/* Calibrate the synthesizer charge pumps.

+ *

+ * Technically, this calibration only needs to be done once, at device

+ * initialization. */

+void ad9361_device_t::_calibrate_synth_charge_pumps()

+{

+    /* If this function ever gets called, and the ENSM isn't already in the

+     * ALERT state, then something has gone horribly wrong. */

+    if ((_io_iface->peek8(0x017) & 0x0F) != 5) {

+        throw uhd::runtime_error("[ad9361_device_t] AD9361 not in ALERT during cal");

+    }

+

+    /* Calibrate the RX synthesizer charge pump. */

+    size_t count = 0;

+    _io_iface->poke8(0x23d, 0x04);

+    while (!(_io_iface->peek8(0x244) & 0x80)) {

+        if (count > 5) {

+            throw uhd::runtime_error("[ad9361_device_t] RX charge pump cal failure");

+            break;

+        }

+        count++;

+        boost::this_thread::sleep(boost::posix_time::milliseconds(1));

+    }

+    _io_iface->poke8(0x23d, 0x00);

+

+    /* Calibrate the TX synthesizer charge pump. */

+    count = 0;

+    _io_iface->poke8(0x27d, 0x04);

+    while (!(_io_iface->peek8(0x284) & 0x80)) {

+        if (count > 5) {

+            throw uhd::runtime_error("[ad9361_device_t] TX charge pump cal failure");

+            break;

+        }

+        count++;

+        boost::this_thread::sleep(boost::posix_time::milliseconds(1));

+    }

+    _io_iface->poke8(0x27d, 0x00);

+}

+

+/* Calibrate the analog BB RX filter.

+ *

+ * Note that the filter calibration depends heavily on the baseband

+ * bandwidth, so this must be re-done after any change to the RX sample

+ * rate. */

+double ad9361_device_t::_calibrate_baseband_rx_analog_filter()

+{

+    /* For filter tuning, baseband BW is half the complex BW, and must be

+     * between 28e6 and 0.2e6. */

+    double bbbw = _baseband_bw / 2.0;

+    if (bbbw > 28e6) {

+        bbbw = 28e6;

+    } else if (bbbw < 0.20e6) {

+        bbbw = 0.20e6;

+    }

+

+    double rxtune_clk = ((1.4 * bbbw * 2 * M_PI) / M_LN2);

+    _rx_bbf_tunediv = std::min<boost::uint16_t>(511, boost::uint16_t(std::ceil(_bbpll_freq / rxtune_clk)));

+    _regs.bbftune_config = (_regs.bbftune_config & 0xFE)

+            | ((_rx_bbf_tunediv >> 8) & 0x0001);

+

+    double bbbw_mhz = bbbw / 1e6;

+    double temp = ((bbbw_mhz - std::floor(bbbw_mhz)) * 1000) / 7.8125;

+    boost::uint8_t bbbw_khz = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(temp + 0.5)));

+

+    /* Set corner frequencies and dividers. */

+    _io_iface->poke8(0x1fb, (boost::uint8_t) (bbbw_mhz));

+    _io_iface->poke8(0x1fc, bbbw_khz);

+    _io_iface->poke8(0x1f8, (_rx_bbf_tunediv & 0x00FF));

+    _io_iface->poke8(0x1f9, _regs.bbftune_config);

+

+    /* RX Mix Voltage settings - only change with apps engineer help. */

+    _io_iface->poke8(0x1d5, 0x3f);

+    _io_iface->poke8(0x1c0, 0x03);

+

+    /* Enable RX1 & RX2 filter tuners. */

+    _io_iface->poke8(0x1e2, 0x02);

+    _io_iface->poke8(0x1e3, 0x02);

+

+    /* Run the calibration! */

+    size_t count = 0;

+    _io_iface->poke8(0x016, 0x80);

+    while (_io_iface->peek8(0x016) & 0x80) {

+        if (count > 100) {

+            throw uhd::runtime_error("[ad9361_device_t] RX baseband filter cal FAILURE");

+            break;

+        }

+        count++;

+        boost::this_thread::sleep(boost::posix_time::milliseconds(1));

+    }

+

+    /* Disable RX1 & RX2 filter tuners. */

+    _io_iface->poke8(0x1e2, 0x03);

+    _io_iface->poke8(0x1e3, 0x03);

+

+    return bbbw;

+}

+

+/* Calibrate the analog BB TX filter.

+ *

+ * Note that the filter calibration depends heavily on the baseband

+ * bandwidth, so this must be re-done after any change to the TX sample

+ * rate. */

+double ad9361_device_t::_calibrate_baseband_tx_analog_filter()

+{

+    /* For filter tuning, baseband BW is half the complex BW, and must be

+     * between 28e6 and 0.2e6. */

+    double bbbw = _baseband_bw / 2.0;

+    if (bbbw > 20e6) {

+        bbbw = 20e6;

+    } else if (bbbw < 0.625e6) {

+        bbbw = 0.625e6;

+    }

+

+    double txtune_clk = ((1.6 * bbbw * 2 * M_PI) / M_LN2);

+    boost::uint16_t txbbfdiv = std::min<boost::uint16_t>(511, boost::uint16_t(std::ceil(_bbpll_freq / txtune_clk)));

+    _regs.bbftune_mode = (_regs.bbftune_mode & 0xFE)

+            | ((txbbfdiv >> 8) & 0x0001);

+

+    /* Program the divider values. */

+    _io_iface->poke8(0x0d6, (txbbfdiv & 0x00FF));

+    _io_iface->poke8(0x0d7, _regs.bbftune_mode);

+

+    /* Enable the filter tuner. */

+    _io_iface->poke8(0x0ca, 0x22);

+

+    /* Calibrate! */

+    size_t count = 0;

+    _io_iface->poke8(0x016, 0x40);

+    while (_io_iface->peek8(0x016) & 0x40) {

+        if (count > 100) {

+            throw uhd::runtime_error("[ad9361_device_t] TX baseband filter cal FAILURE");

+            break;

+        }

+

+        count++;

+        boost::this_thread::sleep(boost::posix_time::milliseconds(1));

+    }

+

+    /* Disable the filter tuner. */

+    _io_iface->poke8(0x0ca, 0x26);

+

+    return bbbw;

+}

+

+/* Calibrate the secondary TX filter.

+ *

+ * This filter also depends on the TX sample rate, so if a rate change is

+ * made, the previous calibration will no longer be valid. */

+void ad9361_device_t::_calibrate_secondary_tx_filter()

+{

+    /* For filter tuning, baseband BW is half the complex BW, and must be

+     * between 20e6 and 0.53e6. */

+    double bbbw = _baseband_bw / 2.0;

+    if (bbbw > 20e6) {

+        bbbw = 20e6;

+    } else if (bbbw < 0.53e6) {

+        bbbw = 0.53e6;

+    }

+

+    double bbbw_mhz = bbbw / 1e6;

+

+    /* Start with a resistor value of 100 Ohms. */

+    int res = 100;

+

+    /* Calculate target corner frequency. */

+    double corner_freq = 5 * bbbw_mhz * 2 * M_PI;

+

+    /* Iterate through RC values to determine correct combination. */

+    int cap = 0;

+    int i;

+    for (i = 0; i <= 3; i++) {

+        cap = static_cast<int>(std::floor(0.5 + ((1 / ((corner_freq * res) * 1e6)) * 1e12)))

+                - 12;

+

+        if (cap <= 63) {

+            break;

+        }

+

+        res = res * 2;

+    }

+    if (cap > 63) {

+        cap = 63;

+    }

+

+    boost::uint8_t reg0d0, reg0d1, reg0d2;

+

+    /* Translate baseband bandwidths to register settings. */

+    if ((bbbw_mhz * 2) <= 9) {

+        reg0d0 = 0x59;

+    } else if (((bbbw_mhz * 2) > 9) && ((bbbw_mhz * 2) <= 24)) {

+        reg0d0 = 0x56;

+    } else if ((bbbw_mhz * 2) > 24) {

+        reg0d0 = 0x57;

+    } else {

+        throw uhd::runtime_error("[ad9361_device_t] Cal2ndTxFil: INVALID_CODE_PATH bad bbbw_mhz");

+        reg0d0 = 0x00;

+    }

+

+    /* Translate resistor values to register settings. */

+    if (res == 100) {

+        reg0d1 = 0x0c;

+    } else if (res == 200) {

+        reg0d1 = 0x04;

+    } else if (res == 400) {

+        reg0d1 = 0x03;

+    } else if (res == 800) {

+        reg0d1 = 0x01;

+    } else {

+        reg0d1 = 0x0c;

+    }

+

+    reg0d2 = cap;

+

+    /* Program the above-calculated values. Sweet. */

+    _io_iface->poke8(0x0d2, reg0d2);

+    _io_iface->poke8(0x0d1, reg0d1);

+    _io_iface->poke8(0x0d0, reg0d0);

+}

+

+/* Calibrate the RX TIAs.

+ *

+ * Note that the values in the TIA register, after calibration, vary with

+ * the RX gain settings. */

+void ad9361_device_t::_calibrate_rx_TIAs()

+{

+    boost::uint8_t reg1eb = _io_iface->peek8(0x1eb) & 0x3F;

+    boost::uint8_t reg1ec = _io_iface->peek8(0x1ec) & 0x7F;

+    boost::uint8_t reg1e6 = _io_iface->peek8(0x1e6) & 0x07;

+    boost::uint8_t reg1db = 0x00;

+    boost::uint8_t reg1dc = 0x00;

+    boost::uint8_t reg1dd = 0x00;

+    boost::uint8_t reg1de = 0x00;

+    boost::uint8_t reg1df = 0x00;

+

+    /* For calibration, baseband BW is half the complex BW, and must be

+     * between 28e6 and 0.2e6. */

+    double bbbw = _baseband_bw / 2.0;

+    if (bbbw > 20e6) {

+        bbbw = 20e6;

+    } else if (bbbw < 0.20e6) {

+        bbbw = 0.20e6;

+    }

+    double ceil_bbbw_mhz = std::ceil(bbbw / 1e6);

+

+    /* Do some crazy resistor and capacitor math. */

+    int Cbbf = (reg1eb * 160) + (reg1ec * 10) + 140;

+    int R2346 = 18300 * (reg1e6 & 0x07);

+    double CTIA_fF = (Cbbf * R2346 * 0.56) / 3500;

+

+    /* Translate baseband BW to register settings. */

+    if (ceil_bbbw_mhz <= 3) {

+        reg1db = 0xe0;

+    } else if ((ceil_bbbw_mhz > 3) && (ceil_bbbw_mhz <= 10)) {

+        reg1db = 0x60;

+    } else if (ceil_bbbw_mhz > 10) {

+        reg1db = 0x20;

+    } else {

+        throw uhd::runtime_error("[ad9361_device_t] CalRxTias: INVALID_CODE_PATH bad bbbw_mhz");

+    }

+

+    if (CTIA_fF > 2920) {

+        reg1dc = 0x40;

+        reg1de = 0x40;

+        boost::uint8_t temp = (boost::uint8_t) std::min<boost::uint8_t>(127,

+                boost::uint8_t(std::floor(0.5 + ((CTIA_fF - 400.0) / 320.0))));

+        reg1dd = temp;

+        reg1df = temp;

+    } else {

+        boost::uint8_t temp = boost::uint8_t(std::floor(0.5 + ((CTIA_fF - 400.0) / 40.0)) + 0x40);

+        reg1dc = temp;

+        reg1de = temp;

+        reg1dd = 0;

+        reg1df = 0;

+    }

+

+    /* w00t. Settings calculated. Program them and roll out. */

+    _io_iface->poke8(0x1db, reg1db);

+    _io_iface->poke8(0x1dd, reg1dd);

+    _io_iface->poke8(0x1df, reg1df);

+    _io_iface->poke8(0x1dc, reg1dc);

+    _io_iface->poke8(0x1de, reg1de);

+}

+

+/* Setup the AD9361 ADC.

+ *

+ * There are 40 registers that control the ADC's operation, most of the

+ * values of which must be derived mathematically, dependent on the current

+ * setting of the BBPLL. Note that the order of calculation is critical, as

+ * some of the 40 registers depend on the values in others. */

+void ad9361_device_t::_setup_adc()

+{

+    double bbbw_mhz = (((_bbpll_freq / 1e6) / _rx_bbf_tunediv) * M_LN2) \

+                  / (1.4 * 2 * M_PI);

+

+    /* For calibration, baseband BW is half the complex BW, and must be

+     * between 28e6 and 0.2e6. */

+    if(bbbw_mhz > 28) {

+        bbbw_mhz = 28;

+    } else if (bbbw_mhz < 0.20) {

+        bbbw_mhz = 0.20;

+    }

+

+    boost::uint8_t rxbbf_c3_msb = _io_iface->peek8(0x1eb) & 0x3F;

+    boost::uint8_t rxbbf_c3_lsb = _io_iface->peek8(0x1ec) & 0x7F;

+    boost::uint8_t rxbbf_r2346 = _io_iface->peek8(0x1e6) & 0x07;

+

+    double fsadc = _adcclock_freq / 1e6;

+

+    /* Sort out the RC time constant for our baseband bandwidth... */

+    double rc_timeconst = 0.0;

+    if(bbbw_mhz < 18) {

+        rc_timeconst = (1 / ((1.4 * 2 * M_PI) \

+                            * (18300 * rxbbf_r2346)

+                            * ((160e-15 * rxbbf_c3_msb)

+                                + (10e-15 * rxbbf_c3_lsb) + 140e-15)

+                            * (bbbw_mhz * 1e6)));

+    } else {

+        rc_timeconst = (1 / ((1.4 * 2 * M_PI) \

+                            * (18300 * rxbbf_r2346)

+                            * ((160e-15 * rxbbf_c3_msb)

+                                + (10e-15 * rxbbf_c3_lsb) + 140e-15)

+                            * (bbbw_mhz * 1e6) * (1 + (0.01 * (bbbw_mhz - 18)))));

+    }

+

+    double scale_res = sqrt(1 / rc_timeconst);

+    double scale_cap = sqrt(1 / rc_timeconst);

+

+    double scale_snr = (_adcclock_freq < 80e6) ? 1.0 : 1.584893192;

+    double maxsnr = 640 / 160;

+

+    /* Calculate the values for all 40 settings registers.

+     *

+     * DO NOT TOUCH THIS UNLESS YOU KNOW EXACTLY WHAT YOU ARE DOING. kthx.*/

+    boost::uint8_t data[40];

+    data[0] = 0;    data[1] = 0; data[2] = 0; data[3] = 0x24;

+    data[4] = 0x24; data[5] = 0; data[6] = 0;

+    data[7] = std::min<boost::uint8_t>(124, boost::uint8_t(std::floor(-0.5

+                    + (80.0 * scale_snr * scale_res

+                    * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0))))));

+    double data007 = data[7];

+    data[8] = std::min<boost::uint8_t>(255, boost::uint8_t(std::floor(0.5

+                    + ((20.0 * (640.0 / fsadc) * ((data007 / 80.0))

+                    / (scale_res * scale_cap))))));

+    data[10] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(-0.5 + (77.0 * scale_res

+                    * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0))))));

+    double data010 = data[10];

+    data[9] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(0.8 * data010)));

+    data[11] = std::min<boost::uint8_t>(255, boost::uint8_t(std::floor(0.5

+                    + (20.0 * (640.0 / fsadc) * ((data010 / 77.0)

+                    / (scale_res * scale_cap))))));

+    data[12] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(-0.5

+                    + (80.0 * scale_res * std::min<double>(1.0,

+                    sqrt(maxsnr * fsadc / 640.0))))));

+    double data012 = data[12];

+    data[13] = std::min<boost::uint8_t>(255, boost::uint8_t(std::floor(-1.5

+                    + (20.0 * (640.0 / fsadc) * ((data012 / 80.0)

+                    / (scale_res * scale_cap))))));

+    data[14] = 21 * boost::uint8_t(std::floor(0.1 * 640.0 / fsadc));

+    data[15] = std::min<boost::uint8_t>(127, boost::uint8_t(1.025 * data007));

+    double data015 = data[15];

+    data[16] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor((data015

+                    * (0.98 + (0.02 * std::max<double>(1.0,

+                    (640.0 / fsadc) / maxsnr)))))));

+    data[17] = data[15];

+    data[18] = std::min<boost::uint8_t>(127, boost::uint8_t(0.975 * (data010)));

+    double data018 = data[18];

+    data[19] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor((data018

+                    * (0.98 + (0.02 * std::max<double>(1.0,

+                    (640.0 / fsadc) / maxsnr)))))));

+    data[20] = data[18];

+    data[21] = std::min<boost::uint8_t>(127, boost::uint8_t(0.975 * data012));

+    double data021 = data[21];

+    data[22] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor((data021

+                    * (0.98 + (0.02 * std::max<double>(1.0,

+                    (640.0 / fsadc) / maxsnr)))))));

+    data[23] = data[21];

+    data[24] = 0x2e;

+    data[25] = boost::uint8_t(std::floor(128.0 + std::min<double>(63.0,

+                    63.0 * (fsadc / 640.0))));

+    data[26] = boost::uint8_t(std::floor(std::min<double>(63.0, 63.0 * (fsadc / 640.0)

+                    * (0.92 + (0.08 * (640.0 / fsadc))))));

+    data[27] = boost::uint8_t(std::floor(std::min<double>(63.0,

+                    32.0 * sqrt(fsadc / 640.0))));

+    data[28] = boost::uint8_t(std::floor(128.0 + std::min<double>(63.0,

+                    63.0 * (fsadc / 640.0))));

+    data[29] = boost::uint8_t(std::floor(std::min<double>(63.0,

+                    63.0 * (fsadc / 640.0)

+                    * (0.92 + (0.08 * (640.0 / fsadc))))));

+    data[30] = boost::uint8_t(std::floor(std::min<double>(63.0,

+                    32.0 * sqrt(fsadc / 640.0))));

+    data[31] = boost::uint8_t(std::floor(128.0 + std::min<double>(63.0,

+                    63.0 * (fsadc / 640.0))));

+    data[32] = boost::uint8_t(std::floor(std::min<double>(63.0,

+                    63.0 * (fsadc / 640.0) * (0.92

+                    + (0.08 * (640.0 / fsadc))))));

+    data[33] = boost::uint8_t(std::floor(std::min<double>(63.0,

+                    63.0 * sqrt(fsadc / 640.0))));

+    data[34] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(64.0

+                    * sqrt(fsadc / 640.0))));

+    data[35] = 0x40;

+    data[36] = 0x40;

+    data[37] = 0x2c;

+    data[38] = 0x00;

+    data[39] = 0x00;

+

+    /* Program the registers! */

+    for(size_t i = 0; i < 40; i++) {

+        _io_iface->poke8(0x200+i, data[i]);

+    }

+}

+

+/* Calibrate the baseband DC offset.

+ *

+ * Note that this function is called from within the TX quadrature

+ * calibration function! */

+void ad9361_device_t::_calibrate_baseband_dc_offset()

+{

+    _io_iface->poke8(0x193, 0x3f); // Calibration settings

+    _io_iface->poke8(0x190, 0x0f); // Set tracking coefficient

+    //write_ad9361_reg(device, 0x190, /*0x0f*//*0xDF*/0x80*1 | 0x40*1 | (16+8/*+4*/)); // Set tracking coefficient: don't *4 counter, do decim /4, increased gain shift

+    _io_iface->poke8(0x194, 0x01); // More calibration settings

+

+    /* Start that calibration, baby. */

+    size_t count = 0;

+    _io_iface->poke8(0x016, 0x01);

+    while (_io_iface->peek8(0x016) & 0x01) {

+        if (count > 100) {

+            throw uhd::runtime_error("[ad9361_device_t] Baseband DC Offset Calibration Failure");

+            break;

+        }

+        count++;

+        boost::this_thread::sleep(boost::posix_time::milliseconds(5));

+    }

+}

+

+/* Calibrate the RF DC offset.

+ *

+ * Note that this function is called from within the TX quadrature

+ * calibration function. */

+void ad9361_device_t::_calibrate_rf_dc_offset()

+{

+    /* Some settings are frequency-dependent. */

+    if (_rx_freq < 4e9) {

+        _io_iface->poke8(0x186, 0x32); // RF DC Offset count

+        _io_iface->poke8(0x187, 0x24);

+        _io_iface->poke8(0x188, 0x05);

+    } else {

+        _io_iface->poke8(0x186, 0x28); // RF DC Offset count

+        _io_iface->poke8(0x187, 0x34);

+        _io_iface->poke8(0x188, 0x06);

+    }

+

+    _io_iface->poke8(0x185, 0x20); // RF DC Offset wait count

+    _io_iface->poke8(0x18b, 0x83);

+    _io_iface->poke8(0x189, 0x30);

+

+    /* Run the calibration! */

+    size_t count = 0;

+    _io_iface->poke8(0x016, 0x02);

+    while (_io_iface->peek8(0x016) & 0x02) {

+        if (count > 100) {

+            throw uhd::runtime_error("[ad9361_device_t] RF DC Offset Calibration Failure");

+            break;

+        }

+        count++;

+        boost::this_thread::sleep(boost::posix_time::milliseconds(50));

+    }

+}

+

+/* Start the RX quadrature calibration.

+ *

+ * Note that we are using AD9361's 'tracking' feature for RX quadrature

+ * calibration, so once it starts it continues to free-run during operation.

+ * It should be re-run for large frequency changes. */

+void ad9361_device_t::_calibrate_rx_quadrature()

+{

+    /* Configure RX Quadrature calibration settings. */

+    _io_iface->poke8(0x168, 0x03); // Set tone level for cal

+    _io_iface->poke8(0x16e, 0x25); // RX Gain index to use for cal

+    _io_iface->poke8(0x16a, 0x75); // Set Kexp phase

+    _io_iface->poke8(0x16b, 0x15); // Set Kexp amplitude

+    _io_iface->poke8(0x169, 0xcf); // Continuous tracking mode

+    _io_iface->poke8(0x18b, 0xad);

+}

+

+/* TX quadtrature calibration routine.

+ *

+ * The TX quadrature needs to be done twice, once for each TX chain, with

+ * only one register change in between. Thus, this function enacts the

+ * calibrations, and it is called from calibrate_tx_quadrature. */

+void ad9361_device_t::_tx_quadrature_cal_routine() {

+    /* This is a weird process, but here is how it works:

+     * 1) Read the calibrated NCO frequency bits out of 0A3.

+     * 2) Write the two bits to the RX NCO freq part of 0A0.

+     * 3) Re-read 0A3 to get bits [5:0] because maybe they changed?

+     * 4) Update only the TX NCO freq bits in 0A3.

+     * 5) Profit (I hope). */

+    boost::uint8_t reg0a3 = _io_iface->peek8(0x0a3);

+    boost::uint8_t nco_freq = (reg0a3 & 0xC0);

+    _io_iface->poke8(0x0a0, 0x15 | (nco_freq >> 1));

+    reg0a3 = _io_iface->peek8(0x0a3);

+    _io_iface->poke8(0x0a3, (reg0a3 & 0x3F) | nco_freq);

+

+    /* It is possible to reach a configuration that won't operate correctly,

+     * where the two test tones used for quadrature calibration are outside

+     * of the RX BBF, and therefore don't make it to the ADC. We will check

+     * for that scenario here. */

+    double max_cal_freq = (((_baseband_bw * _tfir_factor)

+            * ((nco_freq >> 6) + 1)) / 32) * 2;

+    double bbbw = _baseband_bw / 2.0; // bbbw represents the one-sided BW

+    if (bbbw > 28e6) {

+        bbbw = 28e6;

+    } else if (bbbw < 0.20e6) {

+        bbbw = 0.20e6;

+    }

+    if (max_cal_freq > bbbw)

+        throw uhd::runtime_error("[ad9361_device_t] max_cal_freq > bbbw");

+

+    _io_iface->poke8(0x0a1, 0x7B); // Set tracking coefficient

+    _io_iface->poke8(0x0a9, 0xff); // Cal count

+    _io_iface->poke8(0x0a2, 0x7f); // Cal Kexp

+    _io_iface->poke8(0x0a5, 0x01); // Cal magnitude threshold VVVV

+    _io_iface->poke8(0x0a6, 0x01);

+

+    /* The gain table index used for calibration must be adjusted for the

+     * mid-table to get a TIA index = 1 and LPF index = 0. */

+    if ((_rx_freq >= 1300e6) && (_rx_freq < 4000e6)) {

+        _io_iface->poke8(0x0aa, 0x22); // Cal gain table index

+    } else {

+        _io_iface->poke8(0x0aa, 0x25); // Cal gain table index

+    }

+

+    _io_iface->poke8(0x0a4, 0xf0); // Cal setting conut

+    _io_iface->poke8(0x0ae, 0x00); // Cal LPF gain index (split mode)

+

+    /* First, calibrate the baseband DC offset. */

+    _calibrate_baseband_dc_offset();

+

+    /* Second, calibrate the RF DC offset. */

+    _calibrate_rf_dc_offset();

+

+    /* Now, calibrate the TX quadrature! */

+    size_t count = 0;

+    _io_iface->poke8(0x016, 0x10);

+    while (_io_iface->peek8(0x016) & 0x10) {

+        if (count > 100) {

+            throw uhd::runtime_error("[ad9361_device_t] TX Quadrature Calibration Failure");

+            break;

+        }

+        count++;

+        boost::this_thread::sleep(boost::posix_time::milliseconds(10));

+    }

+}

+

+/* Run the TX quadrature calibration.

+ *

+ * Note that from within this function we are also triggering the baseband

+ * and RF DC calibrations. */

+void ad9361_device_t::_calibrate_tx_quadrature()

+{

+    /* Make sure we are, in fact, in the ALERT state. If not, something is

+     * terribly wrong in the driver execution flow. */

+    if ((_io_iface->peek8(0x017) & 0x0F) != 5) {

+        throw uhd::runtime_error("[ad9361_device_t] TX Quad Cal started, but not in ALERT");

+    }

+

+    /* Turn off free-running and continuous calibrations. Note that this

+     * will get turned back on at the end of the RX calibration routine. */

+    _io_iface->poke8(0x169, 0xc0);

+

+    /* This calibration must be done in a certain order, and for both TX_A

+     * and TX_B, separately. Store the original setting so that we can

+     * restore it later. */

+    boost::uint8_t orig_reg_inputsel = _regs.inputsel;

+

+    /***********************************************************************

+     * TX1/2-A Calibration

+     **********************************************************************/

+    _regs.inputsel = _regs.inputsel & 0xBF;

+    _io_iface->poke8(0x004, _regs.inputsel);

+

+    _tx_quadrature_cal_routine();

+

+    /***********************************************************************

+     * TX1/2-B Calibration

+     **********************************************************************/

+    _regs.inputsel = _regs.inputsel | 0x40;

+    _io_iface->poke8(0x004, _regs.inputsel);

+

+    _tx_quadrature_cal_routine();

+

+    /***********************************************************************

+     * fin

+     **********************************************************************/

+    _regs.inputsel = orig_reg_inputsel;

+    _io_iface->poke8(0x004, orig_reg_inputsel);

+}

+

+

+/***********************************************************************

+ * Other Misc Setup Functions

+ ***********************************************************************/

+

+/* Program the mixer gain table.

+ *

+ * Note that this table is fixed for all frequency settings. */

+void ad9361_device_t::_program_mixer_gm_subtable()

+{

+    boost::uint8_t gain[] = { 0x78, 0x74, 0x70, 0x6C, 0x68, 0x64, 0x60, 0x5C, 0x58,

+            0x54, 0x50, 0x4C, 0x48, 0x30, 0x18, 0x00 };

+    boost::uint8_t gm[] = { 0x00, 0x0D, 0x15, 0x1B, 0x21, 0x25, 0x29, 0x2C, 0x2F, 0x31,

+            0x33, 0x34, 0x35, 0x3A, 0x3D, 0x3E };

+

+    /* Start the clock. */

+    _io_iface->poke8(0x13f, 0x02);

+

+    /* Program the GM Sub-table. */

+    int i;

+    for (i = 15; i >= 0; i--) {

+        _io_iface->poke8(0x138, i);

+        _io_iface->poke8(0x139, gain[(15 - i)]);

+        _io_iface->poke8(0x13A, 0x00);

+        _io_iface->poke8(0x13B, gm[(15 - i)]);

+        _io_iface->poke8(0x13F, 0x06);

+        _io_iface->poke8(0x13C, 0x00);

+        _io_iface->poke8(0x13C, 0x00);

+    }

+

+    /* Clear write bit and stop clock. */

+    _io_iface->poke8(0x13f, 0x02);

+    _io_iface->poke8(0x13C, 0x00);

+    _io_iface->poke8(0x13C, 0x00);

+    _io_iface->poke8(0x13f, 0x00);

+}

+

+/* Program the gain table.

+ *

+ * There are three different gain tables for different frequency ranges! */

+void ad9361_device_t::_program_gain_table() {

+    /* Figure out which gain table we should be using for our current

+     * frequency band. */

+    boost::uint8_t (*gain_table)[5] = NULL;

+    boost::uint8_t new_gain_table;

+    if (_rx_freq < 1300e6) {

+        gain_table = gain_table_sub_1300mhz;

+        new_gain_table = 1;

+    } else if (_rx_freq < 4e9) {

+        gain_table = gain_table_1300mhz_to_4000mhz;

+        new_gain_table = 2;

+    } else if (_rx_freq <= 6e9) {

+        gain_table = gain_table_4000mhz_to_6000mhz;

+        new_gain_table = 3;

+    } else {

+        throw uhd::runtime_error("[ad9361_device_t] Wrong _rx_freq value");

+        new_gain_table = 1;

+    }

+

+    /* Only re-program the gain table if there has been a band change. */

+    if (_curr_gain_table == new_gain_table) {

+        return;

+    } else {

+        _curr_gain_table = new_gain_table;

+    }

+

+    /* Okay, we have to program a new gain table. Sucks, brah. Start the

+     * gain table clock. */

+    _io_iface->poke8(0x137, 0x1A);

+

+    /* IT'S PROGRAMMING TIME. */

+    boost::uint8_t index = 0;

+    for (; index < 77; index++) {

+        _io_iface->poke8(0x130, index);

+        _io_iface->poke8(0x131, gain_table[index][1]);

+        _io_iface->poke8(0x132, gain_table[index][2]);

+        _io_iface->poke8(0x133, gain_table[index][3]);

+        _io_iface->poke8(0x137, 0x1E);

+        _io_iface->poke8(0x134, 0x00);

+        _io_iface->poke8(0x134, 0x00);

+    }

+

+    /* Everything above the 77th index is zero. */

+    for (; index < 91; index++) {

+        _io_iface->poke8(0x130, index);

+        _io_iface->poke8(0x131, 0x00);

+        _io_iface->poke8(0x132, 0x00);

+        _io_iface->poke8(0x133, 0x00);

+        _io_iface->poke8(0x137, 0x1E);

+        _io_iface->poke8(0x134, 0x00);

+        _io_iface->poke8(0x134, 0x00);

+    }

+

+    /* Clear the write bit and stop the gain clock. */

+    _io_iface->poke8(0x137, 0x1A);

+    _io_iface->poke8(0x134, 0x00);

+    _io_iface->poke8(0x134, 0x00);

+    _io_iface->poke8(0x137, 0x00);

+}

+

+/* Setup gain control registers.

+ *

+ * This really only needs to be done once, at initialization. */

+void ad9361_device_t::_setup_gain_control()

+{

+    _io_iface->poke8(0x0FA, 0xE0); // Gain Control Mode Select

+    _io_iface->poke8(0x0FB, 0x08); // Table, Digital Gain, Man Gain Ctrl

+    _io_iface->poke8(0x0FC, 0x23); // Incr Step Size, ADC Overrange Size

+    _io_iface->poke8(0x0FD, 0x4C); // Max Full/LMT Gain Table Index

+    _io_iface->poke8(0x0FE, 0x44); // Decr Step Size, Peak Overload Time

+    _io_iface->poke8(0x100, 0x6F); // Max Digital Gain

+    _io_iface->poke8(0x104, 0x2F); // ADC Small Overload Threshold

+    _io_iface->poke8(0x105, 0x3A); // ADC Large Overload Threshold

+    _io_iface->poke8(0x107, 0x31); // Large LMT Overload Threshold

+    _io_iface->poke8(0x108, 0x39); // Small LMT Overload Threshold

+    _io_iface->poke8(0x109, 0x23); // Rx1 Full/LMT Gain Index

+    _io_iface->poke8(0x10A, 0x58); // Rx1 LPF Gain Index

+    _io_iface->poke8(0x10B, 0x00); // Rx1 Digital Gain Index

+    _io_iface->poke8(0x10C, 0x23); // Rx2 Full/LMT Gain Index

+    _io_iface->poke8(0x10D, 0x18); // Rx2 LPF Gain Index

+    _io_iface->poke8(0x10E, 0x00); // Rx2 Digital Gain Index

+    _io_iface->poke8(0x114, 0x30); // Low Power Threshold

+    _io_iface->poke8(0x11A, 0x27); // Initial LMT Gain Limit

+    _io_iface->poke8(0x081, 0x00); // Tx Symbol Gain Control

+}

+

+/* Setup the RX or TX synthesizers.

+ *

+ * This setup depends on a fixed look-up table, which is stored in an

+ * included header file. The table is indexed based on the passed VCO rate.

+ */

+void ad9361_device_t::_setup_synth(direction_t direction, double vcorate)

+{

+    /* The vcorates in the vco_index array represent lower boundaries for

+     * rates. Once we find a match, we use that index to look-up the rest of

+     * the register values in the LUT. */

+    int vcoindex = 0;

+    for (size_t i = 0; i < 53; i++) {

+        vcoindex = i;

+        if (vcorate > vco_index[i]) {

+            break;

+        }

+    }

+    if (vcoindex > 53)

+        throw uhd::runtime_error("[ad9361_device_t] vcoindex > 53");

+

+    /* Parse the values out of the LUT based on our calculated index... */

+    boost::uint8_t vco_output_level = synth_cal_lut[vcoindex][0];

+    boost::uint8_t vco_varactor = synth_cal_lut[vcoindex][1];

+    boost::uint8_t vco_bias_ref = synth_cal_lut[vcoindex][2];

+    boost::uint8_t vco_bias_tcf = synth_cal_lut[vcoindex][3];

+    boost::uint8_t vco_cal_offset = synth_cal_lut[vcoindex][4];

+    boost::uint8_t vco_varactor_ref = synth_cal_lut[vcoindex][5];

+    boost::uint8_t charge_pump_curr = synth_cal_lut[vcoindex][6];

+    boost::uint8_t loop_filter_c2 = synth_cal_lut[vcoindex][7];

+    boost::uint8_t loop_filter_c1 = synth_cal_lut[vcoindex][8];

+    boost::uint8_t loop_filter_r1 = synth_cal_lut[vcoindex][9];

+    boost::uint8_t loop_filter_c3 = synth_cal_lut[vcoindex][10];

+    boost::uint8_t loop_filter_r3 = synth_cal_lut[vcoindex][11];

+

+    /* ... annnd program! */

+    if (direction == RX) {

+        _io_iface->poke8(0x23a, 0x40 | vco_output_level);

+        _io_iface->poke8(0x239, 0xC0 | vco_varactor);

+        _io_iface->poke8(0x242, vco_bias_ref | (vco_bias_tcf << 3));

+        _io_iface->poke8(0x238, (vco_cal_offset << 3));

+        _io_iface->poke8(0x245, 0x00);

+        _io_iface->poke8(0x251, vco_varactor_ref);

+        _io_iface->poke8(0x250, 0x70);

+        _io_iface->poke8(0x23b, 0x80 | charge_pump_curr);

+        _io_iface->poke8(0x23e, loop_filter_c1 | (loop_filter_c2 << 4));

+        _io_iface->poke8(0x23f, loop_filter_c3 | (loop_filter_r1 << 4));

+        _io_iface->poke8(0x240, loop_filter_r3);

+    } else if (direction == TX) {

+        _io_iface->poke8(0x27a, 0x40 | vco_output_level);

+        _io_iface->poke8(0x279, 0xC0 | vco_varactor);

+        _io_iface->poke8(0x282, vco_bias_ref | (vco_bias_tcf << 3));

+        _io_iface->poke8(0x278, (vco_cal_offset << 3));

+        _io_iface->poke8(0x285, 0x00);

+        _io_iface->poke8(0x291, vco_varactor_ref);

+        _io_iface->poke8(0x290, 0x70);

+        _io_iface->poke8(0x27b, 0x80 | charge_pump_curr);

+        _io_iface->poke8(0x27e, loop_filter_c1 | (loop_filter_c2 << 4));

+        _io_iface->poke8(0x27f, loop_filter_c3 | (loop_filter_r1 << 4));

+        _io_iface->poke8(0x280, loop_filter_r3);

+    } else {

+        throw uhd::runtime_error("[ad9361_device_t] [_setup_synth] INVALID_CODE_PATH");

+    }

+}

+

+

+/* Tune the baseband VCO.

+ *

+ * This clock signal is what gets fed to the ADCs and DACs. This function is

+ * not exported outside of this file, and is invoked based on the rate

+ * fed to the public set_clock_rate function. */

+double ad9361_device_t::_tune_bbvco(const double rate)

+{

+    UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] rate=%.10f\n") % rate;

+

+    /* Let's not re-tune to the same frequency over and over... */

+    if (freq_is_nearly_equal(rate, _req_coreclk)) {

+        return _adcclock_freq;

+    }

+

+    _req_coreclk = rate;

+

+    const double fref = 40e6;

+    const int modulus = 2088960;

+    const double vcomax = 1430e6;

+    const double vcomin = 672e6;

+    double vcorate;

+    int vcodiv;

+

+    /* Iterate over VCO dividers until appropriate divider is found. */

+    int i = 1;

+    for (; i <= 6; i++) {

+        vcodiv = 1 << i;

+        vcorate = rate * vcodiv;

+

+        if (vcorate >= vcomin && vcorate <= vcomax)

+            break;

+    }

+    if (i == 7)

+        throw uhd::runtime_error("[ad9361_device_t] _tune_bbvco: wrong vcorate");

+

+    UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] vcodiv=%d vcorate=%.10f\n") % vcodiv % vcorate;

+    /* Fo = Fref * (Nint + Nfrac / mod) */

+    int nint = static_cast<int>(vcorate / fref);

+    UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] (nint)=%.10f\n") % (vcorate / fref);

+    int nfrac = static_cast<int>(boost::math::round(((vcorate / fref) - (double) nint) * (double) modulus));

+    UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] (nfrac)=%.10f\n") % (((vcorate / fref) - (double) nint) * (double) modulus);

+    UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] nint=%d nfrac=%d\n") % nint % nfrac;

+    double actual_vcorate = fref

+            * ((double) nint + ((double) nfrac / (double) modulus));

+

+    /* Scale CP current according to VCO rate */

+    const double icp_baseline = 150e-6;

+    const double freq_baseline = 1280e6;

+    double icp = icp_baseline * (actual_vcorate / freq_baseline);

+    int icp_reg = static_cast<int>(icp / 25e-6) - 1;

+

+    _io_iface->poke8(0x045, 0x00);            // REFCLK / 1 to BBPLL

+    _io_iface->poke8(0x046, icp_reg & 0x3F);  // CP current

+    _io_iface->poke8(0x048, 0xe8);            // BBPLL loop filters

+    _io_iface->poke8(0x049, 0x5b);            // BBPLL loop filters

+    _io_iface->poke8(0x04a, 0x35);            // BBPLL loop filters

+

+    _io_iface->poke8(0x04b, 0xe0);

+    _io_iface->poke8(0x04e, 0x10);            // Max accuracy

+

+    _io_iface->poke8(0x043, nfrac & 0xFF);         // Nfrac[7:0]

+    _io_iface->poke8(0x042, (nfrac >> 8) & 0xFF);  // Nfrac[15:8]

+    _io_iface->poke8(0x041, (nfrac >> 16) & 0xFF); // Nfrac[23:16]

+    _io_iface->poke8(0x044, nint);                 // Nint

+

+    _calibrate_lock_bbpll();

+

+    _regs.bbpll = (_regs.bbpll & 0xF8) | i;

+

+    _bbpll_freq = actual_vcorate;

+    _adcclock_freq = (actual_vcorate / vcodiv);

+

+    return _adcclock_freq;

+}

+

+/* This function re-programs all of the gains in the system.

+ *

+ * Because the gain values match to different gain indices based on the

+ * current operating band, this function can be called to update all gain

+ * settings to the appropriate index after a re-tune. */

+void ad9361_device_t::_reprogram_gains()

+{

+    set_gain(RX, CHAIN_1,_rx1_gain);

+    set_gain(RX, CHAIN_2,_rx2_gain);

+    set_gain(TX, CHAIN_1,_tx1_gain);

+    set_gain(TX, CHAIN_2,_tx2_gain);

+}

+

+/* This is the internal tune function, not available for a host call.

+ *

+ * Calculate the VCO settings for the requested frquency, and then either

+ * tune the RX or TX VCO. */

+double ad9361_device_t::_tune_helper(direction_t direction, const double value)

+{

+    /* The RFPLL runs from 6 GHz - 12 GHz */

+    const double fref = 80e6;

+    const int modulus = 8388593;

+    const double vcomax = 12e9;

+    const double vcomin = 6e9;

+    double vcorate;

+    int vcodiv;

+

+    /* Iterate over VCO dividers until appropriate divider is found. */

+    int i;

+    for (i = 0; i <= 6; i++) {

+        vcodiv = 2 << i;

+        vcorate = value * vcodiv;

+        if (vcorate >= vcomin && vcorate <= vcomax)

+            break;

+    }

+    if (i == 7)

+        throw uhd::runtime_error("[ad9361_device_t] RFVCO can't find valid VCO rate!");

+

+    int nint = static_cast<int>(vcorate / fref);

+    int nfrac = static_cast<int>(((vcorate / fref) - nint) * modulus);

+

+    double actual_vcorate = fref * (nint + (double) (nfrac) / modulus);

+    double actual_lo = actual_vcorate / vcodiv;

+

+    if (direction == RX) {

+

+        _req_rx_freq = value;

+

+        /* Set band-specific settings. */

+        if (value < _client_params->get_band_edge(AD9361_RX_BAND0)) {

+            _regs.inputsel = (_regs.inputsel & 0xC0) | 0x30;

+        } else if ((value

+                >= _client_params->get_band_edge(AD9361_RX_BAND0))

+                && (value

+                        < _client_params->get_band_edge(AD9361_RX_BAND1))) {

+            _regs.inputsel = (_regs.inputsel & 0xC0) | 0x0C;

+        } else if ((value

+                >= _client_params->get_band_edge(AD9361_RX_BAND1))

+                && (value <= 6e9)) {

+            _regs.inputsel = (_regs.inputsel & 0xC0) | 0x03;

+        } else {

+            throw uhd::runtime_error("[ad9361_device_t] [_tune_helper] INVALID_CODE_PATH");

+        }

+

+        _io_iface->poke8(0x004, _regs.inputsel);

+

+        /* Store vcodiv setting. */

+        _regs.vcodivs = (_regs.vcodivs & 0xF0) | (i & 0x0F);

+

+        /* Setup the synthesizer. */

+        _setup_synth(RX, actual_vcorate);

+

+        /* Tune!!!! */

+        _io_iface->poke8(0x233, nfrac & 0xFF);

+        _io_iface->poke8(0x234, (nfrac >> 8) & 0xFF);

+        _io_iface->poke8(0x235, (nfrac >> 16) & 0xFF);

+        _io_iface->poke8(0x232, (nint >> 8) & 0xFF);

+        _io_iface->poke8(0x231, nint & 0xFF);

+        _io_iface->poke8(0x005, _regs.vcodivs);

+

+        /* Lock the PLL! */

+        boost::this_thread::sleep(boost::posix_time::milliseconds(2));

+        if ((_io_iface->peek8(0x247) & 0x02) == 0) {

+            throw uhd::runtime_error("[ad9361_device_t] RX PLL NOT LOCKED");

+        }

+

+        _rx_freq = actual_lo;

+

+        return actual_lo;

+

+    } else {

+

+        _req_tx_freq = value;

+

+        /* Set band-specific settings. */

+        if (value < _client_params->get_band_edge(AD9361_TX_BAND0)) {

+            _regs.inputsel = _regs.inputsel | 0x40;

+        } else if ((value

+                >= _client_params->get_band_edge(AD9361_TX_BAND0))

+                && (value <= 6e9)) {

+            _regs.inputsel = _regs.inputsel & 0xBF;

+        } else {

+            throw uhd::runtime_error("[ad9361_device_t] [_tune_helper] INVALID_CODE_PATH");

+        }

+

+        _io_iface->poke8(0x004, _regs.inputsel);

+

+        /* Store vcodiv setting. */

+        _regs.vcodivs = (_regs.vcodivs & 0x0F) | ((i & 0x0F) << 4);

+

+        /* Setup the synthesizer. */

+        _setup_synth(TX, actual_vcorate);

+

+        /* Tune it, homey. */

+        _io_iface->poke8(0x273, nfrac & 0xFF);

+        _io_iface->poke8(0x274, (nfrac >> 8) & 0xFF);

+        _io_iface->poke8(0x275, (nfrac >> 16) & 0xFF);

+        _io_iface->poke8(0x272, (nint >> 8) & 0xFF);

+        _io_iface->poke8(0x271, nint & 0xFF);

+        _io_iface->poke8(0x005, _regs.vcodivs);

+

+        /* Lock the PLL! */

+        boost::this_thread::sleep(boost::posix_time::milliseconds(2));

+        if ((_io_iface->peek8(0x287) & 0x02) == 0) {

+            throw uhd::runtime_error("[ad9361_device_t] TX PLL NOT LOCKED");

+        }

+

+        _tx_freq = actual_lo;

+

+        return actual_lo;

+    }

+}

+

+/* Configure the various clock / sample rates in the RX and TX chains.

+ *

+ * Functionally, this function configures AD9361's RX and TX rates. For

+ * a requested TX & RX rate, it sets the interpolation & decimation filters,

+ * and tunes the VCO that feeds the ADCs and DACs.

+ */

+double ad9361_device_t::_setup_rates(const double rate)

+{

+    /* If we make it into this function, then we are tuning to a new rate.

+     * Store the new rate. */

+    _req_clock_rate = rate;

+

+    /* Set the decimation and interpolation values in the RX and TX chains.

+     * This also switches filters in / out. Note that all transmitters and

+     * receivers have to be turned on for the calibration portion of

+     * bring-up, and then they will be switched out to reflect the actual

+     * user-requested antenna selections. */

+    int divfactor = 0;

+    _tfir_factor = 0;

+    if (rate < 0.33e6) {

+        // RX1 + RX2 enabled, 3, 2, 2, 4

+        _regs.rxfilt = B8(11101111);

+

+        // TX1 + TX2 enabled, 3, 2, 2, 4

+        _regs.txfilt = B8(11101111);

+

+        divfactor = 48;

+        _tfir_factor = 2;

+    } else if (rate < 0.66e6) {

+        // RX1 + RX2 enabled, 2, 2, 2, 4

+        _regs.rxfilt = B8(11011111);

+

+        // TX1 + TX2 enabled, 2, 2, 2, 4

+        _regs.txfilt = B8(11011111);

+

+        divfactor = 32;

+        _tfir_factor = 2;

+    } else if (rate <= 20e6) {

+        // RX1 + RX2 enabled, 2, 2, 2, 2

+        _regs.rxfilt = B8(11011110);

+

+        // TX1 + TX2 enabled, 2, 2, 2, 2

+        _regs.txfilt = B8(11011110);

+

+        divfactor = 16;

+        _tfir_factor = 2;

+    } else if ((rate > 20e6) && (rate < 23e6)) {

+        // RX1 + RX2 enabled, 3, 2, 2, 2

+        _regs.rxfilt = B8(11101110);

+

+        // TX1 + TX2 enabled, 3, 1, 2, 2

+        _regs.txfilt = B8(11100110);

+

+        divfactor = 24;

+        _tfir_factor = 2;

+    } else if ((rate >= 23e6) && (rate < 41e6)) {

+        // RX1 + RX2 enabled, 2, 2, 2, 2

+        _regs.rxfilt = B8(11011110);

+

+        // TX1 + TX2 enabled, 1, 2, 2, 2

+        _regs.txfilt = B8(11001110);

+

+        divfactor = 16;

+        _tfir_factor = 2;

+    } else if ((rate >= 41e6) && (rate <= 56e6)) {

+        // RX1 + RX2 enabled, 3, 1, 2, 2

+        _regs.rxfilt = B8(11100110);

+

+        // TX1 + TX2 enabled, 3, 1, 1, 2

+        _regs.txfilt = B8(11100010);

+

+        divfactor = 12;

+        _tfir_factor = 2;

+    } else if ((rate > 56e6) && (rate <= 61.44e6)) {

+        // RX1 + RX2 enabled, 3, 1, 1, 2

+        _regs.rxfilt = B8(11100010);

+

+        // TX1 + TX2 enabled, 3, 1, 1, 1

+        _regs.txfilt = B8(11100001);

+

+        divfactor = 6;

+        _tfir_factor = 1;

+    } else {

+        // should never get in here

+        throw uhd::runtime_error("[ad9361_device_t] [_setup_rates] INVALID_CODE_PATH");

+    }

+

+    UHD_LOG << boost::format("[ad9361_device_t::_setup_rates] divfactor=%d\n") % divfactor;

+

+    /* Tune the BBPLL to get the ADC and DAC clocks. */

+    const double adcclk = _tune_bbvco(rate * divfactor);

+    double dacclk = adcclk;

+

+    /* The DAC clock must be <= 336e6, and is either the ADC clock or 1/2 the

+     * ADC clock.*/

+    if (adcclk > 336e6) {

+        /* Make the DAC clock = ADC/2, and bypass the TXFIR. */

+        _regs.bbpll = _regs.bbpll | 0x08;

+        dacclk = adcclk / 2.0;

+    } else {

+        _regs.bbpll = _regs.bbpll & 0xF7;

+    }

+

+    /* Set the dividers / interpolators in AD9361. */

+    _io_iface->poke8(0x002, _regs.txfilt);

+    _io_iface->poke8(0x003, _regs.rxfilt);

+    _io_iface->poke8(0x004, _regs.inputsel);

+    _io_iface->poke8(0x00A, _regs.bbpll);

+

+    UHD_LOG << boost::format("[ad9361_device_t::_setup_rates] adcclk=%f\n") % adcclk;

+    _baseband_bw = (adcclk / divfactor);

+

+    /*

+     The Tx & Rx FIR calculate 16 taps per clock cycle. This limits the number of available taps to the ratio of DAC_CLK/ADC_CLK

+     to the input data rate multiplied by 16. For example, if the input data rate is 25 MHz and DAC_CLK is 100 MHz,

+     then the ratio of DAC_CLK to the input data rate is 100/25 or 4. In this scenario, the total number of taps available is 64.

+

+     Also, whilst the Rx FIR filter always has memory available for 128 taps, the Tx FIR Filter can only support a maximum length of 64 taps

+     in 1x interpolation mode, and 128 taps in 2x & 4x modes.

+     */

+    const size_t max_tx_taps = std::min<size_t>(

+            std::min<size_t>((16 * (int)((dacclk / rate) + 0.5)), 128),

+            (_tfir_factor == 1) ? 64 : 128);

+    const size_t max_rx_taps = std::min<size_t>((16 * (size_t)((adcclk / rate) + 0.5)),

+            128);

+

+    const size_t num_tx_taps = get_num_taps(max_tx_taps);

+    const size_t num_rx_taps = get_num_taps(max_rx_taps);

+

+    _setup_tx_fir(num_tx_taps);

+    _setup_rx_fir(num_rx_taps);

+

+    return _baseband_bw;

+}

+

+/***********************************************************************

+ * Publicly exported functions to host calls

+ **********************************************************************/

+void ad9361_device_t::initialize()

+{

+    boost::lock_guard<boost::recursive_mutex> lock(_mutex);

+

+    /* Initialize shadow registers. */

+    _regs.vcodivs = 0x00;

+    _regs.inputsel = 0x30;

+    _regs.rxfilt = 0x00;

+    _regs.txfilt = 0x00;

+    _regs.bbpll = 0x02;

+    _regs.bbftune_config = 0x1e;

+    _regs.bbftune_mode = 0x1e;

+

+    /* Initialize private VRQ fields. */

+    _rx_freq = 0.0;

+    _tx_freq = 0.0;

+    _req_rx_freq = 0.0;

+    _req_tx_freq = 0.0;

+    _baseband_bw = 0.0;

+    _req_clock_rate = 0.0;

+    _req_coreclk = 0.0;

+    _bbpll_freq = 0.0;

+    _adcclock_freq = 0.0;

+    _rx_bbf_tunediv = 0;

+    _curr_gain_table = 0;

+    _rx1_gain = 0;

+    _rx2_gain = 0;

+    _tx1_gain = 0;

+    _tx2_gain = 0;

+

+    /* Reset the device. */

+    _io_iface->poke8(0x000, 0x01);

+    _io_iface->poke8(0x000, 0x00);

+    boost::this_thread::sleep(boost::posix_time::milliseconds(20));

+

+    /* There is not a WAT big enough for this. */

+    _io_iface->poke8(0x3df, 0x01);

+

+    _io_iface->poke8(0x2a6, 0x0e); // Enable master bias

+    _io_iface->poke8(0x2a8, 0x0e); // Set bandgap trim

+

+    /* Set RFPLL ref clock scale to REFCLK * 2 */

+    _io_iface->poke8(0x2ab, 0x07);

+    _io_iface->poke8(0x2ac, 0xff);

+

+    /* Enable clocks. */

+    switch (_client_params->get_clocking_mode()) {

+    case AD9361_XTAL_N_CLK_PATH: {

+        _io_iface->poke8(0x009, 0x17);

+    } break;

+

+    case AD9361_XTAL_P_CLK_PATH: {

+        _io_iface->poke8(0x009, 0x07);

+        _io_iface->poke8(0x292, 0x08);

+        _io_iface->poke8(0x293, 0x80);

+        _io_iface->poke8(0x294, 0x00);

+        _io_iface->poke8(0x295, 0x14);

+    } break;

+

+    default:

+        throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED");

+    }

+    boost::this_thread::sleep(boost::posix_time::milliseconds(20));

+

+    /* Tune the BBPLL, write TX and RX FIRS. */

+    _setup_rates(50e6);

+

+    /* Setup data ports (FDD dual port DDR):

+     *      FDD dual port DDR CMOS no swap.

+     *      Force TX on one port, RX on the other. */

+    switch (_client_params->get_digital_interface_mode()) {

+    case AD9361_DDR_FDD_LVCMOS: {

+        _io_iface->poke8(0x010, 0xc8);

+        _io_iface->poke8(0x011, 0x00);

+        _io_iface->poke8(0x012, 0x02);

+    } break;

+

+    case AD9361_DDR_FDD_LVDS: {

+        _io_iface->poke8(0x010, 0xcc);

+        _io_iface->poke8(0x011, 0x00);

+        _io_iface->poke8(0x012, 0x10);

+

+        //LVDS Specific

+        _io_iface->poke8(0x03C, 0x23);

+        _io_iface->poke8(0x03D, 0xFF);

+        _io_iface->poke8(0x03E, 0x0F);

+    } break;

+

+    default:

+        throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED");

+    }

+

+    /* Data delay for TX and RX data clocks */

+    digital_interface_delays_t timing =

+            _client_params->get_digital_interface_timing();

+    boost::uint8_t rx_delays = ((timing.rx_clk_delay & 0xF) << 4)

+            | (timing.rx_data_delay & 0xF);

+    boost::uint8_t tx_delays = ((timing.tx_clk_delay & 0xF) << 4)

+            | (timing.tx_data_delay & 0xF);

+    _io_iface->poke8(0x006, rx_delays);

+    _io_iface->poke8(0x007, tx_delays);

+

+    /* Setup AuxDAC */

+    _io_iface->poke8(0x018, 0x00); // AuxDAC1 Word[9:2]

+    _io_iface->poke8(0x019, 0x00); // AuxDAC2 Word[9:2]

+    _io_iface->poke8(0x01A, 0x00); // AuxDAC1 Config and Word[1:0]

+    _io_iface->poke8(0x01B, 0x00); // AuxDAC2 Config and Word[1:0]

+    _io_iface->poke8(0x022, 0x4A); // Invert Bypassed LNA

+    _io_iface->poke8(0x023, 0xFF); // AuxDAC Manaul/Auto Control

+    _io_iface->poke8(0x026, 0x00); // AuxDAC Manual Select Bit/GPO Manual Select

+    _io_iface->poke8(0x030, 0x00); // AuxDAC1 Rx Delay

+    _io_iface->poke8(0x031, 0x00); // AuxDAC1 Tx Delay

+    _io_iface->poke8(0x032, 0x00); // AuxDAC2 Rx Delay

+    _io_iface->poke8(0x033, 0x00); // AuxDAC2 Tx Delay

+

+    /* Setup AuxADC */

+    _io_iface->poke8(0x00B, 0x00); // Temp Sensor Setup (Offset)

+    _io_iface->poke8(0x00C, 0x00); // Temp Sensor Setup (Temp Window)

+    _io_iface->poke8(0x00D, 0x03); // Temp Sensor Setup (Periodic Measure)

+    _io_iface->poke8(0x00F, 0x04); // Temp Sensor Setup (Decimation)

+    _io_iface->poke8(0x01C, 0x10); // AuxADC Setup (Clock Div)

+    _io_iface->poke8(0x01D, 0x01); // AuxADC Setup (Decimation/Enable)

+

+    /* Setup control outputs. */

+    _io_iface->poke8(0x035, 0x07);

+    _io_iface->poke8(0x036, 0xFF);

+

+    /* Setup GPO */

+    _io_iface->poke8(0x03a, 0x27); //set delay register

+    _io_iface->poke8(0x020, 0x00); // GPO Auto Enable Setup in RX and TX

+    _io_iface->poke8(0x027, 0x03); // GPO Manual and GPO auto value in ALERT

+    _io_iface->poke8(0x028, 0x00); // GPO_0 RX Delay

+    _io_iface->poke8(0x029, 0x00); // GPO_1 RX Delay

+    _io_iface->poke8(0x02A, 0x00); // GPO_2 RX Delay

+    _io_iface->poke8(0x02B, 0x00); // GPO_3 RX Delay

+    _io_iface->poke8(0x02C, 0x00); // GPO_0 TX Delay

+    _io_iface->poke8(0x02D, 0x00); // GPO_1 TX Delay

+    _io_iface->poke8(0x02E, 0x00); // GPO_2 TX Delay

+    _io_iface->poke8(0x02F, 0x00); // GPO_3 TX Delay

+

+    _io_iface->poke8(0x261, 0x00); // RX LO power

+    _io_iface->poke8(0x2a1, 0x00); // TX LO power

+    _io_iface->poke8(0x248, 0x0b); // en RX VCO LDO

+    _io_iface->poke8(0x288, 0x0b); // en TX VCO LDO

+    _io_iface->poke8(0x246, 0x02); // pd RX cal Tcf

+    _io_iface->poke8(0x286, 0x02); // pd TX cal Tcf

+    _io_iface->poke8(0x249, 0x8e); // rx vco cal length

+    _io_iface->poke8(0x289, 0x8e); // rx vco cal length

+    _io_iface->poke8(0x23b, 0x80); // set RX MSB?, FIXME 0x89 magic cp

+    _io_iface->poke8(0x27b, 0x80); // "" TX //FIXME 0x88 see above

+    _io_iface->poke8(0x243, 0x0d); // set rx prescaler bias

+    _io_iface->poke8(0x283, 0x0d); // "" TX

+

+    _io_iface->poke8(0x23d, 0x00); // Clear half VCO cal clock setting

+    _io_iface->poke8(0x27d, 0x00); // Clear half VCO cal clock setting

+

+    /* The order of the following process is EXTREMELY important. If the

+     * below functions are modified at all, device initialization and

+     * calibration might be broken in the process! */

+

+    _io_iface->poke8(0x015, 0x04); // dual synth mode, synth en ctrl en

+    _io_iface->poke8(0x014, 0x05); // use SPI for TXNRX ctrl, to ALERT, TX on

+    _io_iface->poke8(0x013, 0x01); // enable ENSM

+    boost::this_thread::sleep(boost::posix_time::milliseconds(1));

+

+    _calibrate_synth_charge_pumps();

+

+    _tune_helper(RX, 800e6);

+    _tune_helper(TX, 850e6);

+

+    _program_mixer_gm_subtable();

+    _program_gain_table();

+    _setup_gain_control();

+

+    _calibrate_baseband_rx_analog_filter();

+    _calibrate_baseband_tx_analog_filter();

+    _calibrate_rx_TIAs();

+    _calibrate_secondary_tx_filter();

+

+    _setup_adc();

+

+    _calibrate_tx_quadrature();

+    _calibrate_rx_quadrature();

+

+    // cals done, set PPORT config

+    switch (_client_params->get_digital_interface_mode()) {

+    case AD9361_DDR_FDD_LVCMOS: {

+        _io_iface->poke8(0x012, 0x02);

+    } break;

+

+    case AD9361_DDR_FDD_LVDS: {

+        _io_iface->poke8(0x012, 0x10);

+    } break;

+

+    default:

+        throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED");

+    }

+

+    _io_iface->poke8(0x013, 0x01); // Set ENSM FDD bit

+    _io_iface->poke8(0x015, 0x04); // dual synth mode, synth en ctrl en

+

+    /* Default TX attentuation to 10dB on both TX1 and TX2 */

+    _io_iface->poke8(0x073, 0x00);

+    _io_iface->poke8(0x074, 0x00);

+    _io_iface->poke8(0x075, 0x00);

+    _io_iface->poke8(0x076, 0x00);

+

+    /* Setup RSSI Measurements */

+    _io_iface->poke8(0x150, 0x0E); // RSSI Measurement Duration 0, 1

+    _io_iface->poke8(0x151, 0x00); // RSSI Measurement Duration 2, 3

+    _io_iface->poke8(0x152, 0xFF); // RSSI Weighted Multiplier 0

+    _io_iface->poke8(0x153, 0x00); // RSSI Weighted Multiplier 1

+    _io_iface->poke8(0x154, 0x00); // RSSI Weighted Multiplier 2

+    _io_iface->poke8(0x155, 0x00); // RSSI Weighted Multiplier 3

+    _io_iface->poke8(0x156, 0x00); // RSSI Delay

+    _io_iface->poke8(0x157, 0x00); // RSSI Wait

+    _io_iface->poke8(0x158, 0x0D); // RSSI Mode Select

+    _io_iface->poke8(0x15C, 0x67); // Power Measurement Duration

+

+    /* Turn on the default RX & TX chains. */

+    set_active_chains(true, false, false, false);

+

+    /* Set TXers & RXers on (only works in FDD mode) */

+    _io_iface->poke8(0x014, 0x21);

+}

+

+

+/* This function sets the RX / TX rate between AD9361 and the FPGA, and

+ * thus determines the interpolation / decimation required in the FPGA to

+ * achieve the user's requested rate.

+ *

+ * This is the only clock setting function that is exposed to the outside. */

+double ad9361_device_t::set_clock_rate(const double req_rate)

+{

+    boost::lock_guard<boost::recursive_mutex> lock(_mutex);

+

+    if (req_rate > 61.44e6) {

+        throw uhd::runtime_error("[ad9361_device_t] Requested master clock rate outside range");

+    }

+

+    UHD_LOG << boost::format("[ad9361_device_t::set_clock_rate] req_rate=%.10f\n") % req_rate;

+

+    /* UHD has a habit of requesting the same rate like four times when it

+     * starts up. This prevents that, and any bugs in user code that request

+     * the same rate over and over. */

+    if (freq_is_nearly_equal(req_rate, _req_clock_rate)) {

+        return _baseband_bw;

+    }

+

+    /* We must be in the SLEEP / WAIT state to do this. If we aren't already

+     * there, transition the ENSM to State 0. */

+    boost::uint8_t current_state = _io_iface->peek8(0x017) & 0x0F;

+    switch (current_state) {

+    case 0x05:

+        /* We are in the ALERT state. */

+        _io_iface->poke8(0x014, 0x21);

+        boost::this_thread::sleep(boost::posix_time::milliseconds(5));

+        _io_iface->poke8(0x014, 0x00);

+        break;

+

+    case 0x0A:

+        /* We are in the FDD state. */

+        _io_iface->poke8(0x014, 0x00);

+        break;

+

+    default:

+        throw uhd::runtime_error("[ad9361_device_t] [set_clock_rate:1] AD9361 in unknown state");

+        break;

+    };

+

+    /* Store the current chain / antenna selections so that we can restore

+     * them at the end of this routine; all chains will be enabled from

+     * within setup_rates for calibration purposes. */

+    boost::uint8_t orig_tx_chains = _regs.txfilt & 0xC0;

+    boost::uint8_t orig_rx_chains = _regs.rxfilt & 0xC0;

+

+    /* Call into the clock configuration / settings function. This is where

+     * all the hard work gets done. */

+    double rate = _setup_rates(req_rate);

+

+    UHD_LOG << boost::format("[ad9361_device_t::set_clock_rate] rate=%.10f\n") % rate;

+

+    /* Transition to the ALERT state and calibrate everything. */

+    _io_iface->poke8(0x015, 0x04); //dual synth mode, synth en ctrl en

+    _io_iface->poke8(0x014, 0x05); //use SPI for TXNRX ctrl, to ALERT, TX on

+    _io_iface->poke8(0x013, 0x01); //enable ENSM

+    boost::this_thread::sleep(boost::posix_time::milliseconds(1));

+

+    _calibrate_synth_charge_pumps();

+

+    _tune_helper(RX, _rx_freq);

+    _tune_helper(TX, _tx_freq);

+

+    _program_mixer_gm_subtable();

+    _program_gain_table();

+    _setup_gain_control();

+    _reprogram_gains();

+

+    _calibrate_baseband_rx_analog_filter();

+    _calibrate_baseband_tx_analog_filter();

+    _calibrate_rx_TIAs();

+    _calibrate_secondary_tx_filter();

+

+    _setup_adc();

+

+    _calibrate_tx_quadrature();

+    _calibrate_rx_quadrature();

+

+    // cals done, set PPORT config

+    switch (_client_params->get_digital_interface_mode()) {

+        case AD9361_DDR_FDD_LVCMOS: {

+            _io_iface->poke8(0x012, 0x02);

+        }break;

+

+        case AD9361_DDR_FDD_LVDS: {

+            _io_iface->poke8(0x012, 0x10);

+        }break;

+

+        default:

+        throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED");

+    }

+    _io_iface->poke8(0x013, 0x01); // Set ENSM FDD bit

+    _io_iface->poke8(0x015, 0x04); // dual synth mode, synth en ctrl en

+

+    /* End the function in the same state as the entry state. */

+    switch (current_state) {

+    case 0x05:

+        /* We are already in ALERT. */

+        break;

+

+    case 0x0A:

+        /* Transition back to FDD, and restore the original antenna

+         * / chain selections. */

+        _regs.txfilt = (_regs.txfilt & 0x3F) | orig_tx_chains;

+        _regs.rxfilt = (_regs.rxfilt & 0x3F) | orig_rx_chains;

+

+        _io_iface->poke8(0x002, _regs.txfilt);

+        _io_iface->poke8(0x003, _regs.rxfilt);

+        _io_iface->poke8(0x014, 0x21);

+        break;

+

+    default:

+        throw uhd::runtime_error("[ad9361_device_t] [set_clock_rate:2] AD9361 in unknown state");

+        break;

+    };

+

+    return rate;

+}

+

+

+/* Set which of the four TX / RX chains provided by AD9361 are active.

+ *

+ * AD9361 provides two sets of chains, Side A and Side B. Each side

+ * provides one TX antenna, and one RX antenna. The B200 maintains the USRP

+ * standard of providing one antenna connection that is both TX & RX, and

+ * one that is RX-only - for each chain. Thus, the possible antenna and

+ * chain selections are:

+ *

+ *  B200 Antenna    AD9361 Side       AD9361 Chain

+ *  -------------------------------------------------------------------

+ *  TX / RX1        Side A              TX1 (when switched to TX)

+ *  TX / RX1        Side A              RX1 (when switched to RX)

+ *  RX1             Side A              RX1

+ *

+ *  TX / RX2        Side B              TX2 (when switched to TX)

+ *  TX / RX2        Side B              RX2 (when switched to RX)

+ *  RX2             Side B              RX2

+ */

+void ad9361_device_t::set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2)

+{

+    boost::lock_guard<boost::recursive_mutex> lock(_mutex);

+

+    /* Clear out the current active chain settings. */

+    _regs.txfilt = _regs.txfilt & 0x3F;

+    _regs.rxfilt = _regs.rxfilt & 0x3F;

+

+    /* Turn on the different chains based on the passed parameters. */

+    if (tx1) {

+        _regs.txfilt = _regs.txfilt | 0x40;

+    }

+    if (tx2) {

+        _regs.txfilt = _regs.txfilt | 0x80;

+    }

+    if (rx1) {

+        _regs.rxfilt = _regs.rxfilt | 0x40;

+    }

+    if (rx2) {

+        _regs.rxfilt = _regs.rxfilt | 0x80;

+    }

+

+    /* Check for FDD state */

+    boost::uint8_t set_back_to_fdd = 0;

+    boost::uint8_t ensm_state = _io_iface->peek8(0x017) & 0x0F;

+    if (ensm_state == 0xA)   // FDD

+            {

+        /* Put into ALERT state (via the FDD flush state). */

+        _io_iface->poke8(0x014, 0x01);

+        set_back_to_fdd = 1;

+    }

+

+    /* Wait for FDD flush state to complete (if necessary) */

+    while (ensm_state == 0xA || ensm_state == 0xB)

+        ensm_state = _io_iface->peek8(0x017) & 0x0F;

+

+    /* Turn on / off the chains. */

+    _io_iface->poke8(0x002, _regs.txfilt);

+    _io_iface->poke8(0x003, _regs.rxfilt);

+

+    /* Put back into FDD state if necessary */

+    if (set_back_to_fdd)

+        _io_iface->poke8(0x014, 0x21);

+}

+

+/* Tune the RX or TX frequency.

+ *

+ * This is the publicly-accessible tune function. It makes sure the tune

+ * isn't a redundant request, and if not, passes it on to the class's

+ * internal tune function.

+ *

+ * After tuning, it runs any appropriate calibrations. */

+double ad9361_device_t::tune(direction_t direction, const double value)

+{

+    boost::lock_guard<boost::recursive_mutex> lock(_mutex);

+

+    if (direction == RX) {

+        if (freq_is_nearly_equal(value, _req_rx_freq)) {

+            return _rx_freq;

+        }

+

+    } else if (direction == TX) {

+        if (freq_is_nearly_equal(value, _req_tx_freq)) {

+            return _tx_freq;

+        }

+

+    } else {

+        throw uhd::runtime_error("[ad9361_device_t] [tune] INVALID_CODE_PATH");

+    }

+

+    /* If we aren't already in the ALERT state, we will need to return to

+     * the FDD state after tuning. */

+    int not_in_alert = 0;

+    if ((_io_iface->peek8(0x017) & 0x0F) != 5) {

+        /* Force the device into the ALERT state. */

+        not_in_alert = 1;

+        _io_iface->poke8(0x014, 0x01);

+    }

+

+    /* Tune the RF VCO! */

+    double tune_freq = _tune_helper(direction, value);

+

+    /* Run any necessary calibrations / setups */

+    if (direction == RX) {

+        _program_gain_table();

+    }

+

+    /* Update the gain settings. */

+    _reprogram_gains();

+

+    /* Run the calibration algorithms. */

+    _calibrate_tx_quadrature();

+    _calibrate_rx_quadrature();

+

+    /* If we were in the FDD state, return it now. */

+    if (not_in_alert) {

+        _io_iface->poke8(0x014, 0x21);

+    }

+

+    return tune_freq;

+}

+

+/* Set the gain of RX1, RX2, TX1, or TX2.

+ *

+ * Note that the 'value' passed to this function is the actual gain value,

+ * _not_ the gain index. This is the opposite of the eval software's GUI!

+ * Also note that the RX chains are done in terms of gain, and the TX chains

+ * are done in terms of attenuation. */

+double ad9361_device_t::set_gain(direction_t direction, chain_t chain, const double value)

+{

+    boost::lock_guard<boost::recursive_mutex> lock(_mutex);

+

+    if (direction == RX) {

+        /* Indexing the gain tables requires an offset from the requested

+         * amount of total gain in dB:

+         *      < 1300MHz: dB + 5

+         *      >= 1300MHz and < 4000MHz: dB + 3

+         *      >= 4000MHz and <= 6000MHz: dB + 14

+         */

+        int gain_offset = 0;

+        if (_rx_freq < 1300e6) {

+            gain_offset = 5;

+        } else if (_rx_freq < 4000e6) {

+            gain_offset = 3;

+        } else {

+            gain_offset = 14;

+        }

+

+        int gain_index = static_cast<int>(value + gain_offset);

+

+        /* Clip the gain values to the proper min/max gain values. */

+        if (gain_index > 76)

+            gain_index = 76;

+        if (gain_index < 0)

+            gain_index = 0;

+

+        if (chain == CHAIN_1) {

+            _rx1_gain = boost::uint32_t(value);

+            _io_iface->poke8(0x109, gain_index);

+        } else {

+            _rx2_gain = boost::uint32_t(value);

+            _io_iface->poke8(0x10c, gain_index);

+        }

+

+        return gain_index - gain_offset;

+    } else {

+        /* Setting the below bits causes a change in the TX attenuation word

+         * to immediately take effect. */

+        _io_iface->poke8(0x077, 0x40);

+        _io_iface->poke8(0x07c, 0x40);

+

+        /* Each gain step is -0.25dB. Calculate the attenuation necessary

+         * for the requested gain, convert it into gain steps, then write

+         * the attenuation word. Max gain (so zero attenuation) is 89.75. */

+        double atten = AD9361_MAX_GAIN - value;

+        boost::uint32_t attenreg = boost::uint32_t(atten * 4);

+        if (chain == CHAIN_1) {

+            _tx1_gain = boost::uint32_t(value);

+            _io_iface->poke8(0x073, attenreg & 0xFF);

+            _io_iface->poke8(0x074, (attenreg >> 8) & 0x01);

+        } else {

+            _tx2_gain = boost::uint32_t(value);

+            _io_iface->poke8(0x075, attenreg & 0xFF);

+            _io_iface->poke8(0x076, (attenreg >> 8) & 0x01);

+        }

+        return AD9361_MAX_GAIN - ((double) (attenreg) / 4);

+    }

+}

+

+void ad9361_device_t::output_test_tone()

+{

+    boost::lock_guard<boost::recursive_mutex> lock(_mutex);

+    /* Output a 480 kHz tone at 800 MHz */

+    _io_iface->poke8(0x3F4, 0x0B);

+    _io_iface->poke8(0x3FC, 0xFF);

+    _io_iface->poke8(0x3FD, 0xFF);

+    _io_iface->poke8(0x3FE, 0x3F);

+}

+

+void ad9361_device_t::data_port_loopback(const bool loopback_enabled)

+{

+    boost::lock_guard<boost::recursive_mutex> lock(_mutex);

+    _io_iface->poke8(0x3F5, (loopback_enabled ? 0x01 : 0x00));

+}

+

+}}

diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
new file mode 100644
index 000000000..5770f332a
--- /dev/null
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
@@ -0,0 +1,125 @@
+//

+// Copyright 2014 Ettus Research LLC

+//

+

+#ifndef INCLUDED_AD9361_DEVICE_H

+#define INCLUDED_AD9361_DEVICE_H

+

+#include <ad9361_client.h>

+#include <boost/noncopyable.hpp>

+#include <boost/thread/recursive_mutex.hpp>

+

+namespace uhd { namespace usrp {

+

+class ad9361_device_t : public boost::noncopyable

+{

+public:

+    enum direction_t { RX, TX };

+    enum chain_t { CHAIN_1, CHAIN_2 };

+

+    ad9361_device_t(ad9361_params::sptr client, ad9361_io::sptr io_iface) :

+        _client_params(client), _io_iface(io_iface) {}

+

+    /* Initialize the AD9361 codec. */

+    void initialize();

+

+    /* This function sets the RX / TX rate between AD9361 and the FPGA, and

+     * thus determines the interpolation / decimation required in the FPGA to

+     * achieve the user's requested rate.

+     */

+    double set_clock_rate(const double req_rate);

+

+    /* Set which of the four TX / RX chains provided by AD9361 are active.

+     *

+     * AD9361 provides two sets of chains, Side A and Side B. Each side

+     * provides one TX antenna, and one RX antenna. The B200 maintains the USRP

+     * standard of providing one antenna connection that is both TX & RX, and

+     * one that is RX-only - for each chain. Thus, the possible antenna and

+     * chain selections are:

+     *

+     */

+    void set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2);

+

+    /* Tune the RX or TX frequency.

+     *

+     * This is the publicly-accessible tune function. It makes sure the tune

+     * isn't a redundant request, and if not, passes it on to the class's

+     * internal tune function.

+     *

+     * After tuning, it runs any appropriate calibrations. */

+    double tune(direction_t direction, const double value);

+

+    /* Set the gain of RX1, RX2, TX1, or TX2.

+     *

+     * Note that the 'value' passed to this function is the actual gain value,

+     * _not_ the gain index. This is the opposite of the eval software's GUI!

+     * Also note that the RX chains are done in terms of gain, and the TX chains

+     * are done in terms of attenuation. */

+    double set_gain(direction_t direction, chain_t chain, const double value);

+

+    /* Make AD9361 output its test tone. */

+    void output_test_tone();

+

+    /* Turn on/off AD9361's TX port --> RX port loopback. */

+    void data_port_loopback(const bool loopback_enabled);

+

+    //Constants

+    static const double AD9361_MAX_GAIN;

+    static const double AD9361_MAX_CLOCK_RATE;

+

+private:    //Methods

+    void _program_fir_filter(direction_t direction, int num_taps, boost::uint16_t *coeffs);

+    void _setup_tx_fir(size_t num_taps);

+    void _setup_rx_fir(size_t num_taps);

+    void _calibrate_lock_bbpll();

+    void _calibrate_synth_charge_pumps();

+    double _calibrate_baseband_rx_analog_filter();

+    double _calibrate_baseband_tx_analog_filter();

+    void _calibrate_secondary_tx_filter();

+    void _calibrate_rx_TIAs();

+    void _setup_adc();

+    void _calibrate_baseband_dc_offset();

+    void _calibrate_rf_dc_offset();

+    void _calibrate_rx_quadrature();

+    void _tx_quadrature_cal_routine();

+    void _calibrate_tx_quadrature();

+    void _program_mixer_gm_subtable();

+    void _program_gain_table();

+    void _setup_gain_control();

+    void _setup_synth(direction_t direction, double vcorate);

+    double _tune_bbvco(const double rate);

+    void _reprogram_gains();

+    double _tune_helper(direction_t direction, const double value);

+    double _setup_rates(const double rate);

+

+private:    //Members

+    typedef struct {

+        boost::uint8_t vcodivs;

+        boost::uint8_t inputsel;

+        boost::uint8_t rxfilt;

+        boost::uint8_t txfilt;

+        boost::uint8_t bbpll;

+        boost::uint8_t bbftune_config;

+        boost::uint8_t bbftune_mode;

+    } chip_regs_t;

+

+    //Interfaces

+    ad9361_params::sptr _client_params;

+    ad9361_io::sptr     _io_iface;

+    //Intermediate state

+    double              _rx_freq, _tx_freq, _req_rx_freq, _req_tx_freq;

+    double              _baseband_bw, _bbpll_freq, _adcclock_freq;

+    double              _req_clock_rate, _req_coreclk;

+    boost::uint16_t     _rx_bbf_tunediv;

+    boost::uint8_t      _curr_gain_table;

+    boost::uint32_t     _rx1_gain, _rx2_gain, _tx1_gain, _tx2_gain;

+    boost::int32_t      _tfir_factor;

+    //Register soft-copies

+    chip_regs_t         _regs;

+    //Synchronization

+    boost::recursive_mutex  _mutex;

+};

+

+}}  //namespace

+

+#endif /* INCLUDED_AD9361_DEVICE_H */

diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h b/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h
new file mode 100644
index 000000000..4059ad7ee
--- /dev/null
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h
@@ -0,0 +1,73 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+
+#ifndef INCLUDED_AD9361_FILTER_TAPS_HPP
+#define INCLUDED_AD9361_FILTER_TAPS_HPP
+
+#include <boost/cstdint.hpp>
+
+/* A default 128-tap filter that can be used for generic circumstances. */
+/* static uint16_t default_128tap_coeffs[] = {
+    0x0001,0xfff1,0xffcf,0xffc0,0xffe8,0x0020,0x001a,0xffe3,
+    0xffe1,0x001f,0x0028,0xffdf,0xffcc,0x0024,0x0043,0xffdb,
+    0xffac,0x0026,0x0068,0xffdb,0xff80,0x0022,0x009a,0xffe2,
+    0xff47,0x0017,0x00db,0xfff3,0xfeff,0xffff,0x012b,0x0013,
+    0xfea5,0xffd7,0x0190,0x0046,0xfe35,0xff97,0x020e,0x0095,
+    0xfda7,0xff36,0x02ae,0x010d,0xfcf0,0xfea1,0x0383,0x01c6,
+    0xfbf3,0xfdb6,0x04b7,0x02f8,0xfa6d,0xfc1a,0x06be,0x0541,
+    0xf787,0xf898,0x0b60,0x0b6d,0xee88,0xea40,0x2786,0x7209
+};
+*/
+
+/* The below pair of filters is from ADI and "optimized for a 10MHz LTE application". */
+/*
+static uint16_t lte10mhz_rx_coeffs[] = {
+    0xffe2,0x0042,0x0024,0x0095,0x0056,0x004d,0xffcf,0xffb7,
+    0xffb1,0x0019,0x0059,0x006a,0x0004,0xff9d,0xff72,0xffd4,
+    0x0063,0x00b7,0x0062,0xffac,0xff21,0xff59,0x0032,0x0101,
+    0x00f8,0x0008,0xfeea,0xfeac,0xffa3,0x0117,0x01b5,0x00d0,
+    0xff05,0xfdea,0xfe9e,0x00ba,0x026f,0x0215,0xffb5,0xfd4a,
+    0xfd18,0xffa0,0x02de,0x03dc,0x0155,0xfd2a,0xfb0d,0xfd54,
+    0x0287,0x062f,0x048a,0xfe37,0xf862,0xf8c1,0x004d,0x0963,
+    0x0b88,0x02a4,0xf3e7,0xebdd,0xf5f8,0x1366,0x3830,0x518b
+};
+
+static uint16_t lte10mhz_tx_coeffs[] = {
+    0xfffb,0x0000,0x0004,0x0017,0x0024,0x0028,0x0013,0xfff3,
+    0xffdc,0xffe5,0x000b,0x0030,0x002e,0xfffe,0xffc4,0xffb8,
+    0xfff0,0x0045,0x0068,0x002b,0xffb6,0xff72,0xffad,0x0047,
+    0x00b8,0x0088,0xffc8,0xff1c,0xff33,0x001a,0x0110,0x0124,
+    0x0019,0xfec8,0xfe74,0xff9a,0x0156,0x0208,0x00d3,0xfe9b,
+    0xfd68,0xfe96,0x015d,0x033f,0x0236,0xfecd,0xfc00,0xfcb5,
+    0x00d7,0x04e5,0x04cc,0xffd5,0xf9fe,0xf8fb,0xfef2,0x078c,
+    0x0aae,0x036d,0xf5c0,0xed89,0xf685,0x12af,0x36a4,0x4faa
+};
+*/
+
+
+/* 127 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,32)) (center tap tweaked to 32767) */
+static boost::int16_t hb127_coeffs[] = {
+  -0,0,1,-0,-2,0,3,-0,-5,0,8,-0,-11,0,17,-0,-24,0,33,-0,-45,0,61,-0,-80,0,104,-0,-134,0,169,-0,
+  -213,0,264,-0,-327,0,401,-0,-489,0,595,-0,-724,0,880,-0,-1075,0,1323,-0,-1652,0,2114,-0,-2819,0,4056,-0,-6883,0,20837,32767,
+  20837,0,-6883,-0,4056,0,-2819,-0,2114,0,-1652,-0,1323,0,-1075,-0,880,0,-724,-0,595,0,-489,-0,401,0,-327,-0,264,0,-213,-0,
+  169,0,-134,-0,104,0,-80,-0,61,0,-45,-0,33,0,-24,-0,17,0,-11,-0,8,0,-5,-0,3,0,-2,-0,1,0,-0, 0 };
+
+/* 95 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,24)) (center tap tweaked to 32767) */
+static boost::int16_t hb95_coeffs[] = {
+  -4,0,8,-0,-14,0,23,-0,-36,0,52,-0,-75,0,104,-0,-140,0,186,-0,-243,0,314,-0,-400,0,505,-0,-634,0,793,-0,
+  -993,0,1247,-0,-1585,0,2056,-0,-2773,0,4022,-0,-6862,0,20830,32767,20830,0,-6862,-0,4022,0,-2773,-0,2056,0,-1585,-0,1247,0,-993,-0,
+  793,0,-634,-0,505,0,-400,-0,314,0,-243,-0,186,0,-140,-0,104,0,-75,-0,52,0,-36,-0,23,0,-14,-0,8,0,-4,0};
+
+/* 63 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,16)) (center tap tweaked to 32767) */
+static boost::int16_t hb63_coeffs[] = {
+  -58,0,83,-0,-127,0,185,-0,-262,0,361,-0,-488,0,648,-0,-853,0,1117,-0,-1466,0,1954,-0,-2689,0,3960,-0,-6825,0,20818,32767,
+  20818,0,-6825,-0,3960,0,-2689,-0,1954,0,-1466,-0,1117,0,-853,-0,648,0,-488,-0,361,0,-262,-0,185,0,-127,-0,83,0,-58,0};
+
+/* 47 tap Halfband designed with: round(2^16 * halfgen4(0.85/4,12)) (center tap tweaked to 32767) */
+static boost::int16_t hb47_coeffs[] = {
+  -50,0,98,-0,-181,0,307,-0,-489,0,747,-0,-1109,0,1628,-0,-2413,0,3750,-0,-6693,0,20773,32767,20773,0,-6693,-0,3750,0,-2413,-0,
+  1628,0,-1109,-0,747,0,-489,-0,307,0,-181,-0,98,0,-50,0};
+
+
+#endif // INCLUDED_AD9361_FILTER_TAPS_HPP
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h b/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h
new file mode 100644
index 000000000..786029d6e
--- /dev/null
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h
@@ -0,0 +1,97 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+
+#ifndef INCLUDED_AD9361_GAIN_TABLES_HPP
+#define INCLUDED_AD9361_GAIN_TABLES_HPP
+
+#include <boost/cstdint.hpp>
+
+boost::uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1},
+    {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0},
+    {4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0},
+    {7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0},
+    {10,0x01,0x05,0x00,0}, {11,0x01,0x06,0x00,0}, {12,0x01,0x07,0x00,0},
+    {13,0x01,0x08,0x00,0}, {14,0x01,0x09,0x00,0}, {15,0x01,0x0A,0x00,0},
+    {16,0x01,0x0B,0x00,0}, {17,0x01,0x0C,0x00,0}, {18,0x01,0x0D,0x00,0},
+    {19,0x01,0x0E,0x00,0}, {20,0x02,0x09,0x20,1}, {21,0x02,0x0A,0x00,0},
+    {22,0x02,0x0B,0x00,0}, {23,0x02,0x0C,0x00,0}, {24,0x02,0x0D,0x00,0},
+    {25,0x02,0x0E,0x00,0}, {26,0x02,0x0F,0x00,0}, {27,0x02,0x10,0x00,0},
+    {28,0x02,0x2B,0x20,1}, {29,0x02,0x2C,0x00,0}, {30,0x04,0x27,0x20,1},
+    {31,0x04,0x28,0x00,0}, {32,0x04,0x29,0x00,0}, {33,0x04,0x2A,0x00,0},
+    {34,0x04,0x2B,0x00,1}, {35,0x24,0x21,0x20,0}, {36,0x24,0x22,0x00,1},
+    {37,0x44,0x20,0x20,0}, {38,0x44,0x21,0x00,0}, {39,0x44,0x22,0x00,0},
+    {40,0x44,0x23,0x00,0}, {41,0x44,0x24,0x00,0}, {42,0x44,0x25,0x00,0},
+    {43,0x44,0x26,0x00,0}, {44,0x44,0x27,0x00,0}, {45,0x44,0x28,0x00,0},
+    {46,0x44,0x29,0x00,0}, {47,0x44,0x2A,0x00,0}, {48,0x44,0x2B,0x00,0},
+    {49,0x44,0x2C,0x00,0}, {50,0x44,0x2D,0x00,0}, {51,0x44,0x2E,0x00,0},
+    {52,0x44,0x2F,0x00,0}, {53,0x44,0x30,0x00,0}, {54,0x44,0x31,0x00,0},
+    {55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
+    {58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
+    {61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
+    {64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
+    {67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
+    {70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
+    {73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
+    {76,0x6F,0x38,0x20,1}};
+
+
+boost::uint8_t gain_table_1300mhz_to_4000mhz[77][5] = {   {0,0x00,0x00,0x20,1},
+    {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0},
+    {4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0},
+    {7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0},
+    {10,0x01,0x05,0x00,0}, {11,0x01,0x06,0x00,0}, {12,0x01,0x07,0x00,0},
+    {13,0x01,0x08,0x00,0}, {14,0x01,0x09,0x00,0}, {15,0x01,0x0A,0x00,0},
+    {16,0x01,0x0B,0x00,0}, {17,0x01,0x0C,0x00,0}, {18,0x01,0x0D,0x00,0},
+    {19,0x01,0x0E,0x00,0}, {20,0x02,0x09,0x20,1}, {21,0x02,0x0A,0x00,0},
+    {22,0x02,0x0B,0x00,0}, {23,0x02,0x0C,0x00,0}, {24,0x02,0x0D,0x00,0},
+    {25,0x02,0x0E,0x00,0}, {26,0x02,0x0F,0x00,0}, {27,0x02,0x10,0x00,0},
+    {28,0x02,0x2B,0x20,1}, {29,0x02,0x2C,0x00,0}, {30,0x04,0x28,0x20,1},
+    {31,0x04,0x29,0x00,0}, {32,0x04,0x2A,0x00,0}, {33,0x04,0x2B,0x00,0},
+    {34,0x24,0x20,0x20,0}, {35,0x24,0x21,0x00,1}, {36,0x44,0x20,0x20,0},
+    {37,0x44,0x21,0x00,1}, {38,0x44,0x22,0x00,0}, {39,0x44,0x23,0x00,0},
+    {40,0x44,0x24,0x00,0}, {41,0x44,0x25,0x00,0}, {42,0x44,0x26,0x00,0},
+    {43,0x44,0x27,0x00,0}, {44,0x44,0x28,0x00,0}, {45,0x44,0x29,0x00,0},
+    {46,0x44,0x2A,0x00,0}, {47,0x44,0x2B,0x00,0}, {48,0x44,0x2C,0x00,0},
+    {49,0x44,0x2D,0x00,0}, {50,0x44,0x2E,0x00,0}, {51,0x44,0x2F,0x00,0},
+    {52,0x44,0x30,0x00,0}, {53,0x44,0x31,0x00,0}, {54,0x44,0x32,0x00,0},
+    {55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
+    {58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
+    {61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
+    {64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
+    {67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
+    {70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
+    {73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
+    {76,0x6F,0x38,0x20,1}};
+
+
+boost::uint8_t gain_table_4000mhz_to_6000mhz[77][5] = { {0,0x00,0x00,0x20,1},
+    {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x00,0x00,0},
+    {4,0x00,0x00,0x00,0}, {5,0x00,0x01,0x00,0}, {6,0x00,0x02,0x00,0},
+    {7,0x00,0x03,0x00,0}, {8,0x01,0x01,0x20,1}, {9,0x01,0x02,0x00,0},
+    {10,0x01,0x03,0x00,0}, {11,0x01,0x04,0x20,1}, {12,0x01,0x05,0x00,0},
+    {13,0x01,0x06,0x00,0}, {14,0x01,0x07,0x00,0}, {15,0x01,0x08,0x00,0},
+    {16,0x01,0x09,0x00,0}, {17,0x01,0x0A,0x00,0}, {18,0x01,0x0B,0x00,0},
+    {19,0x01,0x0C,0x00,0}, {20,0x02,0x08,0x20,1}, {21,0x02,0x09,0x00,0},
+    {22,0x02,0x0A,0x00,0}, {23,0x02,0x0B,0x20,1}, {24,0x02,0x0C,0x00,0},
+    {25,0x02,0x0D,0x00,0}, {26,0x02,0x0E,0x00,0}, {27,0x02,0x0F,0x00,0},
+    {28,0x02,0x2A,0x20,1}, {29,0x02,0x2B,0x00,0}, {30,0x04,0x27,0x20,1},
+    {31,0x04,0x28,0x00,0}, {32,0x04,0x29,0x00,0}, {33,0x04,0x2A,0x00,0},
+    {34,0x04,0x2B,0x00,0}, {35,0x04,0x2C,0x00,0}, {36,0x04,0x2D,0x00,0},
+    {37,0x24,0x20,0x20,1}, {38,0x24,0x21,0x00,0}, {39,0x24,0x22,0x00,0},
+    {40,0x44,0x20,0x20,1}, {41,0x44,0x21,0x00,0}, {42,0x44,0x22,0x00,0},
+    {43,0x44,0x23,0x00,0}, {44,0x44,0x24,0x00,0}, {45,0x44,0x25,0x00,0},
+    {46,0x44,0x26,0x00,0}, {47,0x44,0x27,0x00,0}, {48,0x44,0x28,0x00,0},
+    {49,0x44,0x29,0x00,0}, {50,0x44,0x2A,0x00,0}, {51,0x44,0x2B,0x00,0},
+    {52,0x44,0x2C,0x00,0}, {53,0x44,0x2D,0x00,0}, {54,0x44,0x2E,0x00,0},
+    {55,0x64,0x2E,0x20,1}, {56,0x64,0x2F,0x00,0}, {57,0x64,0x30,0x00,0},
+    {58,0x64,0x31,0x00,0}, {59,0x64,0x32,0x00,0}, {60,0x64,0x33,0x00,0},
+    {61,0x64,0x34,0x00,0}, {62,0x64,0x35,0x00,0}, {63,0x64,0x36,0x00,0},
+    {64,0x64,0x37,0x00,0}, {65,0x64,0x38,0x00,0}, {66,0x65,0x38,0x20,1},
+    {67,0x66,0x38,0x20,1}, {68,0x67,0x38,0x20,1}, {69,0x68,0x38,0x20,1},
+    {70,0x69,0x38,0x20,1}, {71,0x6A,0x38,0x20,1}, {72,0x6B,0x38,0x20,1},
+    {73,0x6C,0x38,0x20,1}, {74,0x6D,0x38,0x20,1}, {75,0x6E,0x38,0x20,1},
+    {76,0x6F,0x38,0x20,1}};
+
+
+#endif /* INCLUDED_AD9361_GAIN_TABLES_HPP */
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h b/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h
new file mode 100644
index 000000000..cb320e1f4
--- /dev/null
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h
@@ -0,0 +1,135 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+
+#ifndef INCLUDED_AD9361_SYNTH_LUT_HPP
+#define INCLUDED_AD9361_SYNTH_LUT_HPP
+
+
+double vco_index[53] = {12605000000, 12245000000, 11906000000, 11588000000,
+                        11288000000, 11007000000, 10742000000, 10492000000,
+                        10258000000, 10036000000, 9827800000, 9631100000,
+                        9445300000, 9269800000, 9103600000, 8946300000,
+                        8797000000, 8655300000, 8520600000, 8392300000,
+                        8269900000, 8153100000, 8041400000, 7934400000,
+                        7831800000, 7733200000, 7638400000, 7547100000,
+                        7459000000, 7374000000, 7291900000, 7212400000,
+                        7135500000, 7061000000, 6988700000, 6918600000,
+                        6850600000, 6784600000, 6720500000, 6658200000,
+                        6597800000, 6539200000, 6482300000, 6427000000,
+                        6373400000, 6321400000, 6270900000, 6222000000,
+                        6174500000, 6128400000, 6083600000, 6040100000,
+                        5997700000};
+
+int synth_cal_lut[53][12] = {   {10, 0, 4, 0, 15, 8, 8, 13, 4, 13, 15, 9},
+                                {10, 0, 4, 0, 15, 8, 9, 13, 4, 13, 15, 9},
+                                {10, 0, 4, 0, 15, 8, 10, 13, 4, 13, 15, 9},
+                                {10, 0, 4, 0, 15, 8, 11, 13, 4, 13, 15, 9},
+                                {10, 0, 4, 0, 15, 8, 11, 13, 4, 13, 15, 9},
+                                {10, 0, 4, 0, 14, 8, 12, 13, 4, 13, 15, 9},
+                                {10, 0, 4, 0, 14, 8, 13, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 14, 9, 13, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 14, 9, 14, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 14, 9, 15, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 14, 9, 15, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 13, 9, 16, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 13, 9, 17, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 13, 9, 18, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 13, 9, 18, 13, 4, 13, 15, 9},
+                                {10, 0, 5, 1, 13, 9, 19, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 14, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 14, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 15, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 15, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 16, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 16, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 17, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 17, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 18, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 18, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 19, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 19, 13, 4, 13, 15, 9},
+                                {10, 1, 6, 1, 15, 11, 20, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 12, 20, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 12, 21, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 12, 21, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 22, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 22, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 23, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 23, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 24, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 24, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 25, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 25, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 26, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 26, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 27, 13, 4, 13, 15, 9},
+                                {10, 1, 7, 2, 15, 14, 27, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 20, 13, 4, 13, 15, 9},
+                                {10, 3, 7, 3, 15, 12, 20, 13, 4, 13, 15, 9}};
+
+
+#if 0 /* This is the table for a 40MHz RFPLL Reference */
+int synth_cal_lut[53][12] = {   {10, 0, 4, 0, 15, 8, 8, 12, 3, 14, 15, 11},
+                                {10, 0, 4, 0, 15, 8, 9, 12, 3, 14, 15, 11},
+                                {10, 0, 4, 0, 15, 8, 9, 12, 3, 14, 15, 11},
+                                {10, 0, 4, 0, 15, 8, 10, 12, 3, 14, 15, 11},
+                                {10, 0, 4, 0, 15, 8, 11, 12, 3, 14, 15, 11},
+                                {10, 0, 4, 0, 15, 8, 11, 12, 3, 14, 15, 11},
+                                {10, 0, 4, 0, 14, 8, 12, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 13, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 13, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 14, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 15, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 15, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 16, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 17, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 17, 12, 3, 14, 15, 11},
+                                {10, 0, 5, 1, 14, 9, 18, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 13, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 14, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 14, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 15, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 15, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 16, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 16, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 18, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 18, 12, 3, 14, 15, 11},
+                                {10, 1, 6, 1, 15, 11, 19, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 12, 19, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 12, 20, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 12, 20, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 21, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 21, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 22, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 22, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 23, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 23, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 24, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 24, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 25, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 25, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 26, 12, 3, 14, 15, 11},
+                                {10, 1, 7, 2, 15, 14, 26, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 19, 12, 3, 14, 15, 11},
+                                {10, 3, 7, 3, 15, 12, 19, 12, 3, 14, 15, 11} };
+#endif
+
+#endif /* INCLUDED_AD9361_SYNTH_LUT_HPP */
diff --git a/host/lib/usrp/common/ad9361_transaction.h b/host/lib/usrp/common/ad9361_transaction.h
deleted file mode 100644
index 693f32e41..000000000
--- a/host/lib/usrp/common/ad9361_transaction.h
+++ /dev/null
@@ -1,109 +0,0 @@
-//
-// Copyright 2013 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-#ifndef INCLUDED_AD9361_TRANSACTION_H
-#define INCLUDED_AD9361_TRANSACTION_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//various constants
-#define AD9361_TRANSACTION_VERSION  0x4
-#define AD9361_DISPATCH_PACKET_SIZE 64
-
-//action types
-#define AD9361_ACTION_ECHO 0
-#define AD9361_ACTION_INIT 1
-#define AD9361_ACTION_SET_RX1_GAIN 2
-#define AD9361_ACTION_SET_TX1_GAIN 3
-#define AD9361_ACTION_SET_RX2_GAIN 4
-#define AD9361_ACTION_SET_TX2_GAIN 5
-#define AD9361_ACTION_SET_RX_FREQ 6
-#define AD9361_ACTION_SET_TX_FREQ 7
-#define AD9361_ACTION_SET_CODEC_LOOP 8
-#define AD9361_ACTION_SET_CLOCK_RATE 9
-#define AD9361_ACTION_SET_ACTIVE_CHAINS 10
-
-typedef union
-{
-    double d;
-    uint32_t x[2];
-} ad9361_double_union_t;
-
-static inline void ad9361_double_pack(const double input, uint32_t output[2])
-{
-    ad9361_double_union_t p = {};
-    p.d = input;
-    output[0] = p.x[0];
-    output[1] = p.x[1];
-}
-
-static inline double ad9361_double_unpack(const uint32_t input[2])
-{
-    ad9361_double_union_t p = {};
-    p.x[0] = input[0];
-    p.x[1] = input[1];
-    return p.d;
-}
-
-typedef struct
-{
-    //version is expected to be AD9361_TRANSACTION_VERSION
-    //check otherwise for compatibility
-    uint32_t version;
-
-    //sequence number - increment every call for sanity
-    uint32_t sequence;
-
-    //action tells us what to do, see AD9361_ACTION_*
-    uint32_t action;
-
-    union
-    {
-        //enable mask for chains
-        uint32_t enable_mask;
-
-        //true to enable codec internal loopback
-        uint32_t codec_loop;
-
-        //freq holds request LO freq and result from tune
-        uint32_t freq[2];
-
-        //gain holds request gain and result from action
-        uint32_t gain[2];
-
-        //rate holds request clock rate and result from action
-        uint32_t rate[2];
-
-    } value;
-
-    //error message comes back as a reply -
-    //set to null string for no error \0
-    char error_msg[];
-
-} ad9361_transaction_t;
-
-#define AD9361_TRANSACTION_MAX_ERROR_MSG (AD9361_DISPATCH_PACKET_SIZE - (sizeof(ad9361_transaction_t)-4)-1)	// -4 for 'error_msg' alignment padding, -1 for terminating \0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* INCLUDED_AD9361_TRANSACTION_H */
diff --git a/host/lib/usrp/common/adf4001_ctrl.cpp b/host/lib/usrp/common/adf4001_ctrl.cpp
index 46171c7ce..a7510c272 100644
--- a/host/lib/usrp/common/adf4001_ctrl.cpp
+++ b/host/lib/usrp/common/adf4001_ctrl.cpp
@@ -93,7 +93,7 @@ boost::uint32_t adf4001_regs_t::get_reg(boost::uint8_t addr) {
 }
 
 
-adf4001_ctrl::adf4001_ctrl(spi_core_3000::sptr _spi, int slaveno):
+adf4001_ctrl::adf4001_ctrl(uhd::spi_iface::sptr _spi, int slaveno):
     spi_iface(_spi),
     slaveno(slaveno)
     {
diff --git a/host/lib/usrp/common/adf4001_ctrl.hpp b/host/lib/usrp/common/adf4001_ctrl.hpp
index a16cff3fa..9ea3caf1a 100644
--- a/host/lib/usrp/common/adf4001_ctrl.hpp
+++ b/host/lib/usrp/common/adf4001_ctrl.hpp
@@ -123,12 +123,11 @@ public:
 
 class adf4001_ctrl {
 public:
-
-    adf4001_ctrl(spi_core_3000::sptr _spi, int slaveno);
+    adf4001_ctrl(uhd::spi_iface::sptr _spi, int slaveno);
     void set_lock_to_ext_ref(bool external);
 
 private:
-    spi_core_3000::sptr spi_iface;
+    uhd::spi_iface::sptr spi_iface;
     int slaveno;
     spi_config_t spi_config;
     adf4001_regs_t adf4001_regs;
diff --git a/host/lib/usrp/e100/e100_impl.cpp b/host/lib/usrp/e100/e100_impl.cpp
index b49ba64a2..e59df7708 100644
--- a/host/lib/usrp/e100/e100_impl.cpp
+++ b/host/lib/usrp/e100/e100_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2012 Ettus Research LLC
+// Copyright 2010-2012,2014 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -96,7 +96,7 @@ static device::sptr e100_make(const device_addr_t &device_addr){
 }
 
 UHD_STATIC_BLOCK(register_e100_device){
-    device::register_device(&e100_find, &e100_make);
+    device::register_device(&e100_find, &e100_make, device::USRP);
 }
 
 static const uhd::dict<std::string, std::string> model_to_fpga_file_name = boost::assign::map_list_of
@@ -109,6 +109,7 @@ static const uhd::dict<std::string, std::string> model_to_fpga_file_name = boost
  **********************************************************************/
 e100_impl::e100_impl(const uhd::device_addr_t &device_addr){
     _tree = property_tree::make();
+    _type = device::USRP;
 
     //read the eeprom so we can determine the hardware
     _dev_i2c_iface = e100_ctrl::make_dev_i2c_iface(E100_I2C_DEV_NODE);
diff --git a/host/lib/usrp/multi_usrp.cpp b/host/lib/usrp/multi_usrp.cpp
index c13d3efba..388cf03fa 100644
--- a/host/lib/usrp/multi_usrp.cpp
+++ b/host/lib/usrp/multi_usrp.cpp
@@ -246,7 +246,7 @@ static double derive_freq_from_xx_subdev_and_dsp(
 class multi_usrp_impl : public multi_usrp{
 public:
     multi_usrp_impl(const device_addr_t &addr){
-        _dev = device::make(addr);
+        _dev = device::make(addr, device::USRP);
         _tree = _dev->get_tree();
     }
 
diff --git a/host/lib/usrp/usrp1/usrp1_impl.cpp b/host/lib/usrp/usrp1/usrp1_impl.cpp
index 0ba2e1e4a..709092e42 100644
--- a/host/lib/usrp/usrp1/usrp1_impl.cpp
+++ b/host/lib/usrp/usrp1/usrp1_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2012 Ettus Research LLC
+// Copyright 2010-2012,2014 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -139,7 +139,7 @@ static device::sptr usrp1_make(const device_addr_t &device_addr){
 }
 
 UHD_STATIC_BLOCK(register_usrp1_device){
-    device::register_device(&usrp1_find, &usrp1_make);
+    device::register_device(&usrp1_find, &usrp1_make, device::USRP);
 }
 
 /***********************************************************************
@@ -147,6 +147,7 @@ UHD_STATIC_BLOCK(register_usrp1_device){
  **********************************************************************/
 usrp1_impl::usrp1_impl(const device_addr_t &device_addr){
     UHD_MSG(status) << "Opening a USRP1 device..." << std::endl;
+    _type = device::USRP;
 
     //extract the FPGA path for the USRP1
     std::string usrp1_fpga_image = find_image_path(
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index d96a8ab7d..93885fbd3 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2012 Ettus Research LLC
+// Copyright 2010-2012,2014 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -200,7 +200,7 @@ static device::sptr usrp2_make(const device_addr_t &device_addr){
 }
 
 UHD_STATIC_BLOCK(register_usrp2_device){
-    device::register_device(&usrp2_find, &usrp2_make);
+    device::register_device(&usrp2_find, &usrp2_make, device::USRP);
 }
 
 /***********************************************************************
@@ -368,6 +368,7 @@ usrp2_impl::usrp2_impl(const device_addr_t &_device_addr){
     // create controller objects and initialize the properties tree
     ////////////////////////////////////////////////////////////////////
     _tree = property_tree::make();
+    _type = device::USRP;
     _tree->create<std::string>("/name").set("USRP2 / N-Series Device");
 
     for (size_t mbi = 0; mbi < device_args.size(); mbi++){
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index 1b651065d..d5eacc3ea 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -326,7 +326,7 @@ static device::sptr x300_make(const device_addr_t &device_addr)
 
 UHD_STATIC_BLOCK(register_x300_device)
 {
-    device::register_device(&x300_find, &x300_make);
+    device::register_device(&x300_find, &x300_make, device::USRP);
 }
 
 static void x300_load_fw(wb_iface::sptr fw_reg_ctrl, const std::string &file_name)
@@ -355,6 +355,7 @@ static void x300_load_fw(wb_iface::sptr fw_reg_ctrl, const std::string &file_nam
 x300_impl::x300_impl(const uhd::device_addr_t &dev_addr)
 {
     UHD_MSG(status) << "X300 initialization sequence..." << std::endl;
+    _type = device::USRP;
     _async_md.reset(new async_md_type(1000/*messages deep*/));
     _tree = uhd::property_tree::make();
     _tree->create<std::string>("/name").set("X-Series Device");
diff --git a/host/lib/usrp_clock/CMakeLists.txt b/host/lib/usrp_clock/CMakeLists.txt
new file mode 100644
index 000000000..8a58aa9ac
--- /dev/null
+++ b/host/lib/usrp_clock/CMakeLists.txt
@@ -0,0 +1,26 @@
+#
+# Copyright 2011-2014 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# This file included, use CMake directory variables
+########################################################################
+
+LIBUHD_APPEND_SOURCES(
+    ${CMAKE_CURRENT_SOURCE_DIR}/multi_usrp_clock.cpp
+)
+
+INCLUDE_SUBDIRECTORY(octoclock)
diff --git a/host/lib/usrp_clock/multi_usrp_clock.cpp b/host/lib/usrp_clock/multi_usrp_clock.cpp
new file mode 100644
index 000000000..77489e13b
--- /dev/null
+++ b/host/lib/usrp_clock/multi_usrp_clock.cpp
@@ -0,0 +1,93 @@
+//
+// Copyright 2010-2013 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <uhd/property_tree.hpp>
+#include <uhd/usrp_clock/multi_usrp_clock.hpp>
+#include <uhd/usrp_clock/octoclock_eeprom.hpp>
+
+#include <uhd/utils/msg.hpp>
+#include <uhd/exception.hpp>
+#include <uhd/utils/log.hpp>
+#include <boost/assign/list_of.hpp>
+#include <boost/foreach.hpp>
+#include <boost/format.hpp>
+
+using namespace uhd;
+using namespace uhd::usrp_clock;
+
+/***********************************************************************
+ * Multi USRP Clock implementation
+ **********************************************************************/
+class multi_usrp_clock_impl : public multi_usrp_clock{
+public:
+    multi_usrp_clock_impl(const device_addr_t &addr){
+        _dev = device::make(addr, device::CLOCK);
+        _tree = _dev->get_tree();
+    }
+
+    device::sptr get_device(void){
+        return _dev;
+    }
+
+    std::string get_pp_string(void){
+        std::string buff = str(boost::format("%s USRP Clock Device\n")
+            % ((get_num_boards() > 1) ? "Multi" : "Single")
+        );
+        for(size_t i = 0; i < get_num_boards(); i++){
+            buff += str(boost::format("  Board %s\n") % i);
+            buff += str(boost::format("    Reference: %s\n")
+                        % (get_sensor("using_ref", i).value)
+                    );
+        }
+
+        return buff;
+    }
+
+    size_t get_num_boards(void){
+        return _tree->list("/mboards").size();
+    }
+
+    boost::uint32_t get_time(size_t board){
+        std::string board_str = str(boost::format("/mboards/%d") % board);
+
+        return _tree->access<boost::uint32_t>(board_str / "time").get();
+    }
+
+    sensor_value_t get_sensor(const std::string &name, size_t board){
+        std::string board_str = str(boost::format("/mboards/%d") % board);
+
+        return _tree->access<sensor_value_t>(board_str / "sensors" / name).get();
+    }
+
+    std::vector<std::string> get_sensor_names(size_t board){
+        std::string board_str = str(boost::format("/mboards/%d") % board);
+
+        return _tree->list(board_str / "sensors");
+    }
+
+private:
+    device::sptr _dev;
+    property_tree::sptr _tree;
+};
+
+/***********************************************************************
+ * Multi USRP Clock factory function
+ **********************************************************************/
+multi_usrp_clock::sptr multi_usrp_clock::make(const device_addr_t &dev_addr){
+    UHD_LOG << "multi_usrp_clock::make with args " << dev_addr.to_pp_string() << std::endl;
+    return sptr(new multi_usrp_clock_impl(dev_addr));
+}
diff --git a/host/lib/usrp_clock/octoclock/CMakeLists.txt b/host/lib/usrp_clock/octoclock/CMakeLists.txt
new file mode 100644
index 000000000..e363bb9da
--- /dev/null
+++ b/host/lib/usrp_clock/octoclock/CMakeLists.txt
@@ -0,0 +1,33 @@
+#
+# Copyright 2011-2014 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# This file included, use CMake directory variables
+########################################################################
+
+########################################################################
+# Conditionally configure the OctoClock support
+########################################################################
+LIBUHD_REGISTER_COMPONENT("OctoClock" ENABLE_OCTOCLOCK ON "ENABLE_LIBUHD" OFF)
+
+IF(ENABLE_OCTOCLOCK)
+    LIBUHD_APPEND_SOURCES(
+        ${CMAKE_CURRENT_SOURCE_DIR}/octoclock_eeprom.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/octoclock_impl.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/octoclock_uart.cpp
+    )
+ENDIF(ENABLE_OCTOCLOCK)
diff --git a/host/lib/usrp_clock/octoclock/common.h b/host/lib/usrp_clock/octoclock/common.h
new file mode 100644
index 000000000..96acbb30f
--- /dev/null
+++ b/host/lib/usrp_clock/octoclock/common.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2014 Ettus Research LLC
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _OCTOCLOCK_COMMON_H_
+#define _OCTOCLOCK_COMMON_H_
+
+#include <stdint.h>
+
+/*
+ * C++ macros used for code cleanliness and extern "C" declaration.
+ */
+#ifdef __cplusplus
+
+#define UHD_OCTOCLOCK_SEND_AND_RECV(xport, pkt_code, pkt_out, len, data) pkt_out.proto_ver = OCTOCLOCK_FW_COMPAT_NUM; \
+                                                                         pkt_out.code = pkt_code; \
+                                                                         xport->send(boost::asio::buffer(&pkt_out, sizeof(octoclock_packet_t))); \
+                                                                         len = xport->recv(boost::asio::buffer(data), 2);
+
+#define UHD_OCTOCLOCK_PACKET_MATCHES(pkt_code, pkt_out, pkt_in, len) (len > offsetof(octoclock_packet_t, data) and \
+                                                                      pkt_in->sequence == pkt_out.sequence and \
+                                                                      pkt_in->code == pkt_code)
+
+extern "C" {
+#endif
+
+/*
+ * This code is used by both the C firmware and C++ host driver, so
+ * only valid C code should go in this section.
+ */
+
+//These values are placed in the octoclock_packet_t.proto_ver field
+#define OCTOCLOCK_BOOTLOADER_PROTO_VER 1234
+#define OCTOCLOCK_FW_COMPAT_NUM 2
+
+//UDP ports assigned for different tasks
+#define OCTOCLOCK_UDP_CTRL_PORT   50000
+#define OCTOCLOCK_UDP_GPSDO_PORT  50001
+#define OCTOCLOCK_UDP_FW_PORT     50002
+#define OCTOCLOCK_UDP_EEPROM_PORT 50003
+
+typedef enum {
+    NO_CODE,
+
+    OCTOCLOCK_QUERY_CMD,
+    OCTOCLOCK_QUERY_ACK,
+
+    SEND_EEPROM_CMD,
+    SEND_EEPROM_ACK,
+    BURN_EEPROM_CMD,
+    BURN_EEPROM_SUCCESS_ACK,
+    BURN_EEPROM_FAILURE_ACK,
+    CLEAR_EEPROM_CMD,
+    CLEAR_EEPROM_ACK,
+
+    SEND_STATE_CMD,
+    SEND_STATE_ACK,
+
+    RESET_CMD,
+    RESET_ACK,
+
+    HOST_SEND_TO_GPSDO_CMD,
+    HOST_SEND_TO_GPSDO_ACK,
+    SEND_POOLSIZE_CMD,
+    SEND_POOLSIZE_ACK,
+    SEND_CACHE_STATE_CMD,
+    SEND_CACHE_STATE_ACK,
+    SEND_GPSDO_CACHE_CMD,
+    SEND_GPSDO_CACHE_ACK,
+
+    PREPARE_FW_BURN_CMD,
+    FW_BURN_READY_ACK,
+    FILE_TRANSFER_CMD,
+    FILE_TRANSFER_ACK,
+    READ_FW_CMD,
+    READ_FW_ACK,
+    FINALIZE_BURNING_CMD,
+    FINALIZE_BURNING_ACK,
+} packet_code_t;
+
+typedef enum {
+    NO_REF,
+    INTERNAL,
+    EXTERNAL
+} ref_t;
+
+typedef enum {
+    UP,
+    DOWN
+} switch_pos_t;
+
+#pragma pack(push,1)
+
+// Structure of values in EEPROM, starting in location 0
+typedef struct {
+    uint8_t mac_addr[6];
+    uint32_t ip_addr;
+    uint32_t dr_addr;
+    uint32_t netmask;
+    uint8_t serial[10];
+    uint8_t name[10];
+    uint8_t revision;
+} octoclock_fw_eeprom_t;
+
+typedef struct {
+    uint8_t external_detected;
+    uint8_t gps_detected;
+    uint8_t which_ref;
+    uint8_t switch_pos;
+} octoclock_state_t;
+
+typedef struct {
+    uint8_t num_wraps;
+    uint8_t pos;
+} gpsdo_cache_state_t;
+
+typedef struct {
+    uint32_t proto_ver;
+    uint32_t sequence;
+    uint8_t code;
+    union {
+        uint16_t len;
+        gpsdo_cache_state_t state;
+        uint16_t poolsize;
+        uint16_t addr;
+    };
+    uint8_t data[256];
+} octoclock_packet_t;
+
+#pragma pack(pop)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OCTOCLOCK_COMMON_H_ */
diff --git a/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp b/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp
new file mode 100644
index 000000000..6d54cac70
--- /dev/null
+++ b/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp
@@ -0,0 +1,184 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <uhd/exception.hpp>
+#include <uhd/usrp_clock/octoclock_eeprom.hpp>
+#include <uhd/transport/udp_simple.hpp>
+#include <uhd/usrp/mboard_eeprom.hpp>
+#include <uhd/types/mac_addr.hpp>
+#include <uhd/utils/byteswap.hpp>
+#include <boost/assign/list_of.hpp>
+#include <boost/asio.hpp>
+#include <boost/lexical_cast.hpp>
+#include <boost/foreach.hpp>
+
+#include <iostream>
+
+#include "common.h"
+
+typedef boost::asio::ip::address_v4 ip_v4;
+
+using namespace uhd;
+using namespace uhd::usrp_clock;
+using namespace uhd::transport;
+
+/***********************************************************************
+ * Utility functions
+ **********************************************************************/
+
+//! A wrapper around std::copy that takes ranges instead of iterators.
+template<typename RangeSrc, typename RangeDst> inline
+void byte_copy(const RangeSrc &src, RangeDst &dst){
+    std::copy(boost::begin(src), boost::end(src), boost::begin(dst));
+}
+
+//! create a string from a byte vector, return empty if invalid ascii
+static const std::string bytes_to_string(const byte_vector_t &bytes){
+    std::string out;
+    BOOST_FOREACH(boost::uint8_t byte, bytes){
+        if (byte < 32 or byte > 127) return out;
+        out += byte;
+    }
+    return out;
+}
+
+/***********************************************************************
+ * Implementation
+ **********************************************************************/
+void octoclock_eeprom_t::_load(){
+    boost::uint32_t octoclock_data[udp_simple::mtu];
+    const octoclock_packet_t *pkt_in = reinterpret_cast<const octoclock_packet_t*>(octoclock_data);
+    const octoclock_fw_eeprom_t *eeprom_in = reinterpret_cast<const octoclock_fw_eeprom_t*>(pkt_in->data);
+
+    octoclock_packet_t pkt_out;
+    pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand());
+    size_t len = 0;
+
+    UHD_OCTOCLOCK_SEND_AND_RECV(xport, SEND_EEPROM_CMD, pkt_out, len, octoclock_data);
+    if(UHD_OCTOCLOCK_PACKET_MATCHES(SEND_EEPROM_ACK, pkt_out, pkt_in, len)){
+        //MAC address
+        byte_vector_t mac_bytes(eeprom_in->mac_addr, eeprom_in->mac_addr+6);
+        (*this)["mac-addr"] = mac_addr_t::from_bytes(mac_bytes).to_string();
+
+        //IP address
+        boost::uint32_t ip_addr = uhd::htonx<boost::uint32_t>(eeprom_in->ip_addr);
+        ip_v4::bytes_type ip_addr_bytes;
+        memcpy(&ip_addr_bytes, &ip_addr, 4);
+        (*this)["ip-addr"] = ip_v4(ip_addr_bytes).to_string();
+
+        //Default router
+        boost::uint32_t dr_addr = uhd::htonx<boost::uint32_t>(eeprom_in->dr_addr);
+        ip_v4::bytes_type dr_addr_bytes;
+        memcpy(&dr_addr_bytes, &dr_addr, 4);
+        (*this)["gateway"] = ip_v4(dr_addr_bytes).to_string();
+
+        //Netmask
+        boost::uint32_t netmask = uhd::htonx<boost::uint32_t>(eeprom_in->netmask);
+        ip_v4::bytes_type netmask_bytes;
+        memcpy(&netmask_bytes, &netmask, 4);
+        (*this)["netmask"] = ip_v4(netmask_bytes).to_string();
+
+        //Serial
+        std::string raw_serial((char*)eeprom_in->serial, 10);
+        byte_vector_t serial_bytes(raw_serial.begin(), raw_serial.end());
+        (*this)["serial"] = bytes_to_string(serial_bytes);
+
+        //Name
+        std::string raw_name((char*)eeprom_in->name, 10);
+        byte_vector_t name_bytes(raw_name.begin(), raw_name.end());
+        (*this)["name"] = bytes_to_string(name_bytes);
+
+        //Revision
+        (*this)["revision"] = boost::lexical_cast<std::string>(int(eeprom_in->revision));
+    }
+    else throw uhd::runtime_error("Error loading OctoClock EEPROM.");
+}
+
+void octoclock_eeprom_t::_store() const {
+    boost::uint32_t octoclock_data[udp_simple::mtu];
+    const octoclock_packet_t *pkt_in = reinterpret_cast<const octoclock_packet_t *>(octoclock_data);
+
+    octoclock_packet_t pkt_out;
+    pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand());
+    pkt_out.len = sizeof(octoclock_fw_eeprom_t);
+    size_t len = 0;
+
+    octoclock_fw_eeprom_t *eeprom_out = reinterpret_cast<octoclock_fw_eeprom_t *>(&pkt_out.data);
+    memset(eeprom_out, 0xFF, sizeof(octoclock_fw_eeprom_t));
+
+    //MAC address
+    if((*this).has_key("mac-addr")){
+        byte_copy(mac_addr_t::from_string((*this)["mac-addr"]).to_bytes(), eeprom_out->mac_addr);
+    }
+
+    //IP address
+    if((*this).has_key("ip-addr")){
+        ip_v4::bytes_type ip_addr_bytes = ip_v4::from_string((*this)["ip-addr"]).to_bytes();
+        memcpy(&eeprom_out->ip_addr, &ip_addr_bytes, 4);
+        eeprom_out->ip_addr = uhd::htonx<boost::uint32_t>(eeprom_out->ip_addr);
+    }
+
+    //Default router
+    if((*this).has_key("gateway")){
+        ip_v4::bytes_type dr_addr_bytes = ip_v4::from_string((*this)["gateway"]).to_bytes();
+        memcpy(&eeprom_out->dr_addr, &dr_addr_bytes, 4);
+        eeprom_out->dr_addr = uhd::htonx<boost::uint32_t>(eeprom_out->dr_addr);
+    }
+
+    //Netmask
+    if((*this).has_key("netmask")){
+        ip_v4::bytes_type netmask_bytes = ip_v4::from_string((*this)["netmask"]).to_bytes();
+        memcpy(&eeprom_out->netmask, &netmask_bytes, 4);
+        eeprom_out->netmask = uhd::htonx<boost::uint32_t>(eeprom_out->netmask);
+    }
+
+    //Serial
+    if((*this).has_key("serial")){
+        byte_copy(byte_vector_t((*this)["serial"].begin(), (*this)["serial"].end()), eeprom_out->serial);
+    }
+
+    //Name
+    if((*this).has_key("name")){
+        byte_copy(byte_vector_t((*this)["name"].begin(), (*this)["name"].end()), eeprom_out->name);
+    }
+
+    //Revision
+    if((*this).has_key("revision")){
+        eeprom_out->revision = (*this)["revision"][0]-'0';
+    }
+
+    UHD_OCTOCLOCK_SEND_AND_RECV(xport, BURN_EEPROM_CMD, pkt_out, len, octoclock_data);
+    if(not UHD_OCTOCLOCK_PACKET_MATCHES(BURN_EEPROM_SUCCESS_ACK, pkt_out, pkt_in, len))
+        throw uhd::runtime_error("Error writing to OctoClock EEPROM.");
+}
+
+/***********************************************************************
+ * Implementation of OctoClock EEPROM
+ **********************************************************************/
+octoclock_eeprom_t::octoclock_eeprom_t(void){
+    /* NOP */
+}
+
+octoclock_eeprom_t::octoclock_eeprom_t(udp_simple::sptr transport){
+    xport = transport;
+    _load();
+}
+
+void octoclock_eeprom_t::commit() const{
+    if(!xport) throw uhd::runtime_error("There is no set device communication.");
+    _store();
+}
diff --git a/host/lib/usrp_clock/octoclock/octoclock_impl.cpp b/host/lib/usrp_clock/octoclock/octoclock_impl.cpp
new file mode 100644
index 000000000..8c207dd9f
--- /dev/null
+++ b/host/lib/usrp_clock/octoclock/octoclock_impl.cpp
@@ -0,0 +1,437 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <iostream>
+
+#include <boost/asio.hpp>
+#include <boost/assign.hpp>
+#include <boost/cstdint.hpp>
+#include <boost/filesystem.hpp>
+#include <boost/foreach.hpp>
+#include <boost/format.hpp>
+#include <boost/thread.hpp>
+
+#include <uhd/device.hpp>
+#include <uhd/exception.hpp>
+#include <uhd/transport/udp_simple.hpp>
+#include <uhd/transport/if_addrs.hpp>
+#include <uhd/types/dict.hpp>
+#include <uhd/usrp/gps_ctrl.hpp>
+#include <uhd/usrp_clock/octoclock_eeprom.hpp>
+#include <uhd/utils/byteswap.hpp>
+#include <uhd/utils/images.hpp>
+#include <uhd/utils/msg.hpp>
+#include <uhd/utils/paths.hpp>
+#include <uhd/utils/static.hpp>
+
+#include "octoclock_impl.hpp"
+#include "octoclock_uart.hpp"
+#include "common.h"
+
+using namespace uhd;
+using namespace uhd::usrp_clock;
+using namespace uhd::transport;
+namespace asio = boost::asio;
+namespace fs = boost::filesystem;
+
+/***********************************************************************
+ * Discovery
+ **********************************************************************/
+device_addrs_t octoclock_find(const device_addr_t &hint){
+    //Handle the multi-device discovery
+    device_addrs_t hints = separate_device_addr(hint);
+    if (hints.size() > 1){
+        device_addrs_t found_devices;
+        std::string error_msg;
+        BOOST_FOREACH(const device_addr_t &hint_i, hints){
+            device_addrs_t found_devices_i = octoclock_find(hint_i);
+            if (found_devices_i.size() != 1) error_msg += str(boost::format(
+                "Could not resolve device hint \"%s\" to a single device."
+            ) % hint_i.to_string());
+            else found_devices.push_back(found_devices_i[0]);
+        }
+        if (found_devices.empty()) return device_addrs_t();
+        if (not error_msg.empty()) throw uhd::value_error(error_msg);
+        return device_addrs_t(1, combine_device_addrs(found_devices));
+    }
+
+    //Initialize the hint for a single device case
+    UHD_ASSERT_THROW(hints.size() <= 1);
+    hints.resize(1); //In case it was empty
+    device_addr_t _hint = hints[0];
+    device_addrs_t octoclock_addrs;
+
+    //return an empty list of addresses when type is set to non-OctoClock
+    if (hint.has_key("type") and hint["type"].find("octoclock") == std::string::npos) return octoclock_addrs;
+
+    //Return an empty list of addresses when a resource is specified,
+    //since a resource is intended for a different, non-USB, device.
+    if (hint.has_key("resource")) return octoclock_addrs;
+
+    //If no address was specified, send a broadcast on each interface
+    if (not _hint.has_key("addr")){
+        BOOST_FOREACH(const if_addrs_t &if_addrs, get_if_addrs()){
+            //avoid the loopback device
+            if (if_addrs.inet == asio::ip::address_v4::loopback().to_string()) continue;
+
+            //create a new hint with this broadcast address
+            device_addr_t new_hint = hint;
+            new_hint["addr"] = if_addrs.bcast;
+
+            //call discover with the new hint and append results
+            device_addrs_t new_octoclock_addrs = octoclock_find(new_hint);
+            octoclock_addrs.insert(octoclock_addrs.begin(),
+                new_octoclock_addrs.begin(), new_octoclock_addrs.end()
+            );
+        }
+        return octoclock_addrs;
+    }
+
+    //Create a UDP transport to communicate
+    udp_simple::sptr udp_transport = udp_simple::make_broadcast(
+                                        _hint["addr"],
+                                        BOOST_STRINGIZE(OCTOCLOCK_UDP_CTRL_PORT)
+                                     );
+
+    //Send a query packet
+    octoclock_packet_t pkt_out;
+    pkt_out.proto_ver = OCTOCLOCK_FW_COMPAT_NUM;
+    pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand());
+    pkt_out.len = 0;
+    pkt_out.code = OCTOCLOCK_QUERY_CMD;
+    try{
+        udp_transport->send(boost::asio::buffer(&pkt_out, sizeof(pkt_out)));
+    }
+    catch(const std::exception &ex){
+        UHD_MSG(error) << "OctoClock network discovery error - " << ex.what() << std::endl;
+    }
+    catch(...){
+        UHD_MSG(error) << "OctoClock network discovery unknown error" << std::endl;
+    }
+
+    boost::uint8_t octoclock_data[udp_simple::mtu];
+    const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data);
+
+    while(true){
+        size_t len = udp_transport->recv(asio::buffer(octoclock_data));
+        if(UHD_OCTOCLOCK_PACKET_MATCHES(OCTOCLOCK_QUERY_ACK, pkt_out, pkt_in, len)){
+            device_addr_t new_addr;
+            new_addr["addr"] = udp_transport->get_recv_addr();
+
+            //Attempt direct communication with OctoClock
+            udp_simple::sptr ctrl_xport = udp_simple::make_connected(
+                                              new_addr["addr"],
+                                              BOOST_STRINGIZE(OCTOCLOCK_UDP_CTRL_PORT)
+                                          );
+            UHD_OCTOCLOCK_SEND_AND_RECV(ctrl_xport, OCTOCLOCK_QUERY_CMD, pkt_out, len, octoclock_data);
+            if(UHD_OCTOCLOCK_PACKET_MATCHES(OCTOCLOCK_QUERY_ACK, pkt_out, pkt_in, len)){
+                //If the OctoClock is in its bootloader, don't ask for details
+                if(pkt_in->proto_ver == OCTOCLOCK_BOOTLOADER_PROTO_VER){
+                    new_addr["type"] = "octoclock-bootloader";
+                    octoclock_addrs.push_back(new_addr);
+                }
+                else{
+                    new_addr["type"] = "octoclock";
+
+                    octoclock_eeprom_t oc_eeprom(ctrl_xport);
+                    new_addr["name"] = oc_eeprom["name"];
+                    new_addr["serial"] = oc_eeprom["serial"];
+
+                    //Filter based on optional keys (if any)
+                    if(
+                       (not _hint.has_key("name") or (_hint["name"] == new_addr["name"])) and
+                       (not _hint.has_key("serial") or (_hint["serial"] == new_addr["serial"]))
+                    ){
+                        octoclock_addrs.push_back(new_addr);
+                    }
+                }
+            }
+            else continue;
+        }
+
+        if(len == 0) break;
+    }
+
+    return octoclock_addrs;
+}
+
+device::sptr octoclock_make(const device_addr_t &device_addr){
+    return device::sptr(new octoclock_impl(device_addr));
+}
+
+UHD_STATIC_BLOCK(register_octoclock_device){
+    device::register_device(&octoclock_find, &octoclock_make, device::CLOCK);
+}
+
+/***********************************************************************
+ * Structors
+ **********************************************************************/
+octoclock_impl::octoclock_impl(const device_addr_t &_device_addr){
+    UHD_MSG(status) << "Opening an OctoClock device..." << std::endl;
+    _type = device::CLOCK;
+    device_addrs_t device_args = separate_device_addr(_device_addr);
+    _sequence = std::rand();
+
+    ////////////////////////////////////////////////////////////////////
+    // Initialize the property tree
+    ////////////////////////////////////////////////////////////////////
+    _tree = property_tree::make();
+    _tree->create<std::string>("/name").set("OctoClock Device");
+
+    for(size_t oci = 0; oci < device_args.size(); oci++){
+        const device_addr_t device_args_i = device_args[oci];
+        const std::string addr = device_args_i["addr"];
+        //Can't make a device out of an OctoClock in bootloader state
+        if(device_args_i["type"] == "octoclock-bootloader"){
+            throw uhd::runtime_error(str(boost::format(
+                    "\n\nThis device is in its bootloader state and cannot be used by UHD.\n"
+                    "This may mean the firmware on the device has been corrupted and will\n"
+                    "need to be burned again.\n\n"
+                    "%s\n"
+                ) % _get_images_help_message(addr)));
+        }
+
+        const std::string oc = boost::lexical_cast<std::string>(oci);
+
+        ////////////////////////////////////////////////////////////////////
+        // Set up UDP transports
+        ////////////////////////////////////////////////////////////////////
+        _oc_dict[oc].ctrl_xport = udp_simple::make_connected(addr, BOOST_STRINGIZE(OCTOCLOCK_UDP_CTRL_PORT));
+        _oc_dict[oc].gpsdo_xport = udp_simple::make_connected(addr, BOOST_STRINGIZE(OCTOCLOCK_UDP_GPSDO_PORT));
+
+        const fs_path oc_path = "/mboards/" + oc;
+        _tree->create<std::string>(oc_path / "name").set("OctoClock");
+
+        ////////////////////////////////////////////////////////////////////
+        // Check the firmware compatibility number
+        ////////////////////////////////////////////////////////////////////
+        boost::uint32_t fw_version = _get_fw_version(oc);
+        if(fw_version != OCTOCLOCK_FW_COMPAT_NUM){
+            throw uhd::runtime_error(str(boost::format(
+                    "\n\nPlease update your OctoClock's firmware.\n"
+                    "Expected firmware compatibility number %d, but got %d:\n"
+                    "The firmware build is not compatible with the host code build.\n\n"
+                    "%s\n"
+                ) % int(OCTOCLOCK_FW_COMPAT_NUM) % int(fw_version) % _get_images_help_message(addr)));
+        }
+        _tree->create<std::string>(oc_path / "fw_version").set(boost::lexical_cast<std::string>(int(fw_version)));
+
+        ////////////////////////////////////////////////////////////////////
+        // Set up EEPROM
+        ////////////////////////////////////////////////////////////////////
+        _oc_dict[oc].eeprom = octoclock_eeprom_t(_oc_dict[oc].ctrl_xport);
+        _tree->create<octoclock_eeprom_t>(oc_path / "eeprom")
+            .set(_oc_dict[oc].eeprom)
+            .subscribe(boost::bind(&octoclock_impl::_set_eeprom, this, oc, _1));
+
+        ////////////////////////////////////////////////////////////////////
+        // Initialize non-GPSDO sensors
+        ////////////////////////////////////////////////////////////////////
+        _tree->create<boost::uint32_t>(oc_path / "time")
+            .publish(boost::bind(&octoclock_impl::_get_time, this, oc));
+        _tree->create<sensor_value_t>(oc_path / "sensors/ext_ref_detected")
+            .publish(boost::bind(&octoclock_impl::_ext_ref_detected, this, oc));
+        _tree->create<sensor_value_t>(oc_path / "sensors/gps_detected")
+            .publish(boost::bind(&octoclock_impl::_gps_detected, this, oc));
+        _tree->create<sensor_value_t>(oc_path / "sensors/using_ref")
+            .publish(boost::bind(&octoclock_impl::_which_ref, this, oc));
+        _tree->create<sensor_value_t>(oc_path / "sensors/switch_pos")
+            .publish(boost::bind(&octoclock_impl::_switch_pos, this, oc));
+
+        ////////////////////////////////////////////////////////////////////
+        // Check reference and GPSDO
+        ////////////////////////////////////////////////////////////////////
+        std::string asterisk = (device_args.size() > 1) ? " * " : "";
+
+        if(device_args.size() > 1){
+            UHD_MSG(status) << std::endl << "Checking status of " << addr << ":" << std::endl;
+        }
+        UHD_MSG(status) << boost::format("%sDetecting internal GPSDO...") % asterisk << std::flush;
+
+        _get_state(oc);
+        if(_oc_dict[oc].state.gps_detected){
+            try{
+                _oc_dict[oc].gps = gps_ctrl::make(octoclock_make_uart_iface(_oc_dict[oc].gpsdo_xport));
+
+                if(_oc_dict[oc].gps and _oc_dict[oc].gps->gps_detected()){
+                    BOOST_FOREACH(const std::string &name, _oc_dict[oc].gps->get_sensors()){
+                        _tree->create<sensor_value_t>(oc_path / "sensors" / name)
+                            .publish(boost::bind(&gps_ctrl::get_sensor, _oc_dict[oc].gps, name));
+                    }
+                }
+                else{
+                    //If GPSDO communication failed, set gps_detected to false
+                    _oc_dict[oc].state.gps_detected = 0;
+                    UHD_MSG(warning) << "Device reports that it has a GPSDO, but we cannot communicate with it." << std::endl;
+                    std::cout << std::endl;
+                }
+            }
+            catch(std::exception &e){
+                UHD_MSG(error) << "An error occurred making GPSDO control: " << e.what() << std::endl;
+            }
+        }
+        else UHD_MSG(status) << "No GPSDO found" << std::endl;
+        UHD_MSG(status) << boost::format("%sDetecting external reference...%s") % asterisk
+                                                                                % _ext_ref_detected(oc).value
+                        << std::endl;
+        UHD_MSG(status) << boost::format("%sDetecting switch position...%s") % asterisk
+                                                                             % _switch_pos(oc).value
+                        << std::endl;
+        std::string ref = _which_ref(oc).value;
+        if(ref == "none") UHD_MSG(status) << boost::format("%sDevice is not using any reference") % asterisk << std::endl;
+        else UHD_MSG(status) << boost::format("%sDevice is using %s reference") % asterisk
+                                                                                % _which_ref(oc).value
+                             << std::endl;
+    }
+}
+
+rx_streamer::sptr octoclock_impl::get_rx_stream(UHD_UNUSED(const stream_args_t &args)){
+    throw uhd::not_implemented_error("This function is incompatible with this device.");
+}
+
+tx_streamer::sptr octoclock_impl::get_tx_stream(UHD_UNUSED(const stream_args_t &args)){
+    throw uhd::not_implemented_error("This function is incompatible with this device.");
+}
+
+bool octoclock_impl::recv_async_msg(UHD_UNUSED(uhd::async_metadata_t&), UHD_UNUSED(double)){
+    throw uhd::not_implemented_error("This function is incompatible with this device.");
+}
+
+void octoclock_impl::_set_eeprom(const std::string &oc, const octoclock_eeprom_t &oc_eeprom){
+    /*
+     * The OctoClock needs a full octoclock_eeprom_t so as to not erase
+     * what it currently has in the EEPROM, so store the relevant values
+     * from the user's input and send that instead.
+     */
+    BOOST_FOREACH(const std::string &key, oc_eeprom.keys()){
+        if(_oc_dict[oc].eeprom.has_key(key)) _oc_dict[oc].eeprom[key] = oc_eeprom[key];
+    }
+    _oc_dict[oc].eeprom.commit();
+}
+
+boost::uint32_t octoclock_impl::_get_fw_version(const std::string &oc){
+    octoclock_packet_t pkt_out;
+    pkt_out.sequence = _sequence++;
+    pkt_out.len = 0;
+    size_t len;
+
+    boost::uint8_t octoclock_data[udp_simple::mtu];
+    const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data);
+
+    UHD_OCTOCLOCK_SEND_AND_RECV(_oc_dict[oc].ctrl_xport, OCTOCLOCK_QUERY_CMD, pkt_out, len, octoclock_data);
+    if(UHD_OCTOCLOCK_PACKET_MATCHES(OCTOCLOCK_QUERY_ACK, pkt_out, pkt_in, len)){
+        return pkt_in->proto_ver;
+    }
+    else throw uhd::runtime_error("Failed to retrive firmware version from OctoClock.");
+}
+
+void octoclock_impl::_get_state(const std::string &oc){
+    octoclock_packet_t pkt_out;
+    pkt_out.sequence = _sequence++;
+    pkt_out.len = 0;
+    size_t len = 0;
+
+    boost::uint8_t octoclock_data[udp_simple::mtu];
+    const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data);
+
+    UHD_OCTOCLOCK_SEND_AND_RECV(_oc_dict[oc].ctrl_xport, SEND_STATE_CMD, pkt_out, len, octoclock_data);
+    if(UHD_OCTOCLOCK_PACKET_MATCHES(SEND_STATE_ACK, pkt_out, pkt_in, len)){
+        const octoclock_state_t *state = reinterpret_cast<const octoclock_state_t*>(pkt_in->data);
+        _oc_dict[oc].state = *state;
+    }
+    else throw uhd::runtime_error("Failed to retrieve state information from OctoClock.");
+}
+
+uhd::dict<ref_t, std::string> _ref_strings = boost::assign::map_list_of
+    (NO_REF, "none")
+    (INTERNAL, "internal")
+    (EXTERNAL, "external")
+;
+
+uhd::dict<switch_pos_t, std::string> _switch_pos_strings = boost::assign::map_list_of
+    (UP, "Prefer internal")
+    (DOWN, "Prefer external")
+;
+
+sensor_value_t octoclock_impl::_ext_ref_detected(const std::string &oc){
+    _get_state(oc);
+
+    return sensor_value_t("External reference detected", (_oc_dict[oc].state.external_detected > 0),
+                          "true", "false");
+}
+
+sensor_value_t octoclock_impl::_gps_detected(const std::string &oc){
+    //Don't check, this shouldn't change once device is turned on
+
+    return sensor_value_t("GPSDO detected", (_oc_dict[oc].state.gps_detected > 0),
+                          "true", "false");
+}
+
+sensor_value_t octoclock_impl::_which_ref(const std::string &oc){
+    _get_state(oc);
+
+    if(not _ref_strings.has_key(ref_t(_oc_dict[oc].state.which_ref))){
+        throw uhd::runtime_error("Invalid reference detected.");
+    }
+
+    return sensor_value_t("Using reference", _ref_strings[ref_t(_oc_dict[oc].state.which_ref)], "");
+}
+
+sensor_value_t octoclock_impl::_switch_pos(const std::string &oc){
+    _get_state(oc);
+
+    if(not _switch_pos_strings.has_key(switch_pos_t(_oc_dict[oc].state.switch_pos))){
+        throw uhd::runtime_error("Invalid switch position detected.");
+    }
+
+    return sensor_value_t("Switch position", _switch_pos_strings[switch_pos_t(_oc_dict[oc].state.switch_pos)], "");
+}
+
+boost::uint32_t octoclock_impl::_get_time(const std::string &oc){
+    if(_oc_dict[oc].state.gps_detected){
+        std::string time_str = _oc_dict[oc].gps->get_sensor("gps_time").value;
+        return boost::lexical_cast<boost::uint32_t>(time_str);
+    }
+    else throw uhd::runtime_error("This device cannot return a time.");
+}
+
+std::string octoclock_impl::_get_images_help_message(const std::string &addr){
+    const std::string image_name = "octoclock_r4_fw.bin";
+
+    //Check to see if image is in default location
+    std::string image_location;
+    try{
+        image_location = uhd::find_image_path(image_name);
+    }
+    catch(const std::exception &e){
+        return str(boost::format("Could not find %s in your images path.\n%s")
+                   % image_name
+                   % uhd::print_images_error());
+    }
+
+    //Get escape character
+    #ifdef UHD_PLATFORM_WIN32
+    const std::string ml = "^\n    ";
+    #else
+    const std::string ml = "\\\n    ";
+    #endif
+
+    //Get burner command
+    const std::string burner_path = (fs::path(uhd::get_pkg_path()) / "bin" / "octoclock_firmware_burner").string();
+    const std::string burner_cmd = str(boost::format("%s %s--addr=\"%s\"") % burner_path % ml % addr);
+    return str(boost::format("%s\n%s") % uhd::print_images_error() % burner_cmd);
+}
diff --git a/host/lib/usrp_clock/octoclock/octoclock_impl.hpp b/host/lib/usrp_clock/octoclock/octoclock_impl.hpp
new file mode 100644
index 000000000..ab45cd5f0
--- /dev/null
+++ b/host/lib/usrp_clock/octoclock/octoclock_impl.hpp
@@ -0,0 +1,80 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_OCTOCLOCK_IMPL_HPP
+#define INCLUDED_OCTOCLOCK_IMPL_HPP
+
+#include <boost/shared_ptr.hpp>
+#include <boost/thread.hpp>
+
+#include <uhd/device.hpp>
+#include <uhd/stream.hpp>
+#include <uhd/usrp/gps_ctrl.hpp>
+#include <uhd/usrp_clock/octoclock_eeprom.hpp>
+#include <uhd/types/device_addr.hpp>
+#include <uhd/types/dict.hpp>
+#include <uhd/types/sensors.hpp>
+
+#include "common.h"
+
+/*!
+ * OctoClock implementation guts
+ */
+class octoclock_impl : public uhd::device{
+public:
+    octoclock_impl(const uhd::device_addr_t &);
+    ~octoclock_impl(void) {};
+
+    uhd::rx_streamer::sptr get_rx_stream(const uhd::stream_args_t &args);
+
+    uhd::tx_streamer::sptr get_tx_stream(const uhd::stream_args_t &args);
+
+    bool recv_async_msg(uhd::async_metadata_t&, double);
+
+private:
+    struct oc_container_type{
+        uhd::usrp_clock::octoclock_eeprom_t eeprom;
+        octoclock_state_t state;
+        uhd::transport::udp_simple::sptr ctrl_xport;
+        uhd::transport::udp_simple::sptr gpsdo_xport;
+        uhd::gps_ctrl::sptr gps;
+    };
+    uhd::dict<std::string, oc_container_type> _oc_dict;
+    boost::uint32_t _sequence;
+
+    void _set_eeprom(const std::string &oc, const uhd::usrp_clock::octoclock_eeprom_t &oc_eeprom);
+
+    boost::uint32_t _get_fw_version(const std::string &oc);
+
+    void _get_state(const std::string &oc);
+
+    uhd::sensor_value_t _ext_ref_detected(const std::string &oc);
+
+    uhd::sensor_value_t _gps_detected(const std::string &oc);
+
+    uhd::sensor_value_t _which_ref(const std::string &oc);
+
+    uhd::sensor_value_t _switch_pos(const std::string &oc);
+
+    boost::uint32_t _get_time(const std::string &oc);
+
+    std::string _get_images_help_message(const std::string &addr);
+
+    boost::mutex _device_mutex;
+};
+
+#endif /* INCLUDED_OCTOCLOCK_IMPL_HPP */
diff --git a/host/lib/usrp_clock/octoclock/octoclock_uart.cpp b/host/lib/usrp_clock/octoclock/octoclock_uart.cpp
new file mode 100644
index 000000000..eb3f40d9c
--- /dev/null
+++ b/host/lib/usrp_clock/octoclock/octoclock_uart.cpp
@@ -0,0 +1,162 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <iostream>
+#include <string>
+#include <string.h>
+
+#include <boost/algorithm/string.hpp>
+#include <boost/asio.hpp>
+#include <boost/cstdint.hpp>
+#include <boost/format.hpp>
+#include <boost/thread/thread.hpp>
+
+#include <uhd/exception.hpp>
+#include <uhd/utils/byteswap.hpp>
+
+#include "common.h"
+#include "octoclock_uart.hpp"
+
+namespace asio = boost::asio;
+using namespace uhd::transport;
+
+#define NUM_WRAPS_EQUAL   (_state.num_wraps == _device_state.num_wraps)
+#define POS_EQUAL         (_state.pos == _device_state.pos)
+#define STATES_EQUAL      (NUM_WRAPS_EQUAL && POS_EQUAL)
+#define LOCAL_STATE_AHEAD (_state.num_wraps > _device_state.num_wraps || \
+                           (NUM_WRAPS_EQUAL && _state.pos > _device_state.pos))
+
+namespace uhd{
+    octoclock_uart_iface::octoclock_uart_iface(udp_simple::sptr udp): uart_iface(){
+        _udp = udp;
+        _state.num_wraps = 0;
+        _state.pos = 0;
+        _device_state.num_wraps = 0;
+        _device_state.pos = 0;
+        size_t len = 0;
+
+        //Get pool size from device
+        octoclock_packet_t pkt_out;
+        pkt_out.sequence = uhd::htonx<boost::uint16_t>(std::rand());
+        pkt_out.len = 0;
+
+        boost::uint8_t octoclock_data[udp_simple::mtu];
+        const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data);
+
+        UHD_OCTOCLOCK_SEND_AND_RECV(_udp, SEND_POOLSIZE_CMD, pkt_out, len, octoclock_data);
+        if(UHD_OCTOCLOCK_PACKET_MATCHES(SEND_POOLSIZE_ACK, pkt_out, pkt_in, len)){
+            _poolsize = pkt_in->poolsize;
+            _cache.resize(_poolsize);
+        }
+        else throw uhd::runtime_error("Failed to communicate with GPSDO.");
+    }
+
+    void octoclock_uart_iface::write_uart(const std::string &buf){
+        std::string to_send = boost::algorithm::replace_all_copy(buf, "\n", "\r\n");
+        size_t len = 0;
+
+        octoclock_packet_t pkt_out;
+        pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand());
+        pkt_out.len = to_send.size();
+        memcpy(pkt_out.data, to_send.c_str(), to_send.size());
+
+        boost::uint8_t octoclock_data[udp_simple::mtu];
+        const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data);
+
+        UHD_OCTOCLOCK_SEND_AND_RECV(_udp, HOST_SEND_TO_GPSDO_CMD, pkt_out, len, octoclock_data);
+        if(not UHD_OCTOCLOCK_PACKET_MATCHES(HOST_SEND_TO_GPSDO_ACK, pkt_out, pkt_in, len)){
+            throw uhd::runtime_error("Failed to send commands to GPSDO.");
+        }
+    }
+
+    std::string octoclock_uart_iface::read_uart(double timeout){
+        std::string result;
+
+        boost::system_time exit_time = boost::get_system_time() + boost::posix_time::milliseconds(long(timeout*1e3));
+
+        while(boost::get_system_time() < exit_time){
+            _update_cache();
+
+            for(char ch = _getchar(); ch != -1; ch = _getchar()){
+                if(ch == '\r') continue; //Skip carriage returns
+                _rxbuff += ch;
+
+                //If newline found, return string
+                if(ch == '\n'){
+                    result = _rxbuff;
+                    _rxbuff.clear();
+                    return result;
+                }
+            }
+            boost::this_thread::sleep(boost::posix_time::milliseconds(1));
+        }
+
+        return result;
+    }
+
+    void octoclock_uart_iface::_update_cache(){
+        octoclock_packet_t pkt_out;
+        pkt_out.len = 0;
+        size_t len = 0;
+
+        boost::uint8_t octoclock_data[udp_simple::mtu];
+        const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data);
+
+        if(STATES_EQUAL or LOCAL_STATE_AHEAD){
+            pkt_out.sequence++;
+            UHD_OCTOCLOCK_SEND_AND_RECV(_udp, SEND_GPSDO_CACHE_CMD, pkt_out, len, octoclock_data);
+            if(UHD_OCTOCLOCK_PACKET_MATCHES(SEND_GPSDO_CACHE_ACK, pkt_out, pkt_in, len)){
+                memcpy(&_cache[0], pkt_in->data, _poolsize);
+                _device_state = pkt_in->state;
+            }
+
+            boost::uint8_t delta_wraps = (_device_state.num_wraps - _state.num_wraps);
+            if(delta_wraps > 1 or
+               ((delta_wraps == 1) and (_device_state.pos >= _state.pos))){
+
+                _state.pos = (_device_state.pos+1) % _poolsize;
+                _state.num_wraps = (_device_state.num_wraps-1);
+
+                while((_cache[_state.pos] != '\n') and (_state.pos != _device_state.pos)){
+                    _state.pos = (_state.pos+1) % _poolsize;
+                    //We may have wrapped around locally
+                    if(_state.pos == 0) _state.num_wraps++;
+                }
+                _state.pos = (_state.pos+1) % _poolsize;
+                //We may have wrapped around locally
+                if(_state.pos == 0) _state.num_wraps++;
+            }
+        }
+    }
+
+    char octoclock_uart_iface::_getchar(){
+        if(LOCAL_STATE_AHEAD){
+            return -1;
+        }
+
+        char ch = _cache[_state.pos];
+        _state.pos = ((_state.pos+1) % _poolsize);
+        //We may have wrapped around locally
+        if(_state.pos == 0) _state.num_wraps++;
+
+        return ch;
+    }
+
+    uart_iface::sptr octoclock_make_uart_iface(udp_simple::sptr udp){
+        return uart_iface::sptr(new octoclock_uart_iface(udp));
+    }
+}
diff --git a/host/lib/usrp_clock/octoclock/octoclock_uart.hpp b/host/lib/usrp_clock/octoclock/octoclock_uart.hpp
new file mode 100644
index 000000000..05d1bb121
--- /dev/null
+++ b/host/lib/usrp_clock/octoclock/octoclock_uart.hpp
@@ -0,0 +1,57 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the uart_ifaceied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_OCTOCLOCK_UART_HPP
+#define INCLUDED_OCTOCLOCK_UART_HPP
+
+#include <vector>
+
+#include <uhd/transport/udp_simple.hpp>
+#include <uhd/types/serial.hpp>
+
+/*!
+ * The OctoClock doesn't take UART input per se but reads a specific
+ * packet type and sends the string from there through its own serial
+ * functions.
+ */
+namespace uhd{
+class octoclock_uart_iface : public uhd::uart_iface{
+public:
+    octoclock_uart_iface(uhd::transport::udp_simple::sptr udp);
+    ~octoclock_uart_iface(void) {};
+
+    void write_uart(const std::string &buf);
+    std::string read_uart(double timeout);
+
+private:
+    uhd::transport::udp_simple::sptr _udp;
+
+    boost::uint16_t _poolsize;
+    gpsdo_cache_state_t _state;
+    gpsdo_cache_state_t _device_state;
+    std::vector<boost::uint8_t> _cache;
+    std::string _rxbuff;
+
+    void _update_cache();
+    char _getchar();
+};
+
+uart_iface::sptr octoclock_make_uart_iface(uhd::transport::udp_simple::sptr udp);
+
+}
+
+#endif /* INCLUDED_OCTOCLOCK_UART_HPP */