diff options
Diffstat (limited to 'host/lib')
43 files changed, 1798 insertions, 432 deletions
diff --git a/host/lib/gain_group.cpp b/host/lib/gain_group.cpp new file mode 100644 index 000000000..1be09dee2 --- /dev/null +++ b/host/lib/gain_group.cpp @@ -0,0 +1,149 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <uhd/utils/gain_group.hpp> +#include <uhd/types/dict.hpp> +#include <uhd/utils/algorithm.hpp> +#include <uhd/utils/assert.hpp> +#include <boost/foreach.hpp> +#include <boost/bind.hpp> +#include <algorithm> +#include <vector> +#include <iostream> + +using namespace uhd; + +static const bool verbose = false; + +static bool compare_by_step_size( + const size_t &rhs, const size_t &lhs, std::vector<gain_fcns_t> &fcns +){ + return fcns.at(rhs).get_range().step > fcns.at(lhs).get_range().step; +} + +/*********************************************************************** + * gain group implementation + **********************************************************************/ +class gain_group_impl : public gain_group{ +public: + gain_group_impl(void){ + /*NOP*/ + } + + gain_range_t get_range(void){ + float overall_min = 0, overall_max = 0, overall_step = 0; + BOOST_FOREACH(const gain_fcns_t &fcns, get_all_fcns()){ + const gain_range_t range = fcns.get_range(); + overall_min += range.min; + overall_max += range.max; + //the overall step is the min (zero is invalid, first run) + if (overall_step == 0) overall_step = range.step; + overall_step = std::min(overall_step, range.step); + } + return gain_range_t(overall_min, overall_max, overall_step); + } + + float get_value(void){ + float overall_gain = 0; + BOOST_FOREACH(const gain_fcns_t &fcns, get_all_fcns()){ + overall_gain += fcns.get_value(); + } + return overall_gain; + } + + void set_value(float gain){ + std::vector<gain_fcns_t> all_fcns = get_all_fcns(); + if (all_fcns.size() == 0) return; //nothing to set! + + //get the max step size among the gains + float max_step = 0; + BOOST_FOREACH(const gain_fcns_t &fcns, all_fcns){ + max_step = std::max(max_step, fcns.get_range().step); + } + + //create gain bucket to distribute power + std::vector<float> gain_bucket; + + //distribute power according to priority (round to max step) + float gain_left_to_distribute = gain; + BOOST_FOREACH(const gain_fcns_t &fcns, all_fcns){ + const gain_range_t range = fcns.get_range(); + gain_bucket.push_back( + max_step*int(std::clip(gain_left_to_distribute, range.min, range.max)/max_step) + ); + gain_left_to_distribute -= gain_bucket.back(); + } + + //get a list of indexes sorted by step size large to small + std::vector<size_t> indexes_step_size_dec; + for (size_t i = 0; i < all_fcns.size(); i++){ + indexes_step_size_dec.push_back(i); + } + std::sort( + indexes_step_size_dec.begin(), indexes_step_size_dec.end(), + boost::bind(&compare_by_step_size, _1, _2, all_fcns) + ); + UHD_ASSERT_THROW( + all_fcns.at(indexes_step_size_dec.front()).get_range().step >= + all_fcns.at(indexes_step_size_dec.back()).get_range().step + ); + + //distribute the remainder (less than max step) + //fill in the largest step sizes first that are less than the remainder + BOOST_FOREACH(size_t i, indexes_step_size_dec){ + const gain_range_t range = all_fcns.at(i).get_range(); + float additional_gain = range.step*int( + std::clip(gain_bucket.at(i) + gain_left_to_distribute, range.min, range.max + )/range.step) - gain_bucket.at(i); + gain_bucket.at(i) += additional_gain; + gain_left_to_distribute -= additional_gain; + } + if (verbose) std::cout << "gain_left_to_distribute " << gain_left_to_distribute << std::endl; + + //now write the bucket out to the individual gain values + for (size_t i = 0; i < gain_bucket.size(); i++){ + if (verbose) std::cout << gain_bucket.at(i) << std::endl; + all_fcns.at(i).set_value(gain_bucket.at(i)); + } + } + + void register_fcns( + const gain_fcns_t &gain_fcns, size_t priority + ){ + _registry[priority].push_back(gain_fcns); + } + +private: + //! get the gain function sets in order (highest priority first) + std::vector<gain_fcns_t> get_all_fcns(void){ + std::vector<gain_fcns_t> all_fcns; + BOOST_FOREACH(ssize_t key, std::sorted(_registry.keys())){ + const std::vector<gain_fcns_t> &fcns = _registry[key]; + all_fcns.insert(all_fcns.begin(), fcns.begin(), fcns.end()); + } + return all_fcns; + } + + uhd::dict<size_t, std::vector<gain_fcns_t> > _registry; +}; + +/*********************************************************************** + * gain group factory function + **********************************************************************/ +gain_group::sptr gain_group::make(void){ + return sptr(new gain_group_impl()); +} diff --git a/host/lib/ic_reg_maps/CMakeLists.txt b/host/lib/ic_reg_maps/CMakeLists.txt index a328fa033..ac051b843 100644 --- a/host/lib/ic_reg_maps/CMakeLists.txt +++ b/host/lib/ic_reg_maps/CMakeLists.txt @@ -80,6 +80,11 @@ LIBUHD_PYTHON_GEN_SOURCE( ) LIBUHD_PYTHON_GEN_SOURCE( + ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ads62p44_regs.py + ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ads62p44_regs.hpp + ) + +LIBUHD_PYTHON_GEN_SOURCE( ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_tuner_4937di5_regs.py ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/tuner_4937di5_regs.hpp ) diff --git a/host/lib/ic_reg_maps/gen_ads62p44_regs.py b/host/lib/ic_reg_maps/gen_ads62p44_regs.py new file mode 100755 index 000000000..f0a84d940 --- /dev/null +++ b/host/lib/ic_reg_maps/gen_ads62p44_regs.py @@ -0,0 +1,124 @@ +#!/usr/bin/env python +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +######################################################################## +# Template for raw text data describing registers +# name addr[bit range inclusive] default optional enums +######################################################################## +REGS_TMPL="""\ +######################################################################## +## address 0 +######################################################################## +reset 0[1] 0 +serial_readout 0[0] 0 +######################################################################## +## address 16 +######################################################################## +clkout_strength 16[6:7] 0 weaker=1, default=0, stronger=3 +######################################################################## +## address 17 +######################################################################## +dataout_strength 17[0:1] 0 weaker=1, default=0, stronger=3, maximum=2 +lvds_current 17[2:3] 0 3_5ma, 2_5ma, 4_5ma, 1_75ma +lvds_current_double 17[4:5] 0 default, dblclk, dbldataclock +######################################################################## +## address 18 +######################################################################## +lvds_clk_term 18[0:2] 0 none, 300, 180, 110, 150, 100, 81, 60 +lvds_data_term 18[3:5] 0 none, 300, 180, 110, 150, 100, 81, 60 +######################################################################## +## address 19 +######################################################################## +offset_freeze 19[4] 0 +######################################################################## +## address 20 +######################################################################## +power_down 20[0:2] 0 normal, a_dis, b_dis, ab_dis, global_pd, a_sby, b_sby, mux +ref_select 20[3] 0 internal, external +coarse_gain 20[4] 0 0db, 3_5db +output_interface 20[5] 0 cmos, lvds +override 20[7] 0 +######################################################################## +## address 22 +######################################################################## +test_patterns 22[0:2] 0 normal, zeros, ones, toggle, ramp, custom +lvds_bytewise 22[3] 0 +data_format 22[4] 0 twos_complement, binary +######################################################################## +## address 23 +######################################################################## +fine_gain 23[0:3] 0 +######################################################################## +## address 24 and 25 +######################################################################## +custom_low 24[0:7] 0 +custom_high 25[0:5] 0 +######################################################################## +## address 26 +######################################################################## +gain_correction 26[0:3] 0 +offset_tc 26[4:6] 0 1_1s, 0_55s, 0_27s, 0_13s, 2_15s, 4_3s +low_latency 26[7] 0 +######################################################################## +## address 27 +######################################################################## +decimation 27[0:2] 0 decimate_2, decimate_4, decimate_1, decimate_8 +odd_tap_enable 27[3] 0 +filter_enable 27[4] 0 +filter_coeff_sel 27[5] 0 predefined, userdefined +offset_enable 27[7] 0 +######################################################################## +## address 29 +######################################################################## +decimation_filter_bands 29[0:1] 0 +""" + +######################################################################## +# Template for methods in the body of the struct +######################################################################## +BODY_TMPL="""\ +boost::uint8_t get_reg(boost::uint8_t addr){ + boost::uint8_t reg = 0; + switch(addr){ + #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) + case $addr: + #for $reg in filter(lambda r: r.get_addr() == addr, $regs) + reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); + #end for + break; + #end for + } + return reg; +} + +boost::uint16_t get_write_reg(boost::uint8_t addr){ + return (boost::uint16_t(addr) << 8) | get_reg(addr); +} + +boost::uint16_t get_read_reg(boost::uint8_t addr){ + return (boost::uint16_t(addr) << 8) | (1 << 7); +} +""" + +if __name__ == '__main__': + import common; common.generate( + name='ads62p44_regs', + regs_tmpl=REGS_TMPL, + body_tmpl=BODY_TMPL, + file=__file__, + ) diff --git a/host/lib/transport/udp_simple.cpp b/host/lib/transport/udp_simple.cpp index 89750f99d..6799ac7b2 100644 --- a/host/lib/transport/udp_simple.cpp +++ b/host/lib/transport/udp_simple.cpp @@ -27,23 +27,38 @@ using namespace uhd::transport; * Helper Functions **********************************************************************/ /*! - * A receive timeout for a socket: - * - * It seems that asio cannot have timeouts with synchronous io. - * However, we can implement a polling loop that will timeout. - * This is okay bacause this is the slow-path implementation. - * + * Wait for available data or timeout. * \param socket the asio socket - * \param timeout_ms the timeout in milliseconds + * \param timeout the timeout in seconds + * \return false for timeout, true for data */ -static void reasonable_recv_timeout( - boost::asio::ip::udp::socket &socket, size_t timeout_ms +static bool wait_available( + boost::asio::ip::udp::socket &socket, double timeout ){ - boost::asio::deadline_timer timer(socket.get_io_service()); - timer.expires_from_now(boost::posix_time::milliseconds(timeout_ms)); - while (not (socket.available() or timer.expires_from_now().is_negative())){ + #if defined(UHD_PLATFORM_LINUX) || defined(UHD_PLATFORM_WIN32) + + //setup timeval for timeout + timeval tv; + tv.tv_sec = 0; + tv.tv_usec = long(timeout*1e6); + + //setup rset for timeout + fd_set rset; + FD_ZERO(&rset); + FD_SET(socket.native(), &rset); + + return ::select(socket.native()+1, &rset, NULL, NULL, &tv) > 0; + + #else /*defined(UHD_PLATFORM_LINUX) || defined(UHD_PLATFORM_WIN32)*/ + + //FIXME: why does select fail on macintosh? + for (size_t i = 0; i < size_t(timeout*1e3); i++){ + if (socket.available()) return true; boost::this_thread::sleep(boost::posix_time::milliseconds(1)); } + return false; + + #endif /*defined(UHD_PLATFORM_LINUX) || defined(UHD_PLATFORM_WIN32)*/ } /*********************************************************************** @@ -57,7 +72,7 @@ public: //send/recv size_t send(const boost::asio::const_buffer &); - size_t recv(const boost::asio::mutable_buffer &, size_t); + size_t recv(const boost::asio::mutable_buffer &, double); private: boost::asio::ip::udp::socket *_socket; @@ -86,9 +101,8 @@ size_t udp_connected_impl::send(const boost::asio::const_buffer &buff){ return _socket->send(boost::asio::buffer(buff)); } -size_t udp_connected_impl::recv(const boost::asio::mutable_buffer &buff, size_t timeout_ms){ - reasonable_recv_timeout(*_socket, timeout_ms); - if (not _socket->available()) return 0; +size_t udp_connected_impl::recv(const boost::asio::mutable_buffer &buff, double timeout){ + if (not wait_available(*_socket, timeout)) return 0; return _socket->receive(boost::asio::buffer(buff)); } @@ -103,7 +117,7 @@ public: //send/recv size_t send(const boost::asio::const_buffer &); - size_t recv(const boost::asio::mutable_buffer &, size_t); + size_t recv(const boost::asio::mutable_buffer &, double); private: boost::asio::ip::udp::socket *_socket; @@ -137,9 +151,8 @@ size_t udp_broadcast_impl::send(const boost::asio::const_buffer &buff){ return _socket->send_to(boost::asio::buffer(buff), _receiver_endpoint); } -size_t udp_broadcast_impl::recv(const boost::asio::mutable_buffer &buff, size_t timeout_ms){ - reasonable_recv_timeout(*_socket, timeout_ms); - if (not _socket->available()) return 0; +size_t udp_broadcast_impl::recv(const boost::asio::mutable_buffer &buff, double timeout){ + if (not wait_available(*_socket, timeout)) return 0; boost::asio::ip::udp::endpoint sender_endpoint; return _socket->receive_from(boost::asio::buffer(buff), sender_endpoint); } diff --git a/host/lib/transport/udp_zero_copy_asio.cpp b/host/lib/transport/udp_zero_copy_asio.cpp index ed29864e9..c758fa894 100644 --- a/host/lib/transport/udp_zero_copy_asio.cpp +++ b/host/lib/transport/udp_zero_copy_asio.cpp @@ -59,16 +59,23 @@ static const size_t DEFAULT_NUM_RECV_FRAMES = 32; #else static const size_t DEFAULT_NUM_RECV_FRAMES = MIN_RECV_SOCK_BUFF_SIZE/udp_simple::mtu; #endif + //The non-async send only ever requires a single frame //because the buffer will be committed before a new get. #ifdef USE_ASIO_ASYNC_SEND static const size_t DEFAULT_NUM_SEND_FRAMES = 32; #else -static const size_t DEFAULT_NUM_SEND_FRAMES = MIN_SEND_SOCK_BUFF_SIZE/udp_simple::mtu;; +static const size_t DEFAULT_NUM_SEND_FRAMES = MIN_SEND_SOCK_BUFF_SIZE/udp_simple::mtu; #endif -//a single concurrent thread for io_service seems to be the fastest +//The number of service threads to spawn for async ASIO: +//A single concurrent thread for io_service seems to be the fastest. +//Threads are disabled when no async implementations are enabled. +#if defined(USE_ASIO_ASYNC_RECV) || defined(USE_ASIO_ASYNC_SEND) static const size_t CONCURRENCY_HINT = 1; +#else +static const size_t CONCURRENCY_HINT = 0; +#endif /*********************************************************************** * Zero Copy UDP implementation with ASIO: @@ -86,11 +93,12 @@ public: const std::string &port, const device_addr_t &hints ): - _io_service(hints.cast<size_t>("concurrency_hint", CONCURRENCY_HINT)), _recv_frame_size(size_t(hints.cast<double>("recv_frame_size", udp_simple::mtu))), _num_recv_frames(size_t(hints.cast<double>("num_recv_frames", DEFAULT_NUM_RECV_FRAMES))), _send_frame_size(size_t(hints.cast<double>("send_frame_size", udp_simple::mtu))), - _num_send_frames(size_t(hints.cast<double>("num_send_frames", DEFAULT_NUM_SEND_FRAMES))) + _num_send_frames(size_t(hints.cast<double>("num_send_frames", DEFAULT_NUM_SEND_FRAMES))), + _concurrency_hint(hints.cast<size_t>("concurrency_hint", CONCURRENCY_HINT)), + _io_service(_concurrency_hint) { //std::cout << boost::format("Creating udp transport for %s %s") % addr % port << std::endl; @@ -129,7 +137,7 @@ public: //spawn the service threads that will run the io service _work = new asio::io_service::work(_io_service); //new work to delete later - for (size_t i = 0; i < CONCURRENCY_HINT; i++) _thread_group.create_thread( + for (size_t i = 0; i < _concurrency_hint; i++) _thread_group.create_thread( boost::bind(&udp_zero_copy_asio_impl::service, this) ); } @@ -292,12 +300,6 @@ public: size_t get_send_frame_size(void) const {return _send_frame_size;} private: - //asio guts -> socket and service - asio::ip::udp::socket *_socket; - asio::io_service _io_service; - asio::io_service::work *_work; - int _sock_fd; - //memory management -> buffers and fifos boost::thread_group _thread_group; boost::shared_array<char> _send_buffer, _recv_buffer; @@ -305,6 +307,13 @@ private: pending_buffs_type::sptr _pending_recv_buffs, _pending_send_buffs; const size_t _recv_frame_size, _num_recv_frames; const size_t _send_frame_size, _num_send_frames; + + //asio guts -> socket and service + size_t _concurrency_hint; + asio::io_service _io_service; + asio::ip::udp::socket *_socket; + asio::io_service::work *_work; + int _sock_fd; }; /*********************************************************************** diff --git a/host/lib/transport/vrt_packet_handler.hpp b/host/lib/transport/vrt_packet_handler.hpp index 939517411..278bcfeaa 100644 --- a/host/lib/transport/vrt_packet_handler.hpp +++ b/host/lib/transport/vrt_packet_handler.hpp @@ -318,7 +318,7 @@ template <typename T> UHD_INLINE T get_context_code( ){ //load the rest of the if_packet_info in here if_packet_info.num_payload_words32 = (num_samps*chans_per_otw_buff*otw_type.get_sample_size())/sizeof(boost::uint32_t); - if_packet_info.packet_count = state.next_packet_seq++; + if_packet_info.packet_count = state.next_packet_seq; //get send buffers for each channel managed_send_buffs_t send_buffs(buffs.size()/chans_per_otw_buff); @@ -345,6 +345,7 @@ template <typename T> UHD_INLINE T get_context_code( size_t num_bytes_total = (vrt_header_offset_words32+if_packet_info.num_packet_words32)*sizeof(boost::uint32_t); send_buffs[i]->commit(num_bytes_total); } + state.next_packet_seq++; //increment sequence after commits return num_samps; } @@ -387,10 +388,19 @@ template <typename T> UHD_INLINE T get_context_code( if_packet_info.sob = metadata.start_of_burst; if_packet_info.eob = metadata.end_of_burst; + //TODO remove this code when sample counts of zero are supported by hardware + std::vector<const void *> buffs_(buffs); + size_t total_num_samps_(total_num_samps); + if (total_num_samps == 0){ + static const boost::uint64_t zeros = 0; //max size of a host sample + buffs_ = std::vector<const void *>(buffs.size(), &zeros); + total_num_samps_ = 1; + } + return _send1( state, - buffs, 0, - std::min(total_num_samps, max_samples_per_packet), + buffs_, 0, + std::min(total_num_samps_, max_samples_per_packet), if_packet_info, io_type, otw_type, vrt_packer, diff --git a/host/lib/types.cpp b/host/lib/types.cpp index e5e6a2512..bea20a4aa 100644 --- a/host/lib/types.cpp +++ b/host/lib/types.cpp @@ -16,12 +16,12 @@ // #include <uhd/utils/assert.hpp> -#include <uhd/types/ranges.hpp> #include <uhd/types/tune_request.hpp> #include <uhd/types/tune_result.hpp> #include <uhd/types/clock_config.hpp> #include <uhd/types/stream_cmd.hpp> #include <uhd/types/metadata.hpp> +#include <uhd/types/ranges.hpp> #include <uhd/types/time_spec.hpp> #include <uhd/types/device_addr.hpp> #include <uhd/types/mac_addr.hpp> @@ -41,22 +41,10 @@ using namespace uhd; /*********************************************************************** - * ranges + * ranges template instantiation **********************************************************************/ -gain_range_t::gain_range_t(float min, float max, float step): - min(min), - max(max), - step(step) -{ - /* NOP */ -} - -freq_range_t::freq_range_t(double min, double max): - min(min), - max(max) -{ - /* NOP */ -} +template struct uhd::meta_range_t<float>; +template struct uhd::meta_range_t<double>; /*********************************************************************** * tune request diff --git a/host/lib/usrp/README b/host/lib/usrp/README new file mode 100644 index 000000000..c125d1dad --- /dev/null +++ b/host/lib/usrp/README @@ -0,0 +1,12 @@ +######################################################################## +# lib USRP directories: +######################################################################## + +dboard: + Daughterboard implementation code for all USRP daughterboards + +usrp1: + Implementation code for the USB-based USRP Classic motherboard. + +usrp2: + Implementation code for USRP2 and USRP-N2XX. diff --git a/host/lib/usrp/dboard/db_basic_and_lf.cpp b/host/lib/usrp/dboard/db_basic_and_lf.cpp index f03dd43d1..73f894374 100644 --- a/host/lib/usrp/dboard/db_basic_and_lf.cpp +++ b/host/lib/usrp/dboard/db_basic_and_lf.cpp @@ -106,6 +106,11 @@ UHD_STATIC_BLOCK(reg_basic_and_lf_dboards){ **********************************************************************/ basic_rx::basic_rx(ctor_args_t args, double max_freq) : rx_dboard_base(args){ _max_freq = max_freq; + + //set GPIOs to output 0x0000 to decrease noise pickup + this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, 0x0000); + this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, 0xFFFF); + this->get_iface()->write_gpio(dboard_iface::UNIT_RX, 0x0000); } basic_rx::~basic_rx(void){ diff --git a/host/lib/usrp/dboard/db_dbsrx.cpp b/host/lib/usrp/dboard/db_dbsrx.cpp index 85251bdf9..7edc1822c 100644 --- a/host/lib/usrp/dboard/db_dbsrx.cpp +++ b/host/lib/usrp/dboard/db_dbsrx.cpp @@ -212,10 +212,10 @@ dbsrx::dbsrx(ctor_args_t args) : rx_dboard_base(args){ //set defaults for LO, gains, and filter bandwidth _bandwidth = 33e6; - set_lo_freq(dbsrx_freq_range.min); + set_lo_freq(dbsrx_freq_range.start()); BOOST_FOREACH(const std::string &name, dbsrx_gain_ranges.keys()){ - set_gain(dbsrx_gain_ranges[name].min, name); + set_gain(dbsrx_gain_ranges[name].start(), name); } set_bandwidth(33e6); // default bandwidth from datasheet @@ -229,7 +229,7 @@ dbsrx::~dbsrx(void){ * Tuning **********************************************************************/ void dbsrx::set_lo_freq(double target_freq){ - target_freq = std::clip(target_freq, dbsrx_freq_range.min, dbsrx_freq_range.max); + target_freq = dbsrx_freq_range.clip(target_freq); double actual_freq=0.0, pfd_freq=0.0, ref_clock=0.0; int R=0, N=0, r=0, m=0; @@ -261,7 +261,7 @@ void dbsrx::set_lo_freq(double target_freq){ pfd_freq = ref_clock / R; //constrain the PFD frequency to specified range - if ((pfd_freq < dbsrx_pfd_freq_range.min) or (pfd_freq > dbsrx_pfd_freq_range.max)) continue; + if ((pfd_freq < dbsrx_pfd_freq_range.start()) or (pfd_freq > dbsrx_pfd_freq_range.stop())) continue; //compute N N = int(std::floor(target_freq/pfd_freq)); @@ -278,7 +278,7 @@ void dbsrx::set_lo_freq(double target_freq){ //Assert because we failed to find a suitable combination of ref_clock, R and N UHD_ASSERT_THROW(ref_clock <= 27.0e6 and ref_clock >= 0.0); UHD_ASSERT_THROW(ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6); - UHD_ASSERT_THROW((pfd_freq >= dbsrx_pfd_freq_range.min) and (pfd_freq <= dbsrx_pfd_freq_range.max)); + UHD_ASSERT_THROW((pfd_freq >= dbsrx_pfd_freq_range.start()) and (pfd_freq <= dbsrx_pfd_freq_range.stop())); UHD_ASSERT_THROW((N >= 256) and (N <= 32768)); if(dbsrx_debug) std::cerr << boost::format( @@ -374,6 +374,9 @@ void dbsrx::set_lo_freq(double target_freq){ //update vco selection and check vtune send_reg(0x2, 0x2); read_reg(0x0, 0x0); + + //allow for setup time before checking condition again + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); } if(dbsrx_debug) std::cerr << boost::format( @@ -417,7 +420,7 @@ void dbsrx::set_lo_freq(double target_freq){ */ static int gain_to_gc2_vga_reg(float &gain){ int reg = 0; - gain = std::clip<float>(float(boost::math::iround(gain)), dbsrx_gain_ranges["GC2"].min, dbsrx_gain_ranges["GC2"].max); + gain = dbsrx_gain_ranges["GC2"].clip(gain); // Half dB steps from 0-5dB, 1dB steps from 5-24dB if (gain < 5) { @@ -443,11 +446,11 @@ static int gain_to_gc2_vga_reg(float &gain){ */ static float gain_to_gc1_rfvga_dac(float &gain){ //clip the input - gain = std::clip<float>(gain, dbsrx_gain_ranges["GC1"].min, dbsrx_gain_ranges["GC1"].max); + gain = dbsrx_gain_ranges["GC1"].clip(gain); //voltage level constants static const float max_volts = float(1.2), min_volts = float(2.7); - static const float slope = (max_volts-min_volts)/dbsrx_gain_ranges["GC1"].max; + static const float slope = (max_volts-min_volts)/dbsrx_gain_ranges["GC1"].stop(); //calculate the voltage for the aux dac float dac_volts = gain*slope + min_volts; diff --git a/host/lib/usrp/dboard/db_dbsrx2.cpp b/host/lib/usrp/dboard/db_dbsrx2.cpp index 5a65e6123..cdafd6a78 100644 --- a/host/lib/usrp/dboard/db_dbsrx2.cpp +++ b/host/lib/usrp/dboard/db_dbsrx2.cpp @@ -195,15 +195,15 @@ dbsrx2::dbsrx2(ctor_args_t args) : rx_dboard_base(args){ //for (boost::uint8_t addr=0; addr<=12; addr++) this->send_reg(addr, addr); //set defaults for LO, gains - set_lo_freq(dbsrx2_freq_range.min); + set_lo_freq(dbsrx2_freq_range.start()); BOOST_FOREACH(const std::string &name, dbsrx2_gain_ranges.keys()){ - set_gain(dbsrx2_gain_ranges[name].min, name); + set_gain(dbsrx2_gain_ranges[name].start(), name); } set_bandwidth(40e6); // default bandwidth from datasheet get_locked(); - _max2112_write_regs.bbg = boost::math::iround(std::clip<float>(0, dbsrx2_gain_ranges["BBG"].min, dbsrx2_gain_ranges["BBG"].max)); + _max2112_write_regs.bbg = boost::math::iround(dbsrx2_gain_ranges["BBG"].start()); send_reg(0x9, 0x9); } @@ -270,7 +270,7 @@ void dbsrx2::set_lo_freq(double target_freq){ * \return 4 bit the register value */ static int gain_to_bbg_vga_reg(float &gain){ - int reg = boost::math::iround(std::clip<float>(gain, dbsrx2_gain_ranges["BBG"].min, dbsrx2_gain_ranges["BBG"].max)); + int reg = boost::math::iround(dbsrx2_gain_ranges["BBG"].clip(gain)); gain = float(reg); @@ -290,11 +290,11 @@ static int gain_to_bbg_vga_reg(float &gain){ */ static float gain_to_gc1_rfvga_dac(float &gain){ //clip the input - gain = std::clip<float>(gain, dbsrx2_gain_ranges["GC1"].min, dbsrx2_gain_ranges["GC1"].max); + gain = dbsrx2_gain_ranges["GC1"].clip(gain); //voltage level constants static const float max_volts = float(0.5), min_volts = float(2.7); - static const float slope = (max_volts-min_volts)/dbsrx2_gain_ranges["GC1"].max; + static const float slope = (max_volts-min_volts)/dbsrx2_gain_ranges["GC1"].stop(); //calculate the voltage for the aux dac float dac_volts = gain*slope + min_volts; diff --git a/host/lib/usrp/dboard/db_rfx.cpp b/host/lib/usrp/dboard/db_rfx.cpp index 152198c3a..74a9fb37b 100644 --- a/host/lib/usrp/dboard/db_rfx.cpp +++ b/host/lib/usrp/dboard/db_rfx.cpp @@ -93,9 +93,9 @@ public: void tx_set(const wax::obj &key, const wax::obj &val); private: - freq_range_t _freq_range; - uhd::dict<std::string, gain_range_t> _rx_gain_ranges; - uhd::dict<dboard_iface::unit_t, bool> _div2; + const freq_range_t _freq_range; + const uhd::dict<std::string, gain_range_t> _rx_gain_ranges; + const uhd::dict<dboard_iface::unit_t, bool> _div2; double _rx_lo_freq, _tx_lo_freq; std::string _rx_ant; uhd::dict<std::string, float> _rx_gains; @@ -168,19 +168,17 @@ rfx_xcvr::rfx_xcvr( ctor_args_t args, const freq_range_t &freq_range, bool rx_div2, bool tx_div2 -) : xcvr_dboard_base(args){ - _freq_range = freq_range; - _div2[dboard_iface::UNIT_RX] = rx_div2; - _div2[dboard_iface::UNIT_TX] = tx_div2; - - if(this->get_rx_id() == 0x0024) { //RFX400 - _rx_gain_ranges = rfx400_rx_gain_ranges; - } - else { - _rx_gain_ranges = rfx_rx_gain_ranges; - } - - +): + xcvr_dboard_base(args), + _freq_range(freq_range), + _rx_gain_ranges((get_rx_id() == 0x0024)? + rfx400_rx_gain_ranges : rfx_rx_gain_ranges + ), + _div2(map_list_of + (dboard_iface::UNIT_RX, rx_div2) + (dboard_iface::UNIT_TX, tx_div2) + ) +{ //enable the clocks that we need this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true); this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true); @@ -204,12 +202,12 @@ rfx_xcvr::rfx_xcvr( this->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, POWER_UP | ANT_RX2| MIXER_ENB); //set some default values - set_rx_lo_freq((_freq_range.min + _freq_range.max)/2.0); - set_tx_lo_freq((_freq_range.min + _freq_range.max)/2.0); + set_rx_lo_freq((_freq_range.start() + _freq_range.stop())/2.0); + set_tx_lo_freq((_freq_range.start() + _freq_range.stop())/2.0); set_rx_ant("RX2"); BOOST_FOREACH(const std::string &name, _rx_gain_ranges.keys()){ - set_rx_gain(_rx_gain_ranges[name].min, name); + set_rx_gain(_rx_gain_ranges[name].start(), name); } } @@ -265,7 +263,7 @@ void rfx_xcvr::set_rx_gain(float gain, const std::string &name){ assert_has(_rx_gain_ranges.keys(), name, "rfx rx gain name"); if(name == "PGA0"){ float dac_volts = rx_pga0_gain_to_dac_volts(gain, - (_rx_gain_ranges["PGA0"].max - _rx_gain_ranges["PGA0"].min)); + (_rx_gain_ranges["PGA0"].stop() - _rx_gain_ranges["PGA0"].start())); _rx_gains[name] = gain; //write the new voltage to the aux dac @@ -294,7 +292,7 @@ double rfx_xcvr::set_lo_freq( ) % (target_freq/1e6) << std::endl; //clip the input - target_freq = std::clip(target_freq, _freq_range.min, _freq_range.max); + target_freq = _freq_range.clip(target_freq); if (_div2[unit]) target_freq *= 2; //map prescalers to the register enums diff --git a/host/lib/usrp/dboard/db_tvrx.cpp b/host/lib/usrp/dboard/db_tvrx.cpp index 2873e3d54..17fdad74a 100644 --- a/host/lib/usrp/dboard/db_tvrx.cpp +++ b/host/lib/usrp/dboard/db_tvrx.cpp @@ -200,12 +200,12 @@ tvrx::tvrx(ctor_args_t args) : rx_dboard_base(args){ //send initial register settings if necessary //set default freq - _lo_freq = tvrx_freq_range.min + tvrx_if_freq; //init _lo_freq to a sane default - set_freq(tvrx_freq_range.min); + _lo_freq = tvrx_freq_range.start() + tvrx_if_freq; //init _lo_freq to a sane default + set_freq(tvrx_freq_range.start()); //set default gains BOOST_FOREACH(const std::string &name, get_tvrx_gain_ranges().keys()){ - set_gain(get_tvrx_gain_ranges()[name].min, name); + set_gain(get_tvrx_gain_ranges()[name].start(), name); } } @@ -219,7 +219,7 @@ tvrx::~tvrx(void){ static std::string get_band(double freq) { BOOST_FOREACH(const std::string &band, tvrx_freq_ranges.keys()) { - if(freq >= tvrx_freq_ranges[band].min && freq <= tvrx_freq_ranges[band].max){ + if(freq >= tvrx_freq_ranges[band].start() && freq <= tvrx_freq_ranges[band].stop()){ if(tvrx_debug) std::cout << "Band: " << band << std::endl; return band; } @@ -277,7 +277,7 @@ static double gain_interp(double gain, boost::array<double, 17> db_vector, boost static float rf_gain_to_voltage(float gain, double lo_freq){ //clip the input - gain = std::clip<float>(gain, get_tvrx_gain_ranges()["RF"].min, get_tvrx_gain_ranges()["RF"].max); + gain = get_tvrx_gain_ranges()["RF"].clip(gain); //first we need to find out what band we're in, because gains are different across different bands std::string band = get_band(lo_freq + tvrx_if_freq); @@ -305,7 +305,7 @@ static float rf_gain_to_voltage(float gain, double lo_freq){ static float if_gain_to_voltage(float gain){ //clip the input - gain = std::clip<float>(gain, get_tvrx_gain_ranges()["IF"].min, get_tvrx_gain_ranges()["IF"].max); + gain = get_tvrx_gain_ranges()["IF"].clip(gain); double gain_volts = gain_interp(gain, tvrx_if_gains_db, tvrx_gains_volts); double dac_volts = gain_volts / opamp_gain; @@ -337,7 +337,7 @@ void tvrx::set_gain(float gain, const std::string &name){ */ void tvrx::set_freq(double freq) { - freq = std::clip<double>(freq, tvrx_freq_range.min, tvrx_freq_range.max); + freq = tvrx_freq_range.clip(freq); std::string prev_band = get_band(_lo_freq - tvrx_if_freq); std::string new_band = get_band(freq); diff --git a/host/lib/usrp/dboard/db_unknown.cpp b/host/lib/usrp/dboard/db_unknown.cpp index d0359d124..168e1971c 100644 --- a/host/lib/usrp/dboard/db_unknown.cpp +++ b/host/lib/usrp/dboard/db_unknown.cpp @@ -131,7 +131,7 @@ void unknown_rx::rx_get(const wax::obj &key_, wax::obj &val){ return; case SUBDEV_PROP_FREQ_RANGE: - val = freq_range_t(0, 0); + val = freq_range_t(0.0, 0.0); return; case SUBDEV_PROP_ANTENNA: @@ -233,7 +233,7 @@ void unknown_tx::tx_get(const wax::obj &key_, wax::obj &val){ return; case SUBDEV_PROP_FREQ_RANGE: - val = freq_range_t(0, 0); + val = freq_range_t(0.0, 0.0); return; case SUBDEV_PROP_ANTENNA: diff --git a/host/lib/usrp/dboard/db_wbx.cpp b/host/lib/usrp/dboard/db_wbx.cpp index 572f5de97..dd5bd600b 100644 --- a/host/lib/usrp/dboard/db_wbx.cpp +++ b/host/lib/usrp/dboard/db_wbx.cpp @@ -177,15 +177,15 @@ wbx_xcvr::wbx_xcvr(ctor_args_t args) : xcvr_dboard_base(args){ ) % RXIO_MASK % TXIO_MASK << std::endl; //set some default values - set_rx_lo_freq((wbx_freq_range.min + wbx_freq_range.max)/2.0); - set_tx_lo_freq((wbx_freq_range.min + wbx_freq_range.max)/2.0); + set_rx_lo_freq((wbx_freq_range.start() + wbx_freq_range.stop())/2.0); + set_tx_lo_freq((wbx_freq_range.start() + wbx_freq_range.stop())/2.0); set_rx_ant("RX2"); BOOST_FOREACH(const std::string &name, wbx_tx_gain_ranges.keys()){ - set_tx_gain(wbx_tx_gain_ranges[name].min, name); + set_tx_gain(wbx_tx_gain_ranges[name].start(), name); } BOOST_FOREACH(const std::string &name, wbx_rx_gain_ranges.keys()){ - set_rx_gain(wbx_rx_gain_ranges[name].min, name); + set_rx_gain(wbx_rx_gain_ranges[name].start(), name); } } @@ -198,33 +198,32 @@ wbx_xcvr::~wbx_xcvr(void){ **********************************************************************/ static int rx_pga0_gain_to_iobits(float &gain){ //clip the input - gain = std::clip<float>(gain, wbx_rx_gain_ranges["PGA0"].min, wbx_rx_gain_ranges["PGA0"].max); + gain = wbx_rx_gain_ranges["PGA0"].clip(gain); //convert to attenuation and update iobits for atr - float attn = wbx_rx_gain_ranges["PGA0"].max - gain; + float attn = wbx_rx_gain_ranges["PGA0"].stop() - gain; //calculate the attenuation - int attn_code = int(floor(attn*2)); + int attn_code = boost::math::iround(attn*2); int iobits = ((~attn_code) << RX_ATTN_SHIFT) & RX_ATTN_MASK; - if (wbx_debug) std::cerr << boost::format( "WBX Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x" ) % attn % attn_code % (iobits & RX_ATTN_MASK) % RX_ATTN_MASK << std::endl; //the actual gain setting - gain = wbx_rx_gain_ranges["PGA0"].max - float(attn_code)/2; + gain = wbx_rx_gain_ranges["PGA0"].stop() - float(attn_code)/2; return iobits; } static float tx_pga0_gain_to_dac_volts(float &gain){ //clip the input - gain = std::clip<float>(gain, wbx_tx_gain_ranges["PGA0"].min, wbx_tx_gain_ranges["PGA0"].max); + gain = wbx_tx_gain_ranges["PGA0"].clip(gain); //voltage level constants static const float max_volts = float(0.5), min_volts = float(1.4); - static const float slope = (max_volts-min_volts)/wbx_tx_gain_ranges["PGA0"].max; + static const float slope = (max_volts-min_volts)/wbx_tx_gain_ranges["PGA0"].stop(); //calculate the voltage for the aux dac float dac_volts = gain*slope + min_volts; @@ -328,7 +327,7 @@ double wbx_xcvr::set_lo_freq( ) % (target_freq/1e6) << std::endl; //clip the input - target_freq = std::clip(target_freq, wbx_freq_range.min, wbx_freq_range.max); + target_freq = wbx_freq_range.clip(target_freq); //map prescaler setting to mininmum integer divider (N) values (pg.18 prescaler) static const uhd::dict<int, int> prescaler_to_min_int_div = map_list_of diff --git a/host/lib/usrp/dboard/db_xcvr2450.cpp b/host/lib/usrp/dboard/db_xcvr2450.cpp index be0e42b92..a3a1e6242 100644 --- a/host/lib/usrp/dboard/db_xcvr2450.cpp +++ b/host/lib/usrp/dboard/db_xcvr2450.cpp @@ -72,8 +72,10 @@ using namespace boost::assign; **********************************************************************/ static const bool xcvr2450_debug = false; -static const freq_range_t xcvr_freq_range(2.4e9, 6.0e9); -static const freq_range_t xcvr_freq_band_seperation(2.5e9, 4.9e9); +static const freq_range_t xcvr_freq_range = list_of + (range_t<double>(2.4e9, 2.5e9)) + (range_t<double>(4.9e9, 6.0e9)) +; static const prop_names_t xcvr_antennas = list_of("J1")("J2"); @@ -82,7 +84,11 @@ static const uhd::dict<std::string, gain_range_t> xcvr_tx_gain_ranges = map_list ("BB", gain_range_t(0, 5, 1.5)) ; static const uhd::dict<std::string, gain_range_t> xcvr_rx_gain_ranges = map_list_of - ("LNA", gain_range_t(0, 30.5, 15)) + ("LNA", gain_range_t(list_of + (range_t<float>(0)) + (range_t<float>(15)) + (range_t<float>(30.5)) + )) ("VGA", gain_range_t(0, 62, 2.0)) ; @@ -212,10 +218,10 @@ xcvr2450::xcvr2450(ctor_args_t args) : xcvr_dboard_base(args){ set_rx_ant(xcvr_antennas.at(0)); set_tx_ant(xcvr_antennas.at(1)); BOOST_FOREACH(const std::string &name, xcvr_tx_gain_ranges.keys()){ - set_tx_gain(xcvr_tx_gain_ranges[name].min, name); + set_tx_gain(xcvr_tx_gain_ranges[name].start(), name); } BOOST_FOREACH(const std::string &name, xcvr_rx_gain_ranges.keys()){ - set_rx_gain(xcvr_rx_gain_ranges[name].min, name); + set_rx_gain(xcvr_rx_gain_ranges[name].start(), name); } } @@ -259,17 +265,9 @@ void xcvr2450::update_atr(void){ * Tuning **********************************************************************/ void xcvr2450::set_lo_freq(double target_freq){ - //clip for highband and lowband - if((target_freq > xcvr_freq_band_seperation.min) and (target_freq < xcvr_freq_band_seperation.max)){ - if(target_freq - xcvr_freq_band_seperation.min < xcvr_freq_band_seperation.max - target_freq){ - target_freq = xcvr_freq_band_seperation.min; - }else{ - target_freq = xcvr_freq_band_seperation.max; - } - } - //clip for max and min - target_freq = std::clip(target_freq, xcvr_freq_range.min, xcvr_freq_range.max); + //clip the input to the range + target_freq = xcvr_freq_range.clip(target_freq); //variables used in the calculation below double scaler = xcvr2450::is_highband(target_freq)? (4.0/5.0) : (4.0/3.0); diff --git a/host/lib/usrp/dsp_utils.cpp b/host/lib/usrp/dsp_utils.cpp index 10ae9a086..2553e4a25 100644 --- a/host/lib/usrp/dsp_utils.cpp +++ b/host/lib/usrp/dsp_utils.cpp @@ -109,9 +109,7 @@ boost::uint32_t dsp_type1::calc_iq_scale_word(unsigned rate){ return calc_iq_scale_word(scale, scale); } -boost::uint32_t dsp_type1::calc_stream_cmd_word( - const stream_cmd_t &stream_cmd, size_t num_samps_continuous -){ +boost::uint32_t dsp_type1::calc_stream_cmd_word(const stream_cmd_t &stream_cmd){ UHD_ASSERT_THROW(stream_cmd.num_samps <= 0x3fffffff); //setup the mode to instruction flags @@ -133,6 +131,6 @@ boost::uint32_t dsp_type1::calc_stream_cmd_word( word |= boost::uint32_t((stream_cmd.stream_now)? 1 : 0) << 31; word |= boost::uint32_t((inst_chain)? 1 : 0) << 30; word |= boost::uint32_t((inst_reload)? 1 : 0) << 29; - word |= (inst_samps)? stream_cmd.num_samps : ((inst_chain)? num_samps_continuous : 1); + word |= (inst_samps)? stream_cmd.num_samps : ((inst_chain)? 1 : 0); return word; } diff --git a/host/lib/usrp/mboard_eeprom.cpp b/host/lib/usrp/mboard_eeprom.cpp index 70f4664a0..a9270cda6 100644 --- a/host/lib/usrp/mboard_eeprom.cpp +++ b/host/lib/usrp/mboard_eeprom.cpp @@ -66,7 +66,7 @@ static const boost::uint8_t N100_EEPROM_ADDR = 0x50; static const uhd::dict<std::string, boost::uint8_t> USRP_N100_OFFSETS = boost::assign::map_list_of ("rev-lsb-msb", 0x00) ("mac-addr", 0x02) - ("ip-addr", 0x08) + ("ip-addr", 0x0C) //leave space here for other addresses (perhaps) ("serial", 0x18) ("name", 0x18 + SERIAL_LEN) @@ -141,7 +141,7 @@ static void store_n100(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ * Implementation of B000 load/store **********************************************************************/ static const boost::uint8_t B000_EEPROM_ADDR = 0x50; -static const size_t B000X_SERIAL_LEN = 8; +static const size_t B000_SERIAL_LEN = 8; static const uhd::dict<std::string, boost::uint8_t> USRP_B000_OFFSETS = boost::assign::map_list_of ("serial", 0xf8) @@ -151,7 +151,7 @@ static const uhd::dict<std::string, boost::uint8_t> USRP_B000_OFFSETS = boost::a static void load_b000(mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ //extract the serial mb_eeprom["serial"] = bytes_to_string(iface.read_eeprom( - B000_EEPROM_ADDR, USRP_B000_OFFSETS["serial"], B000X_SERIAL_LEN + B000_EEPROM_ADDR, USRP_B000_OFFSETS["serial"], B000_SERIAL_LEN )); //extract the name @@ -164,7 +164,7 @@ static void store_b000(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ //store the serial if (mb_eeprom.has_key("serial")) iface.write_eeprom( B000_EEPROM_ADDR, USRP_B000_OFFSETS["serial"], - string_to_bytes(mb_eeprom["serial"], B000X_SERIAL_LEN) + string_to_bytes(mb_eeprom["serial"], B000_SERIAL_LEN) ); //store the name diff --git a/host/lib/usrp/usrp1/codec_ctrl.cpp b/host/lib/usrp/usrp1/codec_ctrl.cpp index 4aa730573..18f794632 100644 --- a/host/lib/usrp/usrp1/codec_ctrl.cpp +++ b/host/lib/usrp/usrp1/codec_ctrl.cpp @@ -160,19 +160,19 @@ usrp1_codec_ctrl_impl::~usrp1_codec_ctrl_impl(void) static const int mtpgw = 255; //maximum tx pga gain word void usrp1_codec_ctrl_impl::set_tx_pga_gain(float gain){ - int gain_word = int(mtpgw*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); + int gain_word = int(mtpgw*(gain - tx_pga_gain_range.start())/(tx_pga_gain_range.stop() - tx_pga_gain_range.start())); _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, mtpgw); this->send_reg(16); } float usrp1_codec_ctrl_impl::get_tx_pga_gain(void){ - return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/mtpgw) + tx_pga_gain_range.min; + return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.stop() - tx_pga_gain_range.start())/mtpgw) + tx_pga_gain_range.start(); } static const int mrpgw = 0x14; //maximum rx pga gain word void usrp1_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){ - int gain_word = int(mrpgw*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min)); + int gain_word = int(mrpgw*(gain - rx_pga_gain_range.start())/(rx_pga_gain_range.stop() - rx_pga_gain_range.start())); gain_word = std::clip(gain_word, 0, mrpgw); switch(which){ case 'A': @@ -194,7 +194,7 @@ float usrp1_codec_ctrl_impl::get_rx_pga_gain(char which){ case 'B': gain_word = _ad9862_regs.rx_pga_b; break; default: UHD_THROW_INVALID_CODE_PATH(); } - return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/mrpgw) + rx_pga_gain_range.min; + return (gain_word*(rx_pga_gain_range.stop() - rx_pga_gain_range.start())/mrpgw) + rx_pga_gain_range.start(); } /*********************************************************************** diff --git a/host/lib/usrp/usrp2/CMakeLists.txt b/host/lib/usrp/usrp2/CMakeLists.txt index 078485d6a..f7984fce5 100644 --- a/host/lib/usrp/usrp2/CMakeLists.txt +++ b/host/lib/usrp/usrp2/CMakeLists.txt @@ -44,6 +44,8 @@ IF(ENABLE_USRP2) ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/dboard_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/dboard_iface.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/dsp_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/gps_ctrl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/gps_ctrl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/io_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/mboard_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/serdes_ctrl.cpp @@ -53,6 +55,7 @@ IF(ENABLE_USRP2) ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/usrp2_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/usrp2_impl.hpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/usrp2_regs.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/usrp2_regs.cpp ) ELSE(ENABLE_USRP2) MESSAGE(STATUS " Skipping USRP2 support.") diff --git a/host/lib/usrp/usrp2/clock_ctrl.cpp b/host/lib/usrp/usrp2/clock_ctrl.cpp index 232f3b32a..428d5539b 100644 --- a/host/lib/usrp/usrp2/clock_ctrl.cpp +++ b/host/lib/usrp/usrp2/clock_ctrl.cpp @@ -18,6 +18,7 @@ #include "clock_ctrl.hpp" #include "ad9510_regs.hpp" #include "usrp2_regs.hpp" //spi slave constants +#include "usrp2_clk_regs.hpp" #include <uhd/utils/assert.hpp> #include <boost/cstdint.hpp> #include <boost/lexical_cast.hpp> @@ -32,9 +33,10 @@ class usrp2_clock_ctrl_impl : public usrp2_clock_ctrl{ public: usrp2_clock_ctrl_impl(usrp2_iface::sptr iface){ _iface = iface; + clk_regs = usrp2_clk_regs_t(_iface->get_rev()); _ad9510_regs.cp_current_setting = ad9510_regs_t::CP_CURRENT_SETTING_3_0MA; - this->write_reg(0x09); + this->write_reg(clk_regs.pll_3); // Setup the clock registers to 100MHz: // This was already done by the firmware (or the host couldnt communicate). @@ -44,20 +46,20 @@ public: _ad9510_regs.pll_power_down = ad9510_regs_t::PLL_POWER_DOWN_NORMAL; _ad9510_regs.prescaler_value = ad9510_regs_t::PRESCALER_VALUE_DIV2; - this->write_reg(0x0A); + this->write_reg(clk_regs.pll_4); _ad9510_regs.acounter = 0; - this->write_reg(0x04); + this->write_reg(clk_regs.acounter); _ad9510_regs.bcounter_msb = 0; _ad9510_regs.bcounter_lsb = 5; - this->write_reg(0x05); - this->write_reg(0x06); + this->write_reg(clk_regs.bcounter_msb); + this->write_reg(clk_regs.bcounter_lsb); _ad9510_regs.ref_counter_msb = 0; _ad9510_regs.ref_counter_lsb = 1; // r divider = 1 - this->write_reg(0x0B); - this->write_reg(0x0C); + this->write_reg(clk_regs.ref_counter_msb); + this->write_reg(clk_regs.ref_counter_lsb); /* regs will be updated in commands below */ @@ -84,16 +86,13 @@ public: } void enable_mimo_clock_out(bool enb){ - boost::uint16_t rev = boost::lexical_cast<boost::uint16_t>(_iface->mb_eeprom["rev"]); - boost::uint8_t rev_hi = boost::uint8_t(rev >> 8); - //calculate the low and high dividers size_t divider = size_t(this->get_master_clock_rate()/10e6); size_t high = divider/2; size_t low = divider - high; - switch(rev_hi){ - case 3: //clock 2 + switch(clk_regs.exp){ + case 2: //U2 rev 3 _ad9510_regs.power_down_lvpecl_out2 = enb? ad9510_regs_t::POWER_DOWN_LVPECL_OUT2_NORMAL : ad9510_regs_t::POWER_DOWN_LVPECL_OUT2_SAFE_PD; @@ -102,11 +101,9 @@ public: _ad9510_regs.divider_low_cycles_out2 = low - 1; _ad9510_regs.divider_high_cycles_out2 = high - 1; _ad9510_regs.bypass_divider_out2 = 0; - this->write_reg(0x3e); - this->write_reg(0x4c); break; - case 4: //clock 5 + case 5: //U2 rev 4 _ad9510_regs.power_down_lvds_cmos_out5 = enb? 0 : 1; _ad9510_regs.lvds_cmos_select_out5 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT5_LVDS; _ad9510_regs.output_level_lvds_out5 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT5_1_75MA; @@ -114,14 +111,23 @@ public: _ad9510_regs.divider_low_cycles_out5 = low - 1; _ad9510_regs.divider_high_cycles_out5 = high - 1; _ad9510_regs.bypass_divider_out5 = 0; - this->write_reg(0x41); - this->write_reg(0x52); + break; + + case 6: //U2+ + _ad9510_regs.power_down_lvds_cmos_out6 = enb? 0 : 1; + _ad9510_regs.lvds_cmos_select_out6 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT6_LVDS; + _ad9510_regs.output_level_lvds_out6 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT6_1_75MA; + //set the registers (divider - 1) + _ad9510_regs.divider_low_cycles_out6 = low - 1; + _ad9510_regs.divider_high_cycles_out6 = high - 1; + _ad9510_regs.bypass_divider_out5 = 0; break; - //TODO FIXME do i want to throw, what about uninitialized boards? - //default: throw std::runtime_error("unknown rev hi in mboard eeprom"); - default: std::cerr << "unknown rev hi: " << rev_hi << std::endl; + default: + break; } + this->write_reg(clk_regs.output(clk_regs.exp)); + this->write_reg(clk_regs.div_lo(clk_regs.exp)); this->update_regs(); } @@ -130,7 +136,7 @@ public: _ad9510_regs.power_down_lvds_cmos_out7 = enb? 0 : 1; _ad9510_regs.lvds_cmos_select_out7 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT7_CMOS; _ad9510_regs.output_level_lvds_out7 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT7_1_75MA; - this->write_reg(0x43); + this->write_reg(clk_regs.output(clk_regs.rx_db)); this->update_regs(); } @@ -146,8 +152,8 @@ public: _ad9510_regs.divider_low_cycles_out7 = low - 1; _ad9510_regs.divider_high_cycles_out7 = high - 1; //write the registers - this->write_reg(0x56); - this->write_reg(0x57); + this->write_reg(clk_regs.div_lo(clk_regs.rx_db)); + this->write_reg(clk_regs.div_hi(clk_regs.rx_db)); this->update_regs(); } @@ -157,12 +163,22 @@ public: return rates; } - //uses output clock 6 (cmos) + //uses output clock 6 (cmos) on USRP2 and output clock 5 (cmos) on USRP2+ void enable_tx_dboard_clock(bool enb){ - _ad9510_regs.power_down_lvds_cmos_out6 = enb? 0 : 1; - _ad9510_regs.lvds_cmos_select_out6 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT6_CMOS; - _ad9510_regs.output_level_lvds_out6 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT6_1_75MA; - this->write_reg(0x42); + switch(clk_regs.tx_db) { + case 5: //USRP2+ + _ad9510_regs.power_down_lvds_cmos_out5 = enb? 0 : 1; + _ad9510_regs.lvds_cmos_select_out5 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT5_CMOS; + _ad9510_regs.output_level_lvds_out5 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT5_1_75MA; + break; + case 6: //USRP2 + _ad9510_regs.power_down_lvds_cmos_out6 = enb? 0 : 1; + _ad9510_regs.lvds_cmos_select_out6 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT6_CMOS; + _ad9510_regs.output_level_lvds_out6 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT6_1_75MA; + break; + } + + this->write_reg(clk_regs.output(clk_regs.tx_db)); this->update_regs(); } @@ -174,18 +190,44 @@ public: //calculate the low and high dividers size_t high = divider/2; size_t low = divider - high; - //set the registers (divider - 1) - _ad9510_regs.divider_low_cycles_out6 = low - 1; - _ad9510_regs.divider_high_cycles_out6 = high - 1; + + switch(clk_regs.tx_db) { + case 5: //USRP2+ + _ad9510_regs.bypass_divider_out5 = (divider == 1)? 1 : 0; + _ad9510_regs.divider_low_cycles_out5 = low - 1; + _ad9510_regs.divider_high_cycles_out5 = high - 1; + break; + case 6: //USRP2 + //bypass when the divider ratio is one + _ad9510_regs.bypass_divider_out6 = (divider == 1)? 1 : 0; + //set the registers (divider - 1) + _ad9510_regs.divider_low_cycles_out6 = low - 1; + _ad9510_regs.divider_high_cycles_out6 = high - 1; + break; + } + //write the registers - this->write_reg(0x54); - this->write_reg(0x55); + this->write_reg(clk_regs.div_hi(clk_regs.tx_db)); + this->write_reg(clk_regs.div_lo(clk_regs.tx_db)); this->update_regs(); } std::vector<double> get_rates_tx_dboard_clock(void){ return get_rates_rx_dboard_clock(); //same master clock, same dividers... } + + void enable_test_clock(bool enb) { + _ad9510_regs.power_down_lvpecl_out0 = enb? + ad9510_regs_t::POWER_DOWN_LVPECL_OUT0_NORMAL : + ad9510_regs_t::POWER_DOWN_LVPECL_OUT0_SAFE_PD; + _ad9510_regs.output_level_lvpecl_out0 = ad9510_regs_t::OUTPUT_LEVEL_LVPECL_OUT0_810MV; + _ad9510_regs.divider_low_cycles_out0 = 0; + _ad9510_regs.divider_high_cycles_out0 = 0; + _ad9510_regs.bypass_divider_out0 = 1; + this->write_reg(0x3c); + this->write_reg(0x48); + this->write_reg(0x49); + } /*! * If we are to use an external reference, enable the charge pump. @@ -197,7 +239,7 @@ public: ad9510_regs_t::CHARGE_PUMP_MODE_3STATE ; _ad9510_regs.pll_mux_control = ad9510_regs_t::PLL_MUX_CONTROL_DLD_HIGH; _ad9510_regs.pfd_polarity = ad9510_regs_t::PFD_POLARITY_POS; - this->write_reg(0x08); + this->write_reg(clk_regs.pll_2); this->update_regs(); } @@ -220,33 +262,46 @@ private: */ void update_regs(void){ _ad9510_regs.update_registers = 1; - this->write_reg(0x5a); + this->write_reg(clk_regs.update); } //uses output clock 3 (pecl) + //this is the same between USRP2 and USRP2+ and doesn't get a switch statement void enable_dac_clock(bool enb){ _ad9510_regs.power_down_lvpecl_out3 = (enb)? ad9510_regs_t::POWER_DOWN_LVPECL_OUT3_NORMAL : ad9510_regs_t::POWER_DOWN_LVPECL_OUT3_SAFE_PD; _ad9510_regs.output_level_lvpecl_out3 = ad9510_regs_t::OUTPUT_LEVEL_LVPECL_OUT3_810MV; _ad9510_regs.bypass_divider_out3 = 1; - this->write_reg(0x3F); - this->write_reg(0x4F); + this->write_reg(clk_regs.output(clk_regs.dac)); + this->write_reg(clk_regs.div_hi(clk_regs.dac)); this->update_regs(); } - //uses output clock 4 (lvds) + //uses output clock 4 (lvds) on USRP2 and output clock 2 (lvpecl) on USRP2+ void enable_adc_clock(bool enb){ - _ad9510_regs.power_down_lvds_cmos_out4 = enb? 0 : 1; - _ad9510_regs.lvds_cmos_select_out4 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT4_LVDS; - _ad9510_regs.output_level_lvds_out4 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT4_1_75MA; - _ad9510_regs.bypass_divider_out4 = 1; - this->write_reg(0x40); - this->write_reg(0x51); + switch(clk_regs.adc) { + case 2: + _ad9510_regs.power_down_lvpecl_out2 = enb? ad9510_regs_t::POWER_DOWN_LVPECL_OUT2_NORMAL : ad9510_regs_t::POWER_DOWN_LVPECL_OUT2_SAFE_PD; + _ad9510_regs.output_level_lvpecl_out2 = ad9510_regs_t::OUTPUT_LEVEL_LVPECL_OUT2_500MV; + _ad9510_regs.bypass_divider_out2 = 1; + break; + case 4: + _ad9510_regs.power_down_lvds_cmos_out4 = enb? 0 : 1; + _ad9510_regs.lvds_cmos_select_out4 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT4_LVDS; + _ad9510_regs.output_level_lvds_out4 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT4_1_75MA; + _ad9510_regs.bypass_divider_out4 = 1; + break; + } + + this->write_reg(clk_regs.output(clk_regs.adc)); + this->write_reg(clk_regs.div_hi(clk_regs.adc)); this->update_regs(); } - + usrp2_iface::sptr _iface; + + usrp2_clk_regs_t clk_regs; ad9510_regs_t _ad9510_regs; }; diff --git a/host/lib/usrp/usrp2/clock_ctrl.hpp b/host/lib/usrp/usrp2/clock_ctrl.hpp index 70a104a81..db6c52c83 100644 --- a/host/lib/usrp/usrp2/clock_ctrl.hpp +++ b/host/lib/usrp/usrp2/clock_ctrl.hpp @@ -83,6 +83,12 @@ public: * \param enb true to enable */ virtual void enable_external_ref(bool enb) = 0; + + /*! + * Enable/disable test clock output. + * \param enb true to enable + */ + virtual void enable_test_clock(bool enb) = 0; /*! * TODO other clock control api here.... diff --git a/host/lib/usrp/usrp2/codec_ctrl.cpp b/host/lib/usrp/usrp2/codec_ctrl.cpp index 32cc13ded..ad1ae1acb 100644 --- a/host/lib/usrp/usrp2/codec_ctrl.cpp +++ b/host/lib/usrp/usrp2/codec_ctrl.cpp @@ -17,10 +17,12 @@ #include "codec_ctrl.hpp" #include "ad9777_regs.hpp" +#include "ads62p44_regs.hpp" #include "usrp2_regs.hpp" #include <boost/cstdint.hpp> #include <boost/foreach.hpp> #include <iostream> +#include <uhd/utils/exception.hpp> static const bool codec_ctrl_debug = false; @@ -57,7 +59,24 @@ public: } //power-up adc - _iface->poke32(U2_REG_MISC_CTRL_ADC, U2_FLAG_MISC_CTRL_ADC_ON); + switch(_iface->get_rev()){ + case usrp2_iface::USRP2_REV3: + case usrp2_iface::USRP2_REV4: + _iface->poke32(_iface->regs.misc_ctrl_adc, U2_FLAG_MISC_CTRL_ADC_ON); + break; + + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + _ads62p44_regs.reset = 1; + this->send_ads62p44_reg(0x00); //issue a reset to the ADC + //everything else should be pretty much default, i think + //_ads62p44_regs.decimation = DECIMATION_DECIMATE_1; + _ads62p44_regs.power_down = ads62p44_regs_t::POWER_DOWN_NORMAL; + this->send_ads62p44_reg(0x14); + break; + + case usrp2_iface::USRP_NXXX: break; + } } ~usrp2_codec_ctrl_impl(void){ @@ -66,11 +85,62 @@ public: this->send_ad9777_reg(0); //power-down adc - _iface->poke32(U2_REG_MISC_CTRL_ADC, U2_FLAG_MISC_CTRL_ADC_OFF); + switch(_iface->get_rev()){ + case usrp2_iface::USRP2_REV3: + case usrp2_iface::USRP2_REV4: + _iface->poke32(_iface->regs.misc_ctrl_adc, U2_FLAG_MISC_CTRL_ADC_OFF); + break; + + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + //send a global power-down to the ADC here... it will get lifted on reset + _ads62p44_regs.power_down = ads62p44_regs_t::POWER_DOWN_GLOBAL_PD; + this->send_ads62p44_reg(0x14); + break; + + case usrp2_iface::USRP_NXXX: break; + } + } + + void set_rx_digital_gain(float gain) { //fine digital gain + switch(_iface->get_rev()){ + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + _ads62p44_regs.fine_gain = int(gain/0.5); + this->send_ads62p44_reg(0x17); + break; + + default: UHD_THROW_INVALID_CODE_PATH(); + } + } + + void set_rx_digital_fine_gain(float gain) { //gain correction + switch(_iface->get_rev()){ + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + _ads62p44_regs.gain_correction = int(gain / 0.05); + this->send_ads62p44_reg(0x1A); + break; + + default: UHD_THROW_INVALID_CODE_PATH(); + } + } + + void set_rx_analog_gain(bool gain) { //turns on/off analog 3.5dB preamp + switch(_iface->get_rev()){ + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + _ads62p44_regs.coarse_gain = gain ? ads62p44_regs_t::COARSE_GAIN_3_5DB : ads62p44_regs_t::COARSE_GAIN_0DB; + this->send_ads62p44_reg(0x14); + break; + + default: UHD_THROW_INVALID_CODE_PATH(); + } } private: ad9777_regs_t _ad9777_regs; + ads62p44_regs_t _ads62p44_regs; usrp2_iface::sptr _iface; void send_ad9777_reg(boost::uint8_t addr){ @@ -81,6 +151,14 @@ private: reg, 16, false /*no rb*/ ); } + + void send_ads62p44_reg(boost::uint8_t addr) { + boost::uint16_t reg = _ads62p44_regs.get_write_reg(addr); + _iface->transact_spi( + SPI_SS_ADS62P44, spi_config_t::EDGE_FALL, + reg, 16, false /*no rb*/ + ); + } }; /*********************************************************************** diff --git a/host/lib/usrp/usrp2/codec_ctrl.hpp b/host/lib/usrp/usrp2/codec_ctrl.hpp index ad014e0e1..57a37b94b 100644 --- a/host/lib/usrp/usrp2/codec_ctrl.hpp +++ b/host/lib/usrp/usrp2/codec_ctrl.hpp @@ -33,6 +33,27 @@ public: */ static sptr make(usrp2_iface::sptr iface); + /*! + * Set the analog preamplifier on the USRP2+ ADC (ADS62P44). + * \param gain enable or disable the 3.5dB preamp + */ + + virtual void set_rx_analog_gain(bool gain) = 0; + + /*! + * Set the digital gain on the USRP2+ ADC (ADS62P44). + * \param gain from 0-6dB + */ + + virtual void set_rx_digital_gain(float gain) = 0; + + /*! + * Set the digital gain correction on the USRP2+ ADC (ADS62P44). + * \param gain from 0-0.5dB + */ + + virtual void set_rx_digital_fine_gain(float gain) = 0; + }; #endif /* INCLUDED_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/usrp2/codec_impl.cpp b/host/lib/usrp/usrp2/codec_impl.cpp index fc917b102..e417bc340 100644 --- a/host/lib/usrp/usrp2/codec_impl.cpp +++ b/host/lib/usrp/usrp2/codec_impl.cpp @@ -17,10 +17,23 @@ #include "usrp2_impl.hpp" #include <uhd/usrp/codec_props.hpp> +#include <uhd/types/dict.hpp> +#include <uhd/types/ranges.hpp> #include <boost/bind.hpp> +#include <boost/assign/list_of.hpp> +#include <uhd/utils/assert.hpp> +#include <uhd/utils/exception.hpp> using namespace uhd; using namespace uhd::usrp; +using namespace boost::assign; + +//this only applies to USRP2P +static const uhd::dict<std::string, gain_range_t> codec_rx_gain_ranges = map_list_of + ("analog", gain_range_t(0, float(3.5), float(3.5))) + ("digital", gain_range_t(0, float(6.0), float(0.5))) + ("digital-fine", gain_range_t(0, float(0.5), float(0.05))); + /*********************************************************************** * Helper Methods @@ -40,12 +53,27 @@ void usrp2_mboard_impl::codec_init(void){ /*********************************************************************** * RX Codec Properties **********************************************************************/ -void usrp2_mboard_impl::rx_codec_get(const wax::obj &key, wax::obj &val){ +void usrp2_mboard_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key switch(key.as<codec_prop_t>()){ case CODEC_PROP_NAME: - val = std::string("usrp2 adc"); + switch(_iface->get_rev()){ + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + val = _iface->get_cname() + " adc - ads62p44"; + break; + + case usrp2_iface::USRP2_REV3: + case usrp2_iface::USRP2_REV4: + val = _iface->get_cname() + " adc - ltc2284"; + break; + + case usrp2_iface::USRP_NXXX: + val = _iface->get_cname() + " adc - ??????"; + break; + } return; case CODEC_PROP_OTHERS: @@ -53,26 +81,79 @@ void usrp2_mboard_impl::rx_codec_get(const wax::obj &key, wax::obj &val){ return; case CODEC_PROP_GAIN_NAMES: - val = prop_names_t(); //no gain elements to be controlled + switch(_iface->get_rev()){ + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + val = prop_names_t(codec_rx_gain_ranges.keys()); + return; + + default: val = prop_names_t(); + } + return; + + case CODEC_PROP_GAIN_I: + case CODEC_PROP_GAIN_Q: + assert_has(_codec_rx_gains.keys(), key.name, "codec rx gain name"); + val = _codec_rx_gains[key.name]; return; + case CODEC_PROP_GAIN_RANGE: + assert_has(codec_rx_gain_ranges.keys(), key.name, "codec rx gain range name"); + val = codec_rx_gain_ranges[key.name]; + return; + default: UHD_THROW_PROP_GET_ERROR(); } } -void usrp2_mboard_impl::rx_codec_set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); +void usrp2_mboard_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as<codec_prop_t>()) { + case CODEC_PROP_GAIN_I: + case CODEC_PROP_GAIN_Q: + this->rx_codec_set_gain(val.as<float>(), key.name); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * Helper function to set RX codec gain + ***********************************************************************/ + +void usrp2_mboard_impl::rx_codec_set_gain(float gain, const std::string &name){ + assert_has(codec_rx_gain_ranges.keys(), name, "codec rx gain name"); + + _codec_rx_gains[name] = gain; + + if(name == "analog") { + _codec_ctrl->set_rx_analog_gain(gain > 0); //just turn it on or off + return; + } + if(name == "digital") { + _codec_ctrl->set_rx_digital_gain(gain); + return; + } + if(name == "digital-fine") { + _codec_ctrl->set_rx_digital_fine_gain(gain); + return; + } + UHD_THROW_PROP_SET_ERROR(); } + /*********************************************************************** * TX Codec Properties **********************************************************************/ -void usrp2_mboard_impl::tx_codec_get(const wax::obj &key, wax::obj &val){ +void usrp2_mboard_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key switch(key.as<codec_prop_t>()){ case CODEC_PROP_NAME: - val = std::string("usrp2 dac - ad9777"); + val = _iface->get_cname() + " dac - ad9777"; return; case CODEC_PROP_OTHERS: diff --git a/host/lib/usrp/usrp2/dboard_iface.cpp b/host/lib/usrp/usrp2/dboard_iface.cpp index fdfbf0d17..ab5f62355 100644 --- a/host/lib/usrp/usrp2/dboard_iface.cpp +++ b/host/lib/usrp/usrp2/dboard_iface.cpp @@ -180,8 +180,8 @@ void usrp2_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){ //write the selection mux value to register switch(unit){ - case UNIT_RX: _iface->poke32(U2_REG_GPIO_RX_SEL, new_sels); return; - case UNIT_TX: _iface->poke32(U2_REG_GPIO_TX_SEL, new_sels); return; + case UNIT_RX: _iface->poke32(_iface->regs.gpio_rx_sel, new_sels); return; + case UNIT_TX: _iface->poke32(_iface->regs.gpio_tx_sel, new_sels); return; } } @@ -189,18 +189,18 @@ void usrp2_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){ _ddr_shadow = \ (_ddr_shadow & ~(0xffff << unit_to_shift[unit])) | (boost::uint32_t(value) << unit_to_shift[unit]); - _iface->poke32(U2_REG_GPIO_DDR, _ddr_shadow); + _iface->poke32(_iface->regs.gpio_ddr, _ddr_shadow); } void usrp2_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){ _gpio_shadow = \ (_gpio_shadow & ~(0xffff << unit_to_shift[unit])) | (boost::uint32_t(value) << unit_to_shift[unit]); - _iface->poke32(U2_REG_GPIO_IO, _gpio_shadow); + _iface->poke32(_iface->regs.gpio_io, _gpio_shadow); } boost::uint16_t usrp2_dboard_iface::read_gpio(unit_t unit){ - return boost::uint16_t(_iface->peek32(U2_REG_GPIO_IO) >> unit_to_shift[unit]); + return boost::uint16_t(_iface->peek32(_iface->regs.gpio_io) >> unit_to_shift[unit]); } void usrp2_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ @@ -209,16 +209,16 @@ void usrp2_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t unit_t, uhd::dict<atr_reg_t, boost::uint32_t> > unit_to_atr_to_addr = map_list_of (UNIT_RX, map_list_of - (ATR_REG_IDLE, U2_REG_ATR_IDLE_RXSIDE) - (ATR_REG_TX_ONLY, U2_REG_ATR_INTX_RXSIDE) - (ATR_REG_RX_ONLY, U2_REG_ATR_INRX_RXSIDE) - (ATR_REG_FULL_DUPLEX, U2_REG_ATR_FULL_RXSIDE) + (ATR_REG_IDLE, _iface->regs.atr_idle_rxside) + (ATR_REG_TX_ONLY, _iface->regs.atr_intx_rxside) + (ATR_REG_RX_ONLY, _iface->regs.atr_inrx_rxside) + (ATR_REG_FULL_DUPLEX, _iface->regs.atr_full_rxside) ) (UNIT_TX, map_list_of - (ATR_REG_IDLE, U2_REG_ATR_IDLE_TXSIDE) - (ATR_REG_TX_ONLY, U2_REG_ATR_INTX_TXSIDE) - (ATR_REG_RX_ONLY, U2_REG_ATR_INRX_TXSIDE) - (ATR_REG_FULL_DUPLEX, U2_REG_ATR_FULL_TXSIDE) + (ATR_REG_IDLE, _iface->regs.atr_idle_txside) + (ATR_REG_TX_ONLY, _iface->regs.atr_intx_txside) + (ATR_REG_RX_ONLY, _iface->regs.atr_inrx_txside) + (ATR_REG_FULL_DUPLEX, _iface->regs.atr_full_txside) ) ; _iface->poke16(unit_to_atr_to_addr[unit][atr], value); @@ -238,8 +238,8 @@ void usrp2_dboard_iface::set_gpio_debug(unit_t unit, int which){ //write the selection mux value to register switch(unit){ - case UNIT_RX: _iface->poke32(U2_REG_GPIO_RX_SEL, new_sels); return; - case UNIT_TX: _iface->poke32(U2_REG_GPIO_TX_SEL, new_sels); return; + case UNIT_RX: _iface->poke32(_iface->regs.gpio_rx_sel, new_sels); return; + case UNIT_TX: _iface->poke32(_iface->regs.gpio_tx_sel, new_sels); return; } } diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp index 540c9fefb..4192c4f78 100644 --- a/host/lib/usrp/usrp2/dboard_impl.cpp +++ b/host/lib/usrp/usrp2/dboard_impl.cpp @@ -64,7 +64,7 @@ void usrp2_mboard_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ //handle the get request conditioned on the key switch(key.as<dboard_prop_t>()){ case DBOARD_PROP_NAME: - val = std::string("usrp2 dboard (rx unit)"); + val = _iface->get_cname() + " dboard (rx unit)"; return; case DBOARD_PROP_SUBDEV: @@ -121,7 +121,7 @@ void usrp2_mboard_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ //handle the get request conditioned on the key switch(key.as<dboard_prop_t>()){ case DBOARD_PROP_NAME: - val = std::string("usrp2 dboard (tx unit)"); + val = _iface->get_cname() + " dboard (tx unit)"; return; case DBOARD_PROP_SUBDEV: diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp index 0c85e643f..77ed594f5 100644 --- a/host/lib/usrp/usrp2/dsp_impl.cpp +++ b/host/lib/usrp/usrp2/dsp_impl.cpp @@ -61,7 +61,7 @@ void usrp2_mboard_impl::ddc_get(const wax::obj &key_, wax::obj &val){ switch(key.as<dsp_prop_t>()){ case DSP_PROP_NAME: - val = std::string("usrp2 ddc0"); + val = _iface->get_cname() + " ddc0"; return; case DSP_PROP_OTHERS: @@ -95,7 +95,7 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val){ case DSP_PROP_FREQ_SHIFT:{ double new_freq = val.as<double>(); - _iface->poke32(U2_REG_DSP_RX_FREQ, + _iface->poke32(_iface->regs.dsp_rx_freq, dsp_type1::calc_cordic_word_and_update(new_freq, get_master_clock_freq()) ); _ddc_freq = new_freq; //shadow @@ -107,11 +107,11 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val){ _ddc_decim = pick_closest_rate(extact_rate, _allowed_decim_and_interp_rates); //set the decimation - _iface->poke32(U2_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim)); + _iface->poke32(_iface->regs.dsp_rx_decim_rate, dsp_type1::calc_cic_filter_word(_ddc_decim)); //set the scaling static const boost::int16_t default_rx_scale_iq = 1024; - _iface->poke32(U2_REG_DSP_RX_SCALE_IQ, + _iface->poke32(_iface->regs.dsp_rx_scale_iq, dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) ); } @@ -144,7 +144,7 @@ void usrp2_mboard_impl::duc_get(const wax::obj &key_, wax::obj &val){ switch(key.as<dsp_prop_t>()){ case DSP_PROP_NAME: - val = std::string("usrp2 duc0"); + val = _iface->get_cname() + " duc0"; return; case DSP_PROP_OTHERS: @@ -178,7 +178,7 @@ void usrp2_mboard_impl::duc_set(const wax::obj &key_, const wax::obj &val){ case DSP_PROP_FREQ_SHIFT:{ double new_freq = val.as<double>(); - _iface->poke32(U2_REG_DSP_TX_FREQ, + _iface->poke32(_iface->regs.dsp_tx_freq, dsp_type1::calc_cordic_word_and_update(new_freq, get_master_clock_freq()) ); _duc_freq = new_freq; //shadow @@ -190,10 +190,10 @@ void usrp2_mboard_impl::duc_set(const wax::obj &key_, const wax::obj &val){ _duc_interp = pick_closest_rate(extact_rate, _allowed_decim_and_interp_rates); //set the interpolation - _iface->poke32(U2_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp)); + _iface->poke32(_iface->regs.dsp_tx_interp_rate, dsp_type1::calc_cic_filter_word(_duc_interp)); //set the scaling - _iface->poke32(U2_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp)); + _iface->poke32(_iface->regs.dsp_tx_scale_iq, dsp_type1::calc_iq_scale_word(_duc_interp)); } return; diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h index 4ff31ddfd..a9c39e650 100644 --- a/host/lib/usrp/usrp2/fw_common.h +++ b/host/lib/usrp/usrp2/fw_common.h @@ -33,8 +33,8 @@ extern "C" { #endif //fpga and firmware compatibility numbers -#define USRP2_FPGA_COMPAT_NUM 2 -#define USRP2_FW_COMPAT_NUM 6 +#define USRP2_FPGA_COMPAT_NUM 3 +#define USRP2_FW_COMPAT_NUM 7 //used to differentiate control packets over data port #define USRP2_INVALID_VRT_HEADER 0 @@ -52,6 +52,14 @@ extern "C" { #define USRP2_I2C_ADDR_TX_DB (USRP2_I2C_DEV_EEPROM | 0x4) #define USRP2_I2C_ADDR_RX_DB (USRP2_I2C_DEV_EEPROM | 0x5) +//////////////////////////////////////////////////////////////////////// +// EEPROM Layout +//////////////////////////////////////////////////////////////////////// +#define USRP2_EE_MBOARD_REV 0x00 //2 bytes, little-endian (historic, don't blame me) +#define USRP2_EE_MBOARD_MAC_ADDR 0x02 //6 bytes +#define USRP2_EE_MBOARD_IP_ADDR 0x0C //uint32, big-endian +#define USRP2_EE_MBOARD_BOOTLOADER_FLAGS 0xF7 + typedef enum{ USRP2_CTRL_ID_HUH_WHAT = ' ', //USRP2_CTRL_ID_FOR_SURE, //TODO error condition enums @@ -75,6 +83,12 @@ typedef enum{ USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO = 'r', USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE = 'R', + USRP2_CTRL_ID_HEY_WRITE_THIS_UART_FOR_ME_BRO = 'u', + USRP2_CTRL_ID_MAN_I_TOTALLY_WROTE_THAT_UART_DUDE = 'U', + + USRP2_CTRL_ID_SO_LIKE_CAN_YOU_READ_THIS_UART_BRO = 'v', + USRP2_CTRL_ID_I_HELLA_READ_THAT_UART_DUDE = 'V', + USRP2_CTRL_ID_PEACE_OUT = '~' } usrp2_ctrl_id_t; @@ -115,6 +129,11 @@ typedef struct{ __stdint(uint32_t) datahi; __stdint(uint8_t) num_bytes; //1, 2, 4, 8 } poke_args; + struct { + __stdint(uint8_t) dev; + __stdint(uint8_t) bytes; + __stdint(uint8_t) data[20]; + } uart_args; } data; } usrp2_ctrl_data_t; diff --git a/host/lib/usrp/usrp2/gps_ctrl.cpp b/host/lib/usrp/usrp2/gps_ctrl.cpp new file mode 100644 index 000000000..2273b2cd9 --- /dev/null +++ b/host/lib/usrp/usrp2/gps_ctrl.cpp @@ -0,0 +1,207 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include "gps_ctrl.hpp" +#include <uhd/utils/assert.hpp> +#include <boost/cstdint.hpp> +#include <string> +#include <boost/date_time/posix_time/posix_time.hpp> +#include <boost/thread.hpp> +#include <boost/algorithm/string/trim.hpp> +#include <boost/tokenizer.hpp> + +using namespace uhd; +using namespace boost::gregorian; +using namespace boost::posix_time; +using namespace boost::algorithm; + +/*! + * A usrp2 GPS control for Jackson Labs devices + */ + +//TODO: multiple baud rate support (requires mboard_impl changes for poking UART registers) +class usrp2_gps_ctrl_impl : public usrp2_gps_ctrl{ +public: + usrp2_gps_ctrl_impl(usrp2_iface::sptr iface){ + _iface = iface; + + std::string reply; + bool i_heard_some_nmea = false, i_heard_something_weird = false; + + gps_type = GPS_TYPE_NONE; + +// set_uart_baud_rate(GPS_UART, 115200); + //first we look for a Jackson Labs Firefly (since that's what we sell with the USRP2+...) + + _iface->read_uart(GPS_UART); //get whatever junk is in the rx buffer right now, and throw it away + _iface->write_uart(GPS_UART, "HAAAY GUYYYYS\n"); //to elicit a response from the Firefly + + //then we loop until we either timeout, or until we get a response that indicates we're a JL device + int timeout = GPS_TIMEOUT_TRIES; + while(timeout--) { + reply = safe_gps_read(); + if(trim_right_copy(reply) == "Command Error") { + gps_type = GPS_TYPE_JACKSON_LABS; + break; + } + else if(reply.substr(0, 3) == "$GP") i_heard_some_nmea = true; //but keep looking for that "Command Error" response + else if(reply.length() != 0) i_heard_something_weird = true; //probably wrong baud rate + } + + if((i_heard_some_nmea) && (gps_type != GPS_TYPE_JACKSON_LABS)) gps_type = GPS_TYPE_GENERIC_NMEA; + + //otherwise, we can try some other common baud rates looking to see if a GPS is connected (todo, later) + if((gps_type == GPS_TYPE_NONE) && i_heard_something_weird) { + std::cout << "Invalid reply, possible incorrect baud rate" << std::endl; + } + + bool found_gprmc = false; + + switch(gps_type) { + case GPS_TYPE_JACKSON_LABS: + std::cout << "Found a Jackson Labs GPS" << std::endl; + //issue some setup stuff so it spits out the appropriate data + //none of these should issue replies so we don't bother looking for them + //we have to sleep between commands because the JL device, despite not acking, takes considerable time to process each command. + boost::this_thread::sleep(boost::posix_time::milliseconds(FIREFLY_STUPID_DELAY_MS)); + _iface->write_uart(GPS_UART, "SYST:COMM:SER:ECHO OFF\n"); + boost::this_thread::sleep(boost::posix_time::milliseconds(FIREFLY_STUPID_DELAY_MS)); + _iface->write_uart(GPS_UART, "SYST:COMM:SER:PRO OFF\n"); + boost::this_thread::sleep(boost::posix_time::milliseconds(FIREFLY_STUPID_DELAY_MS)); + _iface->write_uart(GPS_UART, "GPS:GPGGA 0\n"); + boost::this_thread::sleep(boost::posix_time::milliseconds(FIREFLY_STUPID_DELAY_MS)); + _iface->write_uart(GPS_UART, "GPS:GGAST 0\n"); + boost::this_thread::sleep(boost::posix_time::milliseconds(FIREFLY_STUPID_DELAY_MS)); + _iface->write_uart(GPS_UART, "GPS:GPRMC 1\n"); + boost::this_thread::sleep(boost::posix_time::milliseconds(FIREFLY_STUPID_DELAY_MS)); + +// break; + + case GPS_TYPE_GENERIC_NMEA: + if(gps_type == GPS_TYPE_GENERIC_NMEA) std::cout << "Found a generic NMEA GPS device" << std::endl; + found_gprmc = false; + //here we loop around looking for a GPRMC packet. if we don't get one, we don't have a usable GPS. + timeout = GPS_TIMEOUT_TRIES; + while(timeout--) { + reply = safe_gps_read(); + if(reply.substr(0, 6) == "$GPRMC") { + found_gprmc = true; + break; + } + } + if(!found_gprmc) { + if(gps_type == GPS_TYPE_JACKSON_LABS) std::cout << "Firefly GPS not locked or warming up." << std::endl; + else std::cout << "GPS does not output GPRMC packets. Cannot retrieve time." << std::endl; + gps_type = GPS_TYPE_NONE; + } + break; + + case GPS_TYPE_NONE: + default: + break; + + } + + + } + + ~usrp2_gps_ctrl_impl(void){ + + } + + std::string safe_gps_read() { + std::string reply; + try { + reply = _iface->read_uart(GPS_UART); + //std::cerr << "Got reply from GPS: " << reply.c_str() << " with length = " << reply.length() << std::endl; + } catch (std::runtime_error err) { + if(err.what() != std::string("usrp2 no control response")) throw; //sorry can't cope with that + else { //we don't actually have a GPS installed + reply = std::string(); + } + } + return reply; + } + + ptime get_time(void) { + std::string reply; + ptime now; + boost::tokenizer<boost::escaped_list_separator<char> > tok(reply); + std::vector<std::string> toked; + int timeout = GPS_TIMEOUT_TRIES; + bool found_gprmc = false; + switch(gps_type) { + case GPS_TYPE_JACKSON_LABS: //deprecated in favor of a single NMEA parser + case GPS_TYPE_GENERIC_NMEA: + + while(timeout--) { + reply = safe_gps_read(); + if(reply.substr(0, 6) == "$GPRMC") { + found_gprmc = true; + break; + } + } + UHD_ASSERT_THROW(found_gprmc); + + tok.assign(reply); + toked.assign(tok.begin(), tok.end()); + + UHD_ASSERT_THROW(toked.size() == 11); //if it's not we got something weird in there + + now = ptime( date( + greg_year(boost::lexical_cast<int>(toked[8].substr(4, 2)) + 2000), //just trust me on this one + greg_month(boost::lexical_cast<int>(toked[8].substr(2, 2))), + greg_day(boost::lexical_cast<int>(toked[8].substr(0, 2))) + ), + hours( boost::lexical_cast<int>(toked[1].substr(0, 2))) + + minutes(boost::lexical_cast<int>(toked[1].substr(2, 2))) + + seconds(boost::lexical_cast<int>(toked[1].substr(4, 2))) + ); + break; + case GPS_TYPE_NONE: + default: + throw std::runtime_error("get_time(): Unsupported GPS or no GPS detected\n"); + break; + } + return now; + } + + bool gps_detected(void) { + return (gps_type != GPS_TYPE_NONE); + } + +private: + usrp2_iface::sptr _iface; + + enum { + GPS_TYPE_JACKSON_LABS, + GPS_TYPE_GENERIC_NMEA, + GPS_TYPE_NONE + } gps_type; + + static const int GPS_UART = 2; //TODO: this should be plucked from fw_common.h or memory_map.h or somewhere in common with the firmware + static const int GPS_TIMEOUT_TRIES = 5; + static const int FIREFLY_STUPID_DELAY_MS = 200; + +}; + +/*********************************************************************** + * Public make function for the GPS control + **********************************************************************/ +usrp2_gps_ctrl::sptr usrp2_gps_ctrl::make(usrp2_iface::sptr iface){ + return sptr(new usrp2_gps_ctrl_impl(iface)); +} diff --git a/host/lib/usrp/usrp2/gps_ctrl.hpp b/host/lib/usrp/usrp2/gps_ctrl.hpp new file mode 100644 index 000000000..5936a6fb6 --- /dev/null +++ b/host/lib/usrp/usrp2/gps_ctrl.hpp @@ -0,0 +1,53 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_GPS_CTRL_HPP +#define INCLUDED_GPS_CTRL_HPP + +#include "usrp2_iface.hpp" +#include <boost/shared_ptr.hpp> +#include <boost/utility.hpp> +#include <boost/date_time/posix_time/posix_time_types.hpp> + +using namespace boost::posix_time; + +class usrp2_gps_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr<usrp2_gps_ctrl> sptr; + + /*! + * Make a GPS config for Jackson Labs or generic NMEA GPS devices + */ + static sptr make(usrp2_iface::sptr iface); + + /*! + * Get the current GPS time and date + * \return current GPS time and date as boost::posix_time::ptime object + */ + virtual ptime get_time(void) = 0; + + /*! + * Tell you if there's a supported GPS connected or not + * \return true if a supported GPS is connected + */ + virtual bool gps_detected(void) = 0; + + //TODO: other fun things you can do with a GPS. + +}; + +#endif /* INCLUDED_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp index 83b70bddc..f903a80f6 100644 --- a/host/lib/usrp/usrp2/io_impl.cpp +++ b/host/lib/usrp/usrp2/io_impl.cpp @@ -18,11 +18,11 @@ #include "../../transport/vrt_packet_handler.hpp" #include "usrp2_impl.hpp" #include "usrp2_regs.hpp" +#include <uhd/utils/byteswap.hpp> #include <uhd/utils/thread_priority.hpp> #include <uhd/transport/convert_types.hpp> #include <uhd/transport/alignment_buffer.hpp> #include <boost/format.hpp> -#include <boost/asio.hpp> //htonl and ntohl #include <boost/bind.hpp> #include <boost/thread.hpp> #include <iostream> @@ -32,7 +32,73 @@ using namespace uhd::usrp; using namespace uhd::transport; namespace asio = boost::asio; -static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; +/*********************************************************************** + * constants + **********************************************************************/ +static const int underflow_flags = 0 + | async_metadata_t::EVENT_CODE_UNDERFLOW + | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET +; + +static const size_t vrt_send_header_offset_words32 = 1; + +/*********************************************************************** + * flow control monitor for a single tx channel + * - the pirate thread calls update + * - the get send buffer calls check + **********************************************************************/ +class flow_control_monitor{ +public: + typedef boost::uint32_t seq_type; + typedef boost::shared_ptr<flow_control_monitor> sptr; + + /*! + * Make a new flow control monitor. + * \param max_seqs_out num seqs before throttling + */ + flow_control_monitor(seq_type max_seqs_out){ + _last_seq_out = 0; + _last_seq_ack = 0; + _max_seqs_out = max_seqs_out; + } + + /*! + * Check the flow control condition. + * \param seq the sequence to go out + * \param timeout the timeout in seconds + * \return false on timeout + */ + UHD_INLINE bool check_fc_condition(seq_type seq, double timeout){ + boost::this_thread::disable_interruption di; //disable because the wait can throw + boost::unique_lock<boost::mutex> lock(_fc_mutex); + _last_seq_out = seq; + return _fc_cond.timed_wait( + lock, + boost::posix_time::microseconds(long(timeout*1e6)), + boost::bind(&flow_control_monitor::ready, this) + ); + } + + /*! + * Update the flow control condition. + * \param seq the last sequence number to be ACK'd + */ + UHD_INLINE void update_fc_condition(seq_type seq){ + boost::unique_lock<boost::mutex> lock(_fc_mutex); + _last_seq_ack = seq; + lock.unlock(); + _fc_cond.notify_one(); + } + +private: + bool ready(void){ + return seq_type(_last_seq_out -_last_seq_ack) < _max_seqs_out; + } + + boost::mutex _fc_mutex; + boost::condition _fc_cond; + seq_type _last_seq_out, _last_seq_ack, _max_seqs_out; +}; /*********************************************************************** * io impl details (internal to this file) @@ -44,12 +110,14 @@ static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | asyn struct usrp2_impl::io_impl{ typedef alignment_buffer<managed_recv_buffer::sptr, time_spec_t> alignment_buffer_type; - io_impl(size_t num_frames, size_t width): + io_impl(size_t num_recv_frames, size_t send_frame_size, size_t width): packet_handler_recv_state(width), - recv_pirate_booty(alignment_buffer_type::make(num_frames-3, width)), + recv_pirate_booty(alignment_buffer_type::make(num_recv_frames-3, width)), async_msg_fifo(bounded_buffer<async_metadata_t>::make(100/*messages deep*/)) { - /* NOP */ + for (size_t i = 0; i < width; i++) fc_mons.push_back( + flow_control_monitor::sptr(new flow_control_monitor(usrp2_impl::sram_bytes/send_frame_size)) + ); } ~io_impl(void){ @@ -63,6 +131,29 @@ struct usrp2_impl::io_impl{ return recv_pirate_booty->pop_elems_with_timed_wait(buffs, timeout); } + bool get_send_buffs( + const std::vector<zero_copy_if::sptr> &trans, + vrt_packet_handler::managed_send_buffs_t &buffs, + double timeout + ){ + UHD_ASSERT_THROW(trans.size() == buffs.size()); + + //calculate the flow control word + const boost::uint32_t fc_word32 = packet_handler_send_state.next_packet_seq; + + //grab a managed buffer for each index + for (size_t i = 0; i < buffs.size(); i++){ + if (not fc_mons[i]->check_fc_condition(fc_word32, timeout)) return false; + buffs[i] = trans[i]->get_send_buff(timeout); + if (not buffs[i].get()) return false; + buffs[i]->cast<boost::uint32_t *>()[0] = uhd::htonx(fc_word32); + } + return true; + } + + //flow control monitors + std::vector<flow_control_monitor::sptr> fc_mons; + //state management for the vrt packet handler code vrt_packet_handler::recv_state packet_handler_recv_state; vrt_packet_handler::send_state packet_handler_send_state; @@ -73,6 +164,7 @@ struct usrp2_impl::io_impl{ bool recv_pirate_crew_raiding; alignment_buffer_type::sptr recv_pirate_booty; bounded_buffer<async_metadata_t>::sptr async_msg_fifo; + boost::mutex spawn_mutex; }; /*********************************************************************** @@ -89,6 +181,8 @@ void usrp2_impl::io_impl::recv_pirate_loop( recv_pirate_crew_raiding = true; size_t next_packet_seq = 0; + spawn_mutex.unlock(); + while(recv_pirate_crew_raiding){ managed_recv_buffer::sptr buff = zc_if->get_recv_buff(); if (not buff.get()) continue; //ignore timeout/error buffers @@ -100,8 +194,27 @@ void usrp2_impl::io_impl::recv_pirate_loop( const boost::uint32_t *vrt_hdr = buff->cast<const boost::uint32_t *>(); vrt::if_hdr_unpack_be(vrt_hdr, if_packet_info); + //handle the rx data stream + if (if_packet_info.sid == usrp2_impl::RECV_SID and if_packet_info.packet_type == vrt::if_packet_info_t::PACKET_TYPE_DATA){ + //handle the packet count / sequence number + if (if_packet_info.packet_count != next_packet_seq){ + //std::cerr << "S" << (if_packet_info.packet_count - next_packet_seq)%16; + std::cerr << "O" << std::flush; //report overflow (drops in the kernel) + } + next_packet_seq = (if_packet_info.packet_count+1)%16; + + //extract the timespec and round to the nearest packet + UHD_ASSERT_THROW(if_packet_info.has_tsi and if_packet_info.has_tsf); + time_spec_t time( + time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), mboard->get_master_clock_freq() + ); + + //push the packet into the buffer with the new time + recv_pirate_booty->push_with_pop_on_full(buff, time, index); + } + //handle a tx async report message - if (if_packet_info.sid == 1 and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ + else if (if_packet_info.sid == usrp2_impl::ASYNC_SID and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ //fill in the async metadata async_metadata_t metadata; @@ -112,27 +225,21 @@ void usrp2_impl::io_impl::recv_pirate_loop( ); metadata.event_code = vrt_packet_handler::get_context_code<async_metadata_t::event_code_t>(vrt_hdr, if_packet_info); + //catch the flow control packets and react + if (metadata.event_code == 0){ + boost::uint32_t fc_word32 = (vrt_hdr + if_packet_info.num_header_words32)[1]; + this->fc_mons[index]->update_fc_condition(uhd::ntohx(fc_word32)); + continue; + } + //print the famous U, and push the metadata into the message queue if (metadata.event_code & underflow_flags) std::cerr << "U" << std::flush; + //else std::cout << "metadata.event_code " << metadata.event_code << std::endl; async_msg_fifo->push_with_pop_on_full(metadata); - continue; } - - //handle the packet count / sequence number - if (if_packet_info.packet_count != next_packet_seq){ - //std::cerr << "S" << (if_packet_info.packet_count - next_packet_seq)%16; - std::cerr << "O" << std::flush; //report overflow (drops in the kernel) + else{ + //TODO unknown received packet, may want to print error... } - next_packet_seq = (if_packet_info.packet_count+1)%16; - - //extract the timespec and round to the nearest packet - UHD_ASSERT_THROW(if_packet_info.has_tsi and if_packet_info.has_tsf); - time_spec_t time( - time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), mboard->get_master_clock_freq() - ); - - //push the packet into the buffer with the new time - recv_pirate_booty->push_with_pop_on_full(buff, time, index); }catch(const std::exception &e){ std::cerr << "Error (usrp2 recv pirate loop): " << e.what() << std::endl; } @@ -143,30 +250,38 @@ void usrp2_impl::io_impl::recv_pirate_loop( * Helper Functions **********************************************************************/ void usrp2_impl::io_init(void){ - //send a small data packet so the usrp2 knows the udp source port - BOOST_FOREACH(zero_copy_if::sptr data_transport, _data_transports){ - managed_send_buffer::sptr send_buff = data_transport->get_send_buff(); - static const boost::uint32_t data = htonl(USRP2_INVALID_VRT_HEADER); - std::memcpy(send_buff->cast<void*>(), &data, sizeof(data)); - send_buff->commit(sizeof(data)); - //drain the recv buffers (may have junk) - while (data_transport->get_recv_buff().get()){}; - } - //the number of recv frames is the number for the first transport //the assumption is that all data transports should be identical - size_t num_frames = _data_transports.front()->get_num_recv_frames(); + const size_t num_recv_frames = _data_transports.front()->get_num_recv_frames(); + const size_t send_frame_size = _data_transports.front()->get_send_frame_size(); //create new io impl - _io_impl = UHD_PIMPL_MAKE(io_impl, (num_frames, _data_transports.size())); + _io_impl = UHD_PIMPL_MAKE(io_impl, (num_recv_frames, send_frame_size, _data_transports.size())); + + //TODO temporary fix for weird power up state, remove when FPGA fixed + { + //send an initial packet to all transports + tx_metadata_t md; md.end_of_burst = true; + this->send( + std::vector<const void *>(_data_transports.size(), NULL), 0, md, + io_type_t::COMPLEX_FLOAT32, device::SEND_MODE_ONE_PACKET, 0 + ); + } //create a new pirate thread for each zc if (yarr!!) for (size_t i = 0; i < _data_transports.size(); i++){ + //lock the unlocked mutex (non-blocking) + _io_impl->spawn_mutex.lock(); + //spawn a new pirate to plunder the recv booty _io_impl->recv_pirate_crew.create_thread(boost::bind( &usrp2_impl::io_impl::recv_pirate_loop, _io_impl.get(), _data_transports.at(i), _mboards.at(i), i )); + //block here until the spawned thread unlocks + _io_impl->spawn_mutex.lock(); + //exit loop iteration in an unlocked condition + _io_impl->spawn_mutex.unlock(); } } @@ -183,23 +298,10 @@ bool usrp2_impl::recv_async_msg( /*********************************************************************** * Send Data **********************************************************************/ -static bool get_send_buffs( - const std::vector<udp_zero_copy::sptr> &trans, - vrt_packet_handler::managed_send_buffs_t &buffs, - double timeout -){ - UHD_ASSERT_THROW(trans.size() == buffs.size()); - bool good = true; - for (size_t i = 0; i < buffs.size(); i++){ - buffs[i] = trans[i]->get_send_buff(timeout); - good = good and (buffs[i].get() != NULL); - } - return good; -} - size_t usrp2_impl::get_max_send_samps_per_packet(void) const{ static const size_t hdr_size = 0 + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + + vrt_send_header_offset_words32*sizeof(boost::uint32_t) - sizeof(vrt::if_packet_info_t().cid) //no class id ever used ; const size_t bpp = _data_transports.front()->get_send_frame_size() - hdr_size; @@ -218,8 +320,9 @@ size_t usrp2_impl::send( io_type, _tx_otw_type, //input and output types to convert _mboards.front()->get_master_clock_freq(), //master clock tick rate uhd::transport::vrt::if_hdr_pack_be, - boost::bind(&get_send_buffs, _data_transports, _1, timeout), - get_max_send_samps_per_packet() + boost::bind(&usrp2_impl::io_impl::get_send_buffs, _io_impl.get(), _data_transports, _1, timeout), + get_max_send_samps_per_packet(), + vrt_send_header_offset_words32 ); } diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index a6ca7f2d3..13d8b9856 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -21,12 +21,15 @@ #include <uhd/usrp/dsp_utils.hpp> #include <uhd/usrp/mboard_props.hpp> #include <uhd/utils/assert.hpp> +#include <uhd/utils/byteswap.hpp> #include <uhd/utils/algorithm.hpp> #include <boost/bind.hpp> #include <iostream> +#include <boost/date_time/posix_time/posix_time.hpp> using namespace uhd; using namespace uhd::usrp; +using namespace boost::posix_time; /*********************************************************************** * Structors @@ -34,16 +37,31 @@ using namespace uhd::usrp; usrp2_mboard_impl::usrp2_mboard_impl( size_t index, transport::udp_simple::sptr ctrl_transport, - size_t recv_frame_size + transport::zero_copy_if::sptr data_transport, + size_t recv_samps_per_packet, + const device_addr_t &flow_control_hints ): _index(index), - _recv_frame_size(recv_frame_size), _iface(usrp2_iface::make(ctrl_transport)) { + //Send a small data packet so the usrp2 knows the udp source port. + //This setup must happen before further initialization occurs + //or the async update packets will cause ICMP destination unreachable. + transport::managed_send_buffer::sptr send_buff = data_transport->get_send_buff(); + static const boost::uint32_t data[2] = { + uhd::htonx(boost::uint32_t(0 /* don't care seq num */)), + uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER)) + }; + std::memcpy(send_buff->cast<void*>(), &data, sizeof(data)); + send_buff->commit(sizeof(data)); + //contruct the interfaces to mboard perifs _clock_ctrl = usrp2_clock_ctrl::make(_iface); _codec_ctrl = usrp2_codec_ctrl::make(_iface); _serdes_ctrl = usrp2_serdes_ctrl::make(_iface); + //_gps_ctrl = usrp2_gps_ctrl::make(_iface); + + //if(_gps_ctrl->gps_detected()) std::cout << "GPS time: " << _gps_ctrl->get_time() << std::endl; //TODO move to dsp impl... //load the allowed decim/interp rates @@ -59,30 +77,42 @@ usrp2_mboard_impl::usrp2_mboard_impl( _allowed_decim_and_interp_rates.push_back(i); } + //Issue a stop streaming command (in case it was left running). //Since this command is issued before the networking is setup, //most if not all junk packets will never make it to the socket. this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS); - //init the rx control registers - _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _recv_frame_size); - _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1); - _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); //reset - _iface->poke32(U2_REG_RX_CTRL_VRT_HEADER, 0 + //setup the vrt rx registers + _iface->poke32(_iface->regs.rx_ctrl_clear_overrun, 1); //reset + _iface->poke32(_iface->regs.rx_ctrl_nsamps_per_pkt, recv_samps_per_packet); + _iface->poke32(_iface->regs.rx_ctrl_nchannels, 1); + _iface->poke32(_iface->regs.rx_ctrl_vrt_header, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer | (0x3 << 22) //integer time other | (0x1 << 20) //fractional time sample count ); - _iface->poke32(U2_REG_RX_CTRL_VRT_STREAM_ID, 0); - _iface->poke32(U2_REG_RX_CTRL_VRT_TRAILER, 0); - _iface->poke32(U2_REG_TIME64_TPS, size_t(get_master_clock_freq())); + _iface->poke32(_iface->regs.rx_ctrl_vrt_stream_id, usrp2_impl::RECV_SID); + _iface->poke32(_iface->regs.rx_ctrl_vrt_trailer, 0); + _iface->poke32(_iface->regs.time64_tps, size_t(get_master_clock_freq())); //init the tx control registers - _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0); //1 channel - _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset - _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1); //sid 1 (different from rx) - _iface->poke32(U2_REG_TX_CTRL_POLICY, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); + _iface->poke32(_iface->regs.tx_ctrl_clear_state, 1); //reset + _iface->poke32(_iface->regs.tx_ctrl_num_chan, 0); //1 channel + _iface->poke32(_iface->regs.tx_ctrl_report_sid, usrp2_impl::ASYNC_SID); + _iface->poke32(_iface->regs.tx_ctrl_policy, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); + + //setting the cycles per update + const double ups_per_sec = flow_control_hints.cast<double>("ups_per_sec", 100); + const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec); + _iface->poke32(_iface->regs.tx_ctrl_cycles_per_up, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up); + _iface->poke32(_iface->regs.tx_ctrl_cycles_per_up, 0); //cycles per update is disabled + + //setting the packets per update + const double ups_per_fifo = flow_control_hints.cast<double>("ups_per_fifo", 8); + const size_t packets_per_up = size_t(usrp2_impl::sram_bytes/ups_per_fifo/data_transport->get_send_frame_size()); + _iface->poke32(_iface->regs.tx_ctrl_packets_per_up, U2_FLAG_TX_CTRL_UP_ENB | packets_per_up); //init the ddc init_ddc_config(); @@ -105,7 +135,8 @@ usrp2_mboard_impl::usrp2_mboard_impl( } usrp2_mboard_impl::~usrp2_mboard_impl(void){ - /* NOP */ + _iface->poke32(_iface->regs.tx_ctrl_cycles_per_up, 0); + _iface->poke32(_iface->regs.tx_ctrl_packets_per_up, 0); } /*********************************************************************** @@ -128,46 +159,60 @@ void usrp2_mboard_impl::update_clock_config(void){ switch(_clock_config.pps_source){ case clock_config_t::PPS_SMA: pps_flags |= U2_FLAG_TIME64_PPS_SMA; break; case clock_config_t::PPS_MIMO: pps_flags |= U2_FLAG_TIME64_PPS_MIMO; break; - default: throw std::runtime_error("usrp2: unhandled clock configuration pps source"); + default: throw std::runtime_error("unhandled clock configuration pps source"); } //translate pps polarity enums switch(_clock_config.pps_polarity){ case clock_config_t::PPS_POS: pps_flags |= U2_FLAG_TIME64_PPS_POSEDGE; break; case clock_config_t::PPS_NEG: pps_flags |= U2_FLAG_TIME64_PPS_NEGEDGE; break; - default: throw std::runtime_error("usrp2: unhandled clock configuration pps polarity"); + default: throw std::runtime_error("unhandled clock configuration pps polarity"); } //set the pps flags - _iface->poke32(U2_REG_TIME64_FLAGS, pps_flags); + _iface->poke32(_iface->regs.time64_flags, pps_flags); //clock source ref 10mhz - switch(_clock_config.ref_source){ - case clock_config_t::REF_INT : _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x10); break; - case clock_config_t::REF_SMA : _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x1C); break; - case clock_config_t::REF_MIMO: _iface->poke32(U2_REG_MISC_CTRL_CLOCK, 0x15); break; - default: throw std::runtime_error("usrp2: unhandled clock configuration reference source"); - } + switch(_iface->get_rev()){ + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + switch(_clock_config.ref_source){ + case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x12); break; + case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break; + case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break; + default: throw std::runtime_error("unhandled clock configuration reference source"); + } + _clock_ctrl->enable_external_ref(true); //USRP2P has an internal 10MHz TCXO + break; + + case usrp2_iface::USRP2_REV3: + case usrp2_iface::USRP2_REV4: + switch(_clock_config.ref_source){ + case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x10); break; + case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break; + case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break; + default: throw std::runtime_error("unhandled clock configuration reference source"); + } + _clock_ctrl->enable_external_ref(_clock_config.ref_source != clock_config_t::REF_INT); + break; - //clock source ref 10mhz - bool use_external = _clock_config.ref_source != clock_config_t::REF_INT; - _clock_ctrl->enable_external_ref(use_external); + case usrp2_iface::USRP_NXXX: break; + } } void usrp2_mboard_impl::set_time_spec(const time_spec_t &time_spec, bool now){ //set the ticks - _iface->poke32(U2_REG_TIME64_TICKS, time_spec.get_tick_count(get_master_clock_freq())); + _iface->poke32(_iface->regs.time64_ticks, time_spec.get_tick_count(get_master_clock_freq())); //set the flags register boost::uint32_t imm_flags = (now)? U2_FLAG_TIME64_LATCH_NOW : U2_FLAG_TIME64_LATCH_NEXT_PPS; - _iface->poke32(U2_REG_TIME64_IMM, imm_flags); + _iface->poke32(_iface->regs.time64_imm, imm_flags); //set the seconds (latches in all 3 registers) - _iface->poke32(U2_REG_TIME64_SECS, boost::uint32_t(time_spec.get_full_secs())); + _iface->poke32(_iface->regs.time64_secs, boost::uint32_t(time_spec.get_full_secs())); } void usrp2_mboard_impl::handle_overflow(void){ - _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); if (_continuous_streaming){ //re-issue the stream command if already continuous this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); } @@ -175,11 +220,9 @@ void usrp2_mboard_impl::handle_overflow(void){ void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){ _continuous_streaming = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS; - _iface->poke32(U2_REG_RX_CTRL_STREAM_CMD, dsp_type1::calc_stream_cmd_word( - stream_cmd, _recv_frame_size - )); - _iface->poke32(U2_REG_RX_CTRL_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); - _iface->poke32(U2_REG_RX_CTRL_TIME_TICKS, stream_cmd.time_spec.get_tick_count(get_master_clock_freq())); + _iface->poke32(_iface->regs.rx_ctrl_stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd)); + _iface->poke32(_iface->regs.rx_ctrl_time_secs, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); + _iface->poke32(_iface->regs.rx_ctrl_time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq())); } /*********************************************************************** @@ -189,11 +232,10 @@ static const std::string dboard_name = "0"; void usrp2_mboard_impl::get(const wax::obj &key_, wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); - //handle the get request conditioned on the key switch(key.as<mboard_prop_t>()){ case MBOARD_PROP_NAME: - val = str(boost::format("usrp2 mboard%d - rev %s") % _index % _iface->mb_eeprom["rev"]); + val = _iface->get_cname() + " mboard"; return; case MBOARD_PROP_OTHERS: @@ -242,7 +284,7 @@ void usrp2_mboard_impl::get(const wax::obj &key_, wax::obj &val){ case MBOARD_PROP_TIME_NOW:{ usrp2_iface::pair64 time64( - _iface->peek64(U2_REG_TIME64_SECS_RB, U2_REG_TIME64_TICKS_RB) + _iface->peek64(_iface->regs.time64_secs_rb, _iface->regs.time64_ticks_rb) ); val = time_spec_t( time64.first, time64.second, get_master_clock_freq() @@ -270,8 +312,7 @@ void usrp2_mboard_impl::get(const wax::obj &key_, wax::obj &val){ * MBoard Set Properties **********************************************************************/ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){ - - //handle the get request conditioned on the key + //handle the set request conditioned on the key switch(key.as<mboard_prop_t>()){ case MBOARD_PROP_CLOCK_CONFIG: @@ -297,7 +338,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){ //sanity check UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1); //set the mux - _iface->poke32(U2_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( + _iface->poke32(_iface->regs.dsp_rx_mux, dsp_type1::calc_rx_mux_word( _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>() )); return; @@ -308,7 +349,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){ //sanity check UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1); //set the mux - _iface->poke32(U2_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( + _iface->poke32(_iface->regs.dsp_tx_mux, dsp_type1::calc_tx_mux_word( _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>() )); return; diff --git a/host/lib/usrp/usrp2/serdes_ctrl.cpp b/host/lib/usrp/usrp2/serdes_ctrl.cpp index e83dceb96..1cda22f45 100644 --- a/host/lib/usrp/usrp2/serdes_ctrl.cpp +++ b/host/lib/usrp/usrp2/serdes_ctrl.cpp @@ -27,11 +27,11 @@ class usrp2_serdes_ctrl_impl : public usrp2_serdes_ctrl{ public: usrp2_serdes_ctrl_impl(usrp2_iface::sptr iface){ _iface = iface; - _iface->poke32(U2_REG_MISC_CTRL_SERDES, U2_FLAG_MISC_CTRL_SERDES_ENABLE | U2_FLAG_MISC_CTRL_SERDES_RXEN); + _iface->poke32(_iface->regs.misc_ctrl_serdes, U2_FLAG_MISC_CTRL_SERDES_ENABLE | U2_FLAG_MISC_CTRL_SERDES_RXEN); } ~usrp2_serdes_ctrl_impl(void){ - _iface->poke32(U2_REG_MISC_CTRL_SERDES, 0); //power-down + _iface->poke32(_iface->regs.misc_ctrl_serdes, 0); //power-down } private: diff --git a/host/lib/usrp/usrp2/usrp2_clk_regs.hpp b/host/lib/usrp/usrp2/usrp2_clk_regs.hpp new file mode 100644 index 000000000..6c46d0a35 --- /dev/null +++ b/host/lib/usrp/usrp2/usrp2_clk_regs.hpp @@ -0,0 +1,85 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_USRP2_CLK_REGS_HPP +#define INCLUDED_USRP2_CLK_REGS_HPP + +#include "usrp2_iface.hpp" + +class usrp2_clk_regs_t { +public: + usrp2_clk_regs_t(void) { ; } + usrp2_clk_regs_t(usrp2_iface::rev_type rev) { + test = 0; + fpga = 1; + dac = 3; + + switch(rev) { + case usrp2_iface::USRP2_REV3: + exp = 2; + adc = 4; + serdes = 2; + tx_db = 6; + break; + case usrp2_iface::USRP2_REV4: + exp = 5; + adc = 4; + serdes = 2; + tx_db = 6; + break; + case usrp2_iface::USRP_N200: + case usrp2_iface::USRP_N210: + exp = 6; + adc = 2; + serdes = 4; + tx_db = 5; + break; + case usrp2_iface::USRP_NXXX: + //dont throw, it may be unitialized + break; + } + + rx_db = 7; + } + + static int output(int clknum) { return 0x3C + clknum; } + static int div_lo(int clknum) { return 0x48 + 2 * clknum; } + static int div_hi(int clknum) { return 0x49 + 2 * clknum; } + + const static int acounter = 0x04; + const static int bcounter_msb = 0x05; + const static int bcounter_lsb = 0x06; + const static int pll_1 = 0x07; + const static int pll_2 = 0x08; + const static int pll_3 = 0x09; + const static int pll_4 = 0x0A; + const static int ref_counter_msb = 0x0B; + const static int ref_counter_lsb = 0x0C; + const static int pll_5 = 0x0D; + const static int update = 0x5A; + + int test; + int fpga; + int adc; + int dac; + int serdes; + int exp; + int tx_db; + int rx_db; +}; + +#endif //INCLUDED_USRP2_CLK_REGS_HPP diff --git a/host/lib/usrp/usrp2/usrp2_iface.cpp b/host/lib/usrp/usrp2/usrp2_iface.cpp index 09f3432d6..81bc80c88 100644 --- a/host/lib/usrp/usrp2/usrp2_iface.cpp +++ b/host/lib/usrp/usrp2/usrp2_iface.cpp @@ -17,6 +17,7 @@ #include "usrp2_regs.hpp" #include "usrp2_iface.hpp" +#include <uhd/utils/exception.hpp> #include <uhd/utils/assert.hpp> #include <uhd/types/dict.hpp> #include <boost/thread.hpp> @@ -24,6 +25,7 @@ #include <boost/asio.hpp> //used for htonl and ntohl #include <boost/assign/list_of.hpp> #include <boost/format.hpp> +#include <boost/tokenizer.hpp> #include <stdexcept> #include <algorithm> @@ -31,18 +33,6 @@ using namespace uhd; using namespace uhd::usrp; using namespace uhd::transport; -/*! - * FIXME: large timeout, ethernet pause frames... - * - * Use a large timeout to work-around the fact that - * flow-control may throttle outgoing control packets - * due to its use of ethernet pause frames. - * - * This will be fixed when host-based flow control is implemented, - * along with larger incoming send buffers using the on-board SRAM. - */ -static const size_t CONTROL_TIMEOUT_MS = 3000; //3 seconds - class usrp2_iface_impl : public usrp2_iface{ public: /*********************************************************************** @@ -51,16 +41,28 @@ public: usrp2_iface_impl(udp_simple::sptr ctrl_transport){ _ctrl_transport = ctrl_transport; - //check the fpga compatibility number - const boost::uint32_t fpga_compat_num = this->peek32(U2_REG_COMPAT_NUM_RB); + mb_eeprom = mboard_eeprom_t(*this, mboard_eeprom_t::MAP_N100); + switch(this->get_rev()){ + case USRP2_REV3: + case USRP2_REV4: + regs = usrp2_get_regs(false); + break; + + case USRP_NXXX: + case USRP_N200: + case USRP_N210: + regs = usrp2_get_regs(true); + break; + } + + //check the fpga compatibility number + const boost::uint32_t fpga_compat_num = this->peek32(this->regs.compat_num_rb); if (fpga_compat_num != USRP2_FPGA_COMPAT_NUM){ throw std::runtime_error(str(boost::format( "Expected fpga compatibility number %d, but got %d:\n" "The fpga build is not compatible with the host code build." ) % int(USRP2_FPGA_COMPAT_NUM) % fpga_compat_num)); } - - mb_eeprom = mboard_eeprom_t(*this, mboard_eeprom_t::MAP_N100); } ~usrp2_iface_impl(void){ @@ -175,6 +177,58 @@ public: } /*********************************************************************** + * UART + **********************************************************************/ + void write_uart(boost::uint8_t dev, const std::string &buf){ + //first tokenize the string into 20-byte substrings + boost::offset_separator f(20, 1, true, true); + boost::tokenizer<boost::offset_separator> tok(buf, f); + std::vector<std::string> queue(tok.begin(), tok.end()); + + BOOST_FOREACH(std::string item, queue) { + //setup the out data + usrp2_ctrl_data_t out_data; + out_data.id = htonl(USRP2_CTRL_ID_HEY_WRITE_THIS_UART_FOR_ME_BRO); + out_data.data.uart_args.dev = dev; + out_data.data.uart_args.bytes = item.size(); + + //limitation of uart transaction size + UHD_ASSERT_THROW(item.size() <= sizeof(out_data.data.uart_args.data)); + + //copy in the data + std::copy(item.begin(), item.end(), out_data.data.uart_args.data); + + //send and recv + usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data); + UHD_ASSERT_THROW(ntohl(in_data.id) == USRP2_CTRL_ID_MAN_I_TOTALLY_WROTE_THAT_UART_DUDE); + } + } + + std::string read_uart(boost::uint8_t dev){ + int readlen = 20; + std::string result; + while(readlen == 20) { //while we keep receiving full packets + //setup the out data + usrp2_ctrl_data_t out_data; + out_data.id = htonl(USRP2_CTRL_ID_SO_LIKE_CAN_YOU_READ_THIS_UART_BRO); + out_data.data.uart_args.dev = dev; + out_data.data.uart_args.bytes = 20; + + //limitation of uart transaction size + //UHD_ASSERT_THROW(num_bytes <= sizeof(out_data.data.uart_args.data)); + + //send and recv + usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data); + UHD_ASSERT_THROW(ntohl(in_data.id) == USRP2_CTRL_ID_I_HELLA_READ_THAT_UART_DUDE); + readlen = in_data.data.uart_args.bytes; + + //copy out the data + result += std::string((const char *)in_data.data.uart_args.data, (size_t)readlen); + } + return result; + } + +/*********************************************************************** * Send/Recv over control **********************************************************************/ usrp2_ctrl_data_t ctrl_send_and_recv(const usrp2_ctrl_data_t &out_data){ @@ -190,7 +244,7 @@ public: boost::uint8_t usrp2_ctrl_data_in_mem[udp_simple::mtu]; //allocate max bytes for recv const usrp2_ctrl_data_t *ctrl_data_in = reinterpret_cast<const usrp2_ctrl_data_t *>(usrp2_ctrl_data_in_mem); while(true){ - size_t len = _ctrl_transport->recv(boost::asio::buffer(usrp2_ctrl_data_in_mem), CONTROL_TIMEOUT_MS); + size_t len = _ctrl_transport->recv(boost::asio::buffer(usrp2_ctrl_data_in_mem)); if(len >= sizeof(boost::uint32_t) and ntohl(ctrl_data_in->proto_ver) != USRP2_FW_COMPAT_NUM){ throw std::runtime_error(str(boost::format( "Expected protocol compatibility number %d, but got %d:\n" @@ -203,7 +257,28 @@ public: if (len == 0) break; //timeout //didnt get seq or bad packet, continue looking... } - throw std::runtime_error("usrp2 no control response"); + throw std::runtime_error(this->get_cname() + ": no control response"); + } + + rev_type get_rev(void){ + switch (boost::lexical_cast<boost::uint16_t>(mb_eeprom["rev"])){ + case 0x0300: return USRP2_REV3; + case 0x0400: return USRP2_REV4; + case 0x0A00: return USRP_N200; + case 0x0A01: return USRP_N210; + } + return USRP_NXXX; //unknown type + } + + const std::string get_cname(void){ + switch(this->get_rev()){ + case USRP2_REV3: return "USRP2-REV3"; + case USRP2_REV4: return "USRP2-REV4"; + case USRP_N200: return "USRP-N200"; + case USRP_N210: return "USRP-N210"; + case USRP_NXXX: return "USRP-N???"; + } + UHD_THROW_INVALID_CODE_PATH(); } private: @@ -242,7 +317,6 @@ private: UHD_ASSERT_THROW(ntohl(in_data.id) == USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE); return T(ntohl(in_data.data.poke_args.data)); } - }; /*********************************************************************** @@ -251,3 +325,4 @@ private: usrp2_iface::sptr usrp2_iface::make(udp_simple::sptr ctrl_transport){ return usrp2_iface::sptr(new usrp2_iface_impl(ctrl_transport)); } + diff --git a/host/lib/usrp/usrp2/usrp2_iface.hpp b/host/lib/usrp/usrp2/usrp2_iface.hpp index bf36cbf6e..af3ed6c9f 100644 --- a/host/lib/usrp/usrp2/usrp2_iface.hpp +++ b/host/lib/usrp/usrp2/usrp2_iface.hpp @@ -25,7 +25,9 @@ #include <boost/utility.hpp> #include <boost/cstdint.hpp> #include <utility> +#include <string> #include "fw_common.h" +#include "usrp2_regs.hpp" /*! * The usrp2 interface class: @@ -104,6 +106,30 @@ public: bool readback ) = 0; + virtual void write_uart(boost::uint8_t dev, const std::string &buf) = 0; + + virtual std::string read_uart(boost::uint8_t dev) = 0; + + //! The list of possible revision types + enum rev_type { + USRP2_REV3 = 3, + USRP2_REV4 = 4, + USRP_N200 = 200, + USRP_N210 = 210, + USRP_NXXX = 0 + }; + + //! Get the revision type for this device + virtual rev_type get_rev(void) = 0; + + //! Get the canonical name for this device + virtual const std::string get_cname(void) = 0; + + /*! + * Register map selected from USRP2/USRP2+. + */ + usrp2_regs_t regs; + //motherboard eeprom map structure uhd::usrp::mboard_eeprom_t mb_eeprom; }; diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index 5f549c4fd..610e2f404 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -17,7 +17,7 @@ #include "usrp2_impl.hpp" #include <uhd/transport/if_addrs.hpp> -#include <uhd/transport/udp_simple.hpp> +#include <uhd/transport/udp_zero_copy.hpp> #include <uhd/usrp/device_props.hpp> #include <uhd/utils/assert.hpp> #include <uhd/utils/static.hpp> @@ -36,9 +36,6 @@ using namespace uhd::usrp; using namespace uhd::transport; namespace asio = boost::asio; -//! wait this long for a control response when discovering devices -static const size_t DISCOVERY_TIMEOUT_MS = 100; - /*********************************************************************** * Helper Functions **********************************************************************/ @@ -100,7 +97,7 @@ static uhd::device_addrs_t usrp2_find(const device_addr_t &hint){ boost::uint8_t usrp2_ctrl_data_in_mem[udp_simple::mtu]; //allocate max bytes for recv const usrp2_ctrl_data_t *ctrl_data_in = reinterpret_cast<const usrp2_ctrl_data_t *>(usrp2_ctrl_data_in_mem); while(true){ - size_t len = udp_transport->recv(asio::buffer(usrp2_ctrl_data_in_mem), DISCOVERY_TIMEOUT_MS); + size_t len = udp_transport->recv(asio::buffer(usrp2_ctrl_data_in_mem)); //std::cout << len << "\n"; if (len > offsetof(usrp2_ctrl_data_t, data) and ntohl(ctrl_data_in->id) == USRP2_CTRL_ID_WAZZUP_DUDE){ //make a boost asio ipv4 with the raw addr in host byte order @@ -147,7 +144,7 @@ static device::sptr usrp2_make(const device_addr_t &device_addr){ //create a ctrl and data transport for each address std::vector<udp_simple::sptr> ctrl_transports; - std::vector<udp_zero_copy::sptr> data_transports; + std::vector<zero_copy_if::sptr> data_transports; BOOST_FOREACH(const std::string &addr, std::split_string(device_addr["addr"])){ ctrl_transports.push_back(udp_simple::make_connected( @@ -160,7 +157,7 @@ static device::sptr usrp2_make(const device_addr_t &device_addr){ //create the usrp2 implementation guts return device::sptr( - new usrp2_impl(ctrl_transports, data_transports) + new usrp2_impl(ctrl_transports, data_transports, device_addr) ); } @@ -173,7 +170,8 @@ UHD_STATIC_BLOCK(register_usrp2_device){ **********************************************************************/ usrp2_impl::usrp2_impl( std::vector<udp_simple::sptr> ctrl_transports, - std::vector<udp_zero_copy::sptr> data_transports + std::vector<zero_copy_if::sptr> data_transports, + const device_addr_t &flow_control_hints ): _data_transports(data_transports) { @@ -192,7 +190,9 @@ usrp2_impl::usrp2_impl( //create a new mboard handler for each control transport for(size_t i = 0; i < ctrl_transports.size(); i++){ _mboards.push_back(usrp2_mboard_impl::sptr(new usrp2_mboard_impl( - i, ctrl_transports[i], this->get_max_recv_samps_per_packet() + i, ctrl_transports[i], data_transports[i], + this->get_max_recv_samps_per_packet(), + flow_control_hints ))); //use an empty name when there is only one mboard std::string name = (ctrl_transports.size() > 1)? boost::lexical_cast<std::string>(i) : ""; @@ -217,8 +217,8 @@ void usrp2_impl::get(const wax::obj &key_, wax::obj &val){ //handle the get request conditioned on the key switch(key.as<device_prop_t>()){ case DEVICE_PROP_NAME: - if (_mboards.size() > 1) val = std::string("usrp2 mimo device"); - else val = std::string("usrp2 device"); + if (_mboards.size() > 1) val = std::string("USRP-NXXX mimo device"); + else val = std::string("USRP-NXXX device"); return; case DEVICE_PROP_MBOARD: diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index 71f52878c..aa8eb0155 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -21,6 +21,7 @@ #include "usrp2_iface.hpp" #include "clock_ctrl.hpp" #include "codec_ctrl.hpp" +#include "gps_ctrl.hpp" #include "serdes_ctrl.hpp" #include <uhd/device.hpp> #include <uhd/utils/pimpl.hpp> @@ -84,7 +85,9 @@ public: usrp2_mboard_impl( size_t index, uhd::transport::udp_simple::sptr, - size_t recv_frame_size + uhd::transport::zero_copy_if::sptr, + size_t recv_samps_per_packet, + const uhd::device_addr_t &flow_control_hints ); ~usrp2_mboard_impl(void); @@ -96,7 +99,6 @@ public: private: size_t _index; - const size_t _recv_frame_size; bool _continuous_streaming; //interfaces @@ -104,6 +106,7 @@ private: usrp2_clock_ctrl::sptr _clock_ctrl; usrp2_codec_ctrl::sptr _codec_ctrl; usrp2_serdes_ctrl::sptr _serdes_ctrl; + usrp2_gps_ctrl::sptr _gps_ctrl; //properties for this mboard void get(const wax::obj &, wax::obj &); @@ -130,6 +133,9 @@ private: wax_obj_proxy::sptr _rx_codec_proxy; wax_obj_proxy::sptr _tx_codec_proxy; + void rx_codec_set_gain(float, const std::string &); + uhd::dict<std::string, float> _codec_rx_gains; + //properties interface for rx dboard void rx_dboard_get(const wax::obj &, wax::obj &); void rx_dboard_set(const wax::obj &, const wax::obj &); @@ -173,14 +179,20 @@ private: */ class usrp2_impl : public uhd::device{ public: + static const size_t sram_bytes = size_t(1 << 20); + static const boost::uint32_t RECV_SID = 1; + static const boost::uint32_t ASYNC_SID = 2; + /*! * Create a new usrp2 impl base. * \param ctrl_transports the udp transports for control * \param data_transports the udp transports for data + * \param flow_control_hints optional flow control params */ usrp2_impl( std::vector<uhd::transport::udp_simple::sptr> ctrl_transports, - std::vector<uhd::transport::udp_zero_copy::sptr> data_transports + std::vector<uhd::transport::zero_copy_if::sptr> data_transports, + const uhd::device_addr_t &flow_control_hints ); ~usrp2_impl(void); @@ -210,7 +222,7 @@ private: uhd::dict<std::string, usrp2_mboard_impl::sptr> _mboard_dict; //io impl methods and members - std::vector<uhd::transport::udp_zero_copy::sptr> _data_transports; + std::vector<uhd::transport::zero_copy_if::sptr> _data_transports; uhd::otw_type_t _rx_otw_type, _tx_otw_type; UHD_PIMPL_DECL(io_impl) _io_impl; void io_init(void); diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp new file mode 100644 index 000000000..dd0433816 --- /dev/null +++ b/host/lib/usrp/usrp2/usrp2_regs.cpp @@ -0,0 +1,102 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include "usrp2_regs.hpp" +#include "usrp2_iface.hpp" + +int sr_addr(int misc_output_base, int sr) { + return misc_output_base + 4 * sr; +} + +usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) { + + //how about you just make this dependent on hw_rev instead of doing the init before main, and give up the const globals, since the application won't ever need both. + const int misc_output_base = (use_n2xx_map) ? USRP2P_MISC_OUTPUT_BASE : USRP2_MISC_OUTPUT_BASE, + gpio_base = (use_n2xx_map) ? USRP2P_GPIO_BASE : USRP2_GPIO_BASE, + atr_base = (use_n2xx_map) ? USRP2P_ATR_BASE : USRP2_ATR_BASE, + bp_base = (use_n2xx_map) ? USRP2P_BP_STATUS_BASE : USRP2_BP_STATUS_BASE; + + usrp2_regs_t x; + x.sr_misc = 0; + x.sr_tx_prot_eng = 32; + x.sr_rx_prot_eng = 48; + x.sr_buffer_pool_ctrl = 64; + x.sr_udp_sm = 96; + x.sr_tx_dsp = 208; + x.sr_tx_ctrl = 224; + x.sr_rx_dsp = 160; + x.sr_rx_ctrl = 176; + x.sr_time64 = 192; + x.sr_simtimer = 198; + x.sr_last = 255; + x.misc_ctrl_clock = sr_addr(misc_output_base, 0); + x.misc_ctrl_serdes = sr_addr(misc_output_base, 1); + x.misc_ctrl_adc = sr_addr(misc_output_base, 2); + x.misc_ctrl_leds = sr_addr(misc_output_base, 3); + x.misc_ctrl_phy = sr_addr(misc_output_base, 4); + x.misc_ctrl_dbg_mux = sr_addr(misc_output_base, 5); + x.misc_ctrl_ram_page = sr_addr(misc_output_base, 6); + x.misc_ctrl_flush_icache = sr_addr(misc_output_base, 7); + x.misc_ctrl_led_src = sr_addr(misc_output_base, 8); + x.time64_secs = sr_addr(misc_output_base, x.sr_time64 + 0); + x.time64_ticks = sr_addr(misc_output_base, x.sr_time64 + 1); + x.time64_flags = sr_addr(misc_output_base, x.sr_time64 + 2); + x.time64_imm = sr_addr(misc_output_base, x.sr_time64 + 3); + x.time64_tps = sr_addr(misc_output_base, x.sr_time64 + 4); + x.time64_secs_rb = bp_base + 4*10; + x.time64_ticks_rb = bp_base + 4*11; + x.compat_num_rb = bp_base + 4*12; + x.dsp_tx_freq = sr_addr(misc_output_base, x.sr_tx_dsp + 0); + x.dsp_tx_scale_iq = sr_addr(misc_output_base, x.sr_tx_dsp + 1); + x.dsp_tx_interp_rate = sr_addr(misc_output_base, x.sr_tx_dsp + 2); + x.dsp_tx_mux = sr_addr(misc_output_base, x.sr_tx_dsp + 4); + x.dsp_rx_freq = sr_addr(misc_output_base, x.sr_rx_dsp + 0); + x.dsp_rx_scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp + 1); + x.dsp_rx_decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp + 2); + x.dsp_rx_dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp + 3); + x.dsp_rx_dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp + 4); + x.dsp_rx_mux = sr_addr(misc_output_base, x.sr_rx_dsp + 5); + x.gpio_io = gpio_base + 0; + x.gpio_ddr = gpio_base + 4; + x.gpio_tx_sel = gpio_base + 8; + x.gpio_rx_sel = gpio_base + 12; + x.atr_idle_txside = atr_base + 0; + x.atr_idle_rxside = atr_base + 2; + x.atr_intx_txside = atr_base + 4; + x.atr_intx_rxside = atr_base + 6; + x.atr_inrx_txside = atr_base + 8; + x.atr_inrx_rxside = atr_base + 10; + x.atr_full_txside = atr_base + 12; + x.atr_full_rxside = atr_base + 14; + x.rx_ctrl_stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl + 0); + x.rx_ctrl_time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl + 1); + x.rx_ctrl_time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl + 2); + x.rx_ctrl_clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl + 3); + x.rx_ctrl_vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl + 4); + x.rx_ctrl_vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl + 5); + x.rx_ctrl_vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl + 6); + x.rx_ctrl_nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl + 7); + x.rx_ctrl_nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl + 8); + x.tx_ctrl_num_chan = sr_addr(misc_output_base, x.sr_tx_ctrl + 0); + x.tx_ctrl_clear_state = sr_addr(misc_output_base, x.sr_tx_ctrl + 1); + x.tx_ctrl_report_sid = sr_addr(misc_output_base, x.sr_tx_ctrl + 2); + x.tx_ctrl_policy = sr_addr(misc_output_base, x.sr_tx_ctrl + 3); + x.tx_ctrl_cycles_per_up = sr_addr(misc_output_base, x.sr_tx_ctrl + 4); + x.tx_ctrl_packets_per_up = sr_addr(misc_output_base, x.sr_tx_ctrl + 5); + + return x; +} diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 064ad4e95..9936d634a 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -18,6 +18,93 @@ #ifndef INCLUDED_USRP2_REGS_HPP #define INCLUDED_USRP2_REGS_HPP +#include <boost/cstdint.hpp> + +#define USRP2_MISC_OUTPUT_BASE 0xD400 +#define USRP2_GPIO_BASE 0xC800 +#define USRP2_ATR_BASE 0xE400 +#define USRP2_BP_STATUS_BASE 0xCC00 + +#define USRP2P_MISC_OUTPUT_BASE 0x2000 +#define USRP2P_GPIO_BASE 0x3200 +#define USRP2P_ATR_BASE 0x3800 +#define USRP2P_BP_STATUS_BASE 0x3300 + +typedef struct { + int sr_misc; + int sr_tx_prot_eng; + int sr_rx_prot_eng; + int sr_buffer_pool_ctrl; + int sr_udp_sm; + int sr_tx_dsp; + int sr_tx_ctrl; + int sr_rx_dsp; + int sr_rx_ctrl; + int sr_time64; + int sr_simtimer; + int sr_last; + int misc_ctrl_clock; + int misc_ctrl_serdes; + int misc_ctrl_adc; + int misc_ctrl_leds; + int misc_ctrl_phy; + int misc_ctrl_dbg_mux; + int misc_ctrl_ram_page; + int misc_ctrl_flush_icache; + int misc_ctrl_led_src; + int time64_secs; // value to set absolute secs to on next PPS + int time64_ticks; // value to set absolute ticks to on next PPS + int time64_flags; // flags -- see chart below + int time64_imm; // set immediate (0=latch on next pps, 1=latch immediate, default=0) + int time64_tps; // ticks per second rollover count + int time64_secs_rb; + int time64_ticks_rb; + int compat_num_rb; + int dsp_tx_freq; + int dsp_tx_scale_iq; + int dsp_tx_interp_rate; + int dsp_tx_mux; + int dsp_rx_freq; + int dsp_rx_scale_iq; + int dsp_rx_decim_rate; + int dsp_rx_dcoffset_i; + int dsp_rx_dcoffset_q; + int dsp_rx_mux; + int gpio_base; + int gpio_io; + int gpio_ddr; + int gpio_tx_sel; + int gpio_rx_sel; + int atr_base; + int atr_idle_txside; + int atr_idle_rxside; + int atr_intx_txside; + int atr_intx_rxside; + int atr_inrx_txside; + int atr_inrx_rxside; + int atr_full_txside; + int atr_full_rxside; + int rx_ctrl_stream_cmd; + int rx_ctrl_time_secs; + int rx_ctrl_time_ticks; + int rx_ctrl_clear_overrun; + int rx_ctrl_vrt_header; + int rx_ctrl_vrt_stream_id; + int rx_ctrl_vrt_trailer; + int rx_ctrl_nsamps_per_pkt; + int rx_ctrl_nchannels; + int tx_ctrl_num_chan; + int tx_ctrl_clear_state; + int tx_ctrl_report_sid; + int tx_ctrl_policy; + int tx_ctrl_cycles_per_up; + int tx_ctrl_packets_per_up; +} usrp2_regs_t; + +extern const usrp2_regs_t usrp2_regs; //the register definitions, set in usrp2_regs.cpp and usrp2p_regs.cpp + +usrp2_regs_t usrp2_get_regs(bool); + //////////////////////////////////////////////////// // Settings Bus, Slave #7, Not Byte Addressable! // @@ -25,27 +112,12 @@ // 1KB of address space (== 256 32-bit write-only regs) -#define MISC_OUTPUT_BASE 0xD400 +//#define MISC_OUTPUT_BASE 0xD400 //#define TX_PROTOCOL_ENGINE_BASE 0xD480 //#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 //#define BUFFER_POOL_CTRL_BASE 0xD500 //#define LAST_SETTING_REG 0xD7FC // last valid setting register -#define SR_MISC 0 -#define SR_TX_PROT_ENG 32 -#define SR_RX_PROT_ENG 48 -#define SR_BUFFER_POOL_CTRL 64 -#define SR_UDP_SM 96 -#define SR_TX_DSP 208 -#define SR_TX_CTRL 224 -#define SR_RX_DSP 160 -#define SR_RX_CTRL 176 -#define SR_TIME64 192 -#define SR_SIMTIMER 198 -#define SR_LAST 255 - -#define _SR_ADDR(sr) ((MISC_OUTPUT_BASE) + (4*(sr))) - ///////////////////////////////////////////////// // SPI Slave Constants //////////////////////////////////////////////// @@ -58,20 +130,11 @@ #define SPI_SS_TX_DAC 32 #define SPI_SS_TX_ADC 64 #define SPI_SS_TX_DB 128 +#define SPI_SS_ADS62P44 256 //for usrp2p ///////////////////////////////////////////////// // Misc Control //////////////////////////////////////////////// -#define U2_REG_MISC_CTRL_CLOCK _SR_ADDR(0) -#define U2_REG_MISC_CTRL_SERDES _SR_ADDR(1) -#define U2_REG_MISC_CTRL_ADC _SR_ADDR(2) -#define U2_REG_MISC_CTRL_LEDS _SR_ADDR(3) -#define U2_REG_MISC_CTRL_PHY _SR_ADDR(4) // LSB is reset line to eth phy -#define U2_REG_MISC_CTRL_DBG_MUX _SR_ADDR(5) -#define U2_REG_MISC_CTRL_RAM_PAGE _SR_ADDR(6) // FIXME should go somewhere else... -#define U2_REG_MISC_CTRL_FLUSH_ICACHE _SR_ADDR(7) // Flush the icache -#define U2_REG_MISC_CTRL_LED_SRC _SR_ADDR(8) // HW or SW control for LEDs - #define U2_FLAG_MISC_CTRL_SERDES_ENABLE 8 #define U2_FLAG_MISC_CTRL_SERDES_PRBSEN 4 #define U2_FLAG_MISC_CTRL_SERDES_LOOPEN 2 @@ -99,15 +162,6 @@ * * </pre> */ -#define U2_REG_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS -#define U2_REG_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS -#define U2_REG_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above -#define U2_REG_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) -#define U2_REG_TIME64_TPS _SR_ADDR(SR_TIME64 + 4) // the ticks per second rollover count - -#define U2_REG_TIME64_SECS_RB (0xCC00 + 4*10) -#define U2_REG_TIME64_TICKS_RB (0xCC00 + 4*11) -#define U2_REG_COMPAT_NUM_RB (0xCC00 + 4*12) //pps flags (see above) #define U2_FLAG_TIME64_PPS_NEGEDGE (0 << 0) @@ -121,34 +175,72 @@ ///////////////////////////////////////////////// // DSP TX Regs //////////////////////////////////////////////// -#define U2_REG_DSP_TX_FREQ _SR_ADDR(SR_TX_DSP + 0) -#define U2_REG_DSP_TX_SCALE_IQ _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q} -#define U2_REG_DSP_TX_INTERP_RATE _SR_ADDR(SR_TX_DSP + 2) -#define U2_REG_DSP_TX_MUX _SR_ADDR(SR_TX_DSP + 4) + + /*! + * \brief output mux configuration. + * + * <pre> + * 3 2 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-------------------------------+-------+-------+-------+-------+ + * | | DAC1 | DAC0 | + * +-------------------------------+-------+-------+-------+-------+ + * + * There are N DUCs (1 now) with complex inputs and outputs. + * There are two DACs. + * + * Each 4-bit DACx field specifies the source for the DAC + * Each subfield is coded like this: + * + * 3 2 1 0 + * +-------+ + * | N | + * +-------+ + * + * N specifies which DUC output is connected to this DAC. + * + * N which interp output + * --- ------------------- + * 0 DUC 0 I + * 1 DUC 0 Q + * 2 DUC 1 I + * 3 DUC 1 Q + * F All Zeros + * + * The default value is 0x10 + * </pre> + */ + ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// -#define U2_REG_DSP_RX_FREQ _SR_ADDR(SR_RX_DSP + 0) -#define U2_REG_DSP_RX_SCALE_IQ _SR_ADDR(SR_RX_DSP + 1) // {scale_i,scale_q} -#define U2_REG_DSP_RX_DECIM_RATE _SR_ADDR(SR_RX_DSP + 2) -#define U2_REG_DSP_RX_DCOFFSET_I _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits, - // otherwise it is automatic -#define U2_REG_DSP_RX_DCOFFSET_Q _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits -#define U2_REG_DSP_RX_MUX _SR_ADDR(SR_RX_DSP + 5) // called adc_mux in dsp_core_rx.v + + /*! + * \brief input mux configuration. + * + * This determines which ADC (or constant zero) is connected to + * each DDC input. There are N DDCs (1 now). Each has two inputs. + * + * <pre> + * Mux value: + * + * 3 2 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-------+-------+-------+-------+-------+-------+-------+-------+ + * | |Q0 |I0 | + * +-------+-------+-------+-------+-------+-------+-------+-------+ + * + * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero) + * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero) + * + * The default value is 0x4 + * </pre> + */ //////////////////////////////////////////////// // GPIO, Slave 4 //////////////////////////////////////////////// -// -// These go to the daughterboard i/o pins -// -#define U2_REG_GPIO_BASE 0xC800 - -#define U2_REG_GPIO_IO U2_REG_GPIO_BASE + 0 // 32 bits, gpio io pins (tx high 16 bits, rx low 16 bits) -#define U2_REG_GPIO_DDR U2_REG_GPIO_BASE + 4 // 32 bits, gpio ddr, 1 means output (tx high 16 bits, rx low 16 bits) -#define U2_REG_GPIO_TX_SEL U2_REG_GPIO_BASE + 8 // 16 2-bit fields select which source goes to TX DB -#define U2_REG_GPIO_RX_SEL U2_REG_GPIO_BASE + 12 // 16 2-bit fields select which source goes to RX DB // each 2-bit sel field is layed out this way #define U2_FLAG_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register @@ -159,43 +251,39 @@ /////////////////////////////////////////////////// // ATR Controller, Slave 11 //////////////////////////////////////////////// -#define U2_REG_ATR_BASE 0xE400 -#define U2_REG_ATR_IDLE_TXSIDE U2_REG_ATR_BASE + 0 -#define U2_REG_ATR_IDLE_RXSIDE U2_REG_ATR_BASE + 2 -#define U2_REG_ATR_INTX_TXSIDE U2_REG_ATR_BASE + 4 -#define U2_REG_ATR_INTX_RXSIDE U2_REG_ATR_BASE + 6 -#define U2_REG_ATR_INRX_TXSIDE U2_REG_ATR_BASE + 8 -#define U2_REG_ATR_INRX_RXSIDE U2_REG_ATR_BASE + 10 -#define U2_REG_ATR_FULL_TXSIDE U2_REG_ATR_BASE + 12 -#define U2_REG_ATR_FULL_RXSIDE U2_REG_ATR_BASE + 14 /////////////////////////////////////////////////// // RX CTRL regs /////////////////////////////////////////////////// // The following 3 are logically a single command register. // They are clocked into the underlying fifo when time_ticks is written. -#define U2_REG_RX_CTRL_STREAM_CMD _SR_ADDR(SR_RX_CTRL + 0) // {now, chain, num_samples(30) -#define U2_REG_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1) -#define U2_REG_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2) +//#define U2_REG_RX_CTRL_STREAM_CMD _SR_ADDR(SR_RX_CTRL + 0) // {now, chain, num_samples(30) +//#define U2_REG_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1) +//#define U2_REG_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2) -#define U2_REG_RX_CTRL_CLEAR_OVERRUN _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun -#define U2_REG_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter -#define U2_REG_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet. -#define U2_REG_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6) -#define U2_REG_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7) -#define U2_REG_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources +//#define U2_REG_RX_CTRL_CLEAR_STATE _SR_ADDR(SR_RX_CTRL + 3) +//#define U2_REG_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter +//#define U2_REG_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet. +//#define U2_REG_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6) +//#define U2_REG_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7) +//#define U2_REG_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources /////////////////////////////////////////////////// // TX CTRL regs /////////////////////////////////////////////////// -#define U2_REG_TX_CTRL_NUM_CHAN _SR_ADDR(SR_TX_CTRL + 0) -#define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) -#define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) -#define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3) +//#define U2_REG_TX_CTRL_NUM_CHAN _SR_ADDR(SR_TX_CTRL + 0) +//#define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) +//#define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) +//#define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3) +//#define U2_REG_TX_CTRL_CYCLES_PER_UP _SR_ADDR(SR_TX_CTRL + 4) +//#define U2_REG_TX_CTRL_PACKETS_PER_UP _SR_ADDR(SR_TX_CTRL + 5) #define U2_FLAG_TX_CTRL_POLICY_WAIT (0x1 << 0) #define U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET (0x1 << 1) #define U2_FLAG_TX_CTRL_POLICY_NEXT_BURST (0x1 << 2) +//enable flag for registers: cycles and packets per update packet +#define U2_FLAG_TX_CTRL_UP_ENB (1ul << 31) + #endif /* INCLUDED_USRP2_REGS_HPP */ diff --git a/host/lib/usrp/wrapper_utils.hpp b/host/lib/usrp/wrapper_utils.hpp index 6f9fdbfca..a7b5c5da6 100644 --- a/host/lib/usrp/wrapper_utils.hpp +++ b/host/lib/usrp/wrapper_utils.hpp @@ -30,7 +30,7 @@ static inline uhd::freq_range_t add_dsp_shift( wax::obj dsp ){ double codec_rate = dsp[uhd::usrp::DSP_PROP_CODEC_RATE].as<double>(); - return uhd::freq_range_t(range.min - codec_rate/2.0, range.max + codec_rate/2.0); + return uhd::freq_range_t(range.start() - codec_rate/2.0, range.stop() + codec_rate/2.0); } static inline void do_samp_rate_warning_message( diff --git a/host/lib/utils/gain_group.cpp b/host/lib/utils/gain_group.cpp index 54146726a..11bbb8c0a 100644 --- a/host/lib/utils/gain_group.cpp +++ b/host/lib/utils/gain_group.cpp @@ -32,7 +32,7 @@ static const bool verbose = false; static bool compare_by_step_size( const size_t &rhs, const size_t &lhs, std::vector<gain_fcns_t> &fcns ){ - return fcns.at(rhs).get_range().step > fcns.at(lhs).get_range().step; + return fcns.at(rhs).get_range().step() > fcns.at(lhs).get_range().step(); } /*! @@ -69,11 +69,11 @@ public: float overall_min = 0, overall_max = 0, overall_step = 0; BOOST_FOREACH(const gain_fcns_t &fcns, get_all_fcns()){ const gain_range_t range = fcns.get_range(); - overall_min += range.min; - overall_max += range.max; + overall_min += range.start(); + overall_max += range.stop(); //the overall step is the min (zero is invalid, first run) - if (overall_step == 0) overall_step = range.step; - overall_step = std::min(overall_step, range.step); + if (overall_step == 0) overall_step = range.step(); + overall_step = std::min(overall_step, range.step()); } return gain_range_t(overall_min, overall_max, overall_step); } @@ -97,7 +97,7 @@ public: //get the max step size among the gains float max_step = 0; BOOST_FOREACH(const gain_fcns_t &fcns, all_fcns){ - max_step = std::max(max_step, fcns.get_range().step); + max_step = std::max(max_step, fcns.get_range().step()); } //create gain bucket to distribute power @@ -108,7 +108,7 @@ public: BOOST_FOREACH(const gain_fcns_t &fcns, all_fcns){ const gain_range_t range = fcns.get_range(); gain_bucket.push_back(floor_step(std::clip( - gain_left_to_distribute, range.min, range.max + gain_left_to_distribute, range.start(), range.stop() ), max_step)); gain_left_to_distribute -= gain_bucket.back(); } @@ -123,8 +123,8 @@ public: boost::bind(&compare_by_step_size, _1, _2, all_fcns) ); UHD_ASSERT_THROW( - all_fcns.at(indexes_step_size_dec.front()).get_range().step >= - all_fcns.at(indexes_step_size_dec.back()).get_range().step + all_fcns.at(indexes_step_size_dec.front()).get_range().step() >= + all_fcns.at(indexes_step_size_dec.back()).get_range().step() ); //distribute the remainder (less than max step) @@ -132,8 +132,8 @@ public: BOOST_FOREACH(size_t i, indexes_step_size_dec){ const gain_range_t range = all_fcns.at(i).get_range(); float additional_gain = floor_step(std::clip( - gain_bucket.at(i) + gain_left_to_distribute, range.min, range.max - ), range.step) - gain_bucket.at(i); + gain_bucket.at(i) + gain_left_to_distribute, range.start(), range.stop() + ), range.step()) - gain_bucket.at(i); gain_bucket.at(i) += additional_gain; gain_left_to_distribute -= additional_gain; } |