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-rw-r--r--host/lib/usrp/dboard/db_rfx.cpp39
-rw-r--r--host/lib/usrp/dboard/db_xcvr2450.cpp13
-rw-r--r--host/lib/usrp/usrp_e100/clock_ctrl.cpp16
-rw-r--r--host/lib/usrp/usrp_e100/clock_ctrl.hpp12
-rw-r--r--host/lib/usrp/usrp_e100/dboard_iface.cpp8
5 files changed, 65 insertions, 23 deletions
diff --git a/host/lib/usrp/dboard/db_rfx.cpp b/host/lib/usrp/dboard/db_rfx.cpp
index 725b5cc03..f938c749a 100644
--- a/host/lib/usrp/dboard/db_rfx.cpp
+++ b/host/lib/usrp/dboard/db_rfx.cpp
@@ -312,7 +312,8 @@ double rfx_xcvr::set_lo_freq(
(8, adf4360_regs_t::BAND_SELECT_CLOCK_DIV_8)
;
- double actual_freq=0, ref_freq = this->get_iface()->get_clock_rate(unit);
+ std::vector<double> clock_rates = this->get_iface()->get_clock_rates(unit);
+ double actual_freq = 0, ref_freq = 0;
int R=0, BS=0, P=0, B=0, A=0;
/*
@@ -325,27 +326,31 @@ double rfx_xcvr::set_lo_freq(
* fvco = [P*B + A] * fref/R
* fvco*R/fref = P*B + A = N
*/
- for(R = 2; R <= 32; R+=2){
- BOOST_FOREACH(BS, bandsel_to_enum.keys()){
- if (ref_freq/R/BS > 1e6) continue; //constraint on band select clock
- BOOST_FOREACH(P, prescaler_to_enum.keys()){
- //calculate B and A from N
- double N = target_freq*R/ref_freq;
- B = int(std::floor(N/P));
- A = boost::math::iround(N - P*B);
- if (B < A or B > 8191 or B < 3 or A > 31) continue; //constraints on A, B
- //calculate the actual frequency
- actual_freq = double(P*B + A)*ref_freq/R;
- if (actual_freq/P > 300e6) continue; //constraint on prescaler output
- //constraints met: exit loop
- goto done_loop;
+ for(R = 1; R <= 32; R+=((R==1)?1:2)){
+ BOOST_FOREACH(ref_freq, uhd::reversed(uhd::sorted(clock_rates))){
+ BOOST_FOREACH(BS, bandsel_to_enum.keys()){
+ if (ref_freq/R/BS > 1e6) continue; //constraint on band select clock
+ BOOST_FOREACH(P, prescaler_to_enum.keys()){
+ //calculate B and A from N
+ double N = target_freq*R/ref_freq;
+ B = int(std::floor(N/P));
+ A = boost::math::iround(N - P*B);
+ if (B < A or B > 8191 or B < 3 or A > 31) continue; //constraints on A, B
+ //calculate the actual frequency
+ actual_freq = double(P*B + A)*ref_freq/R;
+ if (actual_freq/P > 300e6) continue; //constraint on prescaler output
+ //constraints met: exit loop
+ goto done_loop;
+ }
}
}
} done_loop:
if (rfx_debug) std::cerr << boost::format(
- "RFX tune: R=%d, BS=%d, P=%d, B=%d, A=%d, DIV2=%d"
- ) % R % BS % P % B % A % int(_div2[unit] && (!is_rx_rfx400)) << std::endl;
+ "RFX tune: R=%d, BS=%d, P=%d, B=%d, A=%d, DIV2=%d, ref=%fMHz"
+ ) % R % BS % P % B % A % int(_div2[unit] && (!is_rx_rfx400)) % (ref_freq/1e6) << std::endl;
+
+ this->get_iface()->set_clock_rate(unit, ref_freq);
//load the register values
adf4360_regs_t regs;
diff --git a/host/lib/usrp/dboard/db_xcvr2450.cpp b/host/lib/usrp/dboard/db_xcvr2450.cpp
index 9d25b30a5..70b0bbabd 100644
--- a/host/lib/usrp/dboard/db_xcvr2450.cpp
+++ b/host/lib/usrp/dboard/db_xcvr2450.cpp
@@ -152,12 +152,21 @@ private:
* \return the rssi in dB
*/
double get_rssi(void){
+ //*FIXME* RSSI depends on LNA Gain Setting (datasheet pg 16 top middle chart)
+ double max_power;
+ switch(_max2829_regs.rx_lna_gain){
+ case 0:
+ case 1: max_power = 0; break;
+ case 2: max_power = -15; break;
+ case 3: max_power = -30.5; break;
+ }
+
//constants for the rssi calculation
static const double min_v = 0.5, max_v = 2.5;
static const double rssi_dyn_range = 60;
//calculate the rssi from the voltage
double voltage = this->get_iface()->read_aux_adc(dboard_iface::UNIT_RX, dboard_iface::AUX_ADC_B);
- return rssi_dyn_range*(voltage - min_v)/(max_v - min_v);
+ return max_power - rssi_dyn_range*(voltage - min_v)/(max_v - min_v);
}
};
@@ -621,7 +630,7 @@ void xcvr2450::rx_get(const wax::obj &key_, wax::obj &val){
if (key.name == "lo_locked")
val = sensor_value_t("LO", this->get_locked(), "locked", "unlocked");
else if (key.name == "rssi")
- val = sensor_value_t("RSSI", this->get_rssi(), "dB");
+ val = sensor_value_t("RSSI", this->get_rssi(), "dBm");
else
UHD_THROW_INVALID_CODE_PATH();
return;
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
index b0bf20b67..1ac2b804c 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
@@ -287,6 +287,9 @@ public:
if (_out_rate == rate) return;
if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate);
else set_clock_settings_with_internal_vco(rate);
+ //clock rate changed! update dboard clocks and FPGA ticks per second
+ set_rx_dboard_clock_rate(rate);
+ set_tx_dboard_clock_rate(rate);
_iface->poke32(UE_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate()));
}
@@ -328,6 +331,7 @@ public:
void set_rx_dboard_clock_rate(double rate){
assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate");
+ _rx_clock_rate = rate;
size_t divider = size_t(this->_chan_rate/rate);
//set the divider registers
set_clock_divider(divider,
@@ -340,6 +344,10 @@ public:
this->latch_regs();
}
+ double get_rx_clock_rate(void){
+ return _rx_clock_rate;
+ }
+
/***********************************************************************
* TX Dboard Clock Control (output 6, divider 2)
**********************************************************************/
@@ -358,6 +366,7 @@ public:
void set_tx_dboard_clock_rate(double rate){
assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate");
+ _tx_clock_rate = rate;
size_t divider = size_t(this->_chan_rate/rate);
//set the divider registers
set_clock_divider(divider,
@@ -369,7 +378,11 @@ public:
this->send_reg(0x197);
this->latch_regs();
}
-
+
+ double get_tx_clock_rate(void){
+ return _tx_clock_rate;
+ }
+
/***********************************************************************
* Clock reference control
**********************************************************************/
@@ -401,6 +414,7 @@ private:
ad9522_regs_t _ad9522_regs;
double _out_rate; //rate at the fpga and codec
double _chan_rate; //rate before final dividers
+ double _rx_clock_rate, _tx_clock_rate;
void latch_regs(void){
_ad9522_regs.io_update = 1;
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
index 623fbc73b..507f914f3 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
@@ -79,6 +79,18 @@ public:
virtual void set_tx_dboard_clock_rate(double rate) = 0;
/*!
+ * Get the current rx dboard clock rate.
+ * \return the clock rate in Hz
+ */
+ virtual double get_rx_clock_rate(void) = 0;
+
+ /*!
+ * Get the current tx dboard clock rate.
+ * \return the clock rate in Hz
+ */
+ virtual double get_tx_clock_rate(void) = 0;
+
+ /*!
* Enable/disable the rx dboard clock.
* \param enb true to enable
*/
diff --git a/host/lib/usrp/usrp_e100/dboard_iface.cpp b/host/lib/usrp/usrp_e100/dboard_iface.cpp
index 4ee354486..61b5a1c92 100644
--- a/host/lib/usrp/usrp_e100/dboard_iface.cpp
+++ b/host/lib/usrp/usrp_e100/dboard_iface.cpp
@@ -97,7 +97,6 @@ private:
usrp_e100_iface::sptr _iface;
usrp_e100_clock_ctrl::sptr _clock;
usrp_e100_codec_ctrl::sptr _codec;
- uhd::dict<unit_t, double> _clock_rates;
};
/***********************************************************************
@@ -115,7 +114,6 @@ dboard_iface::sptr make_usrp_e100_dboard_iface(
* Clock Rates
**********************************************************************/
void usrp_e100_dboard_iface::set_clock_rate(unit_t unit, double rate){
- _clock_rates[unit] = rate;
switch(unit){
case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate);
case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate);
@@ -131,7 +129,11 @@ std::vector<double> usrp_e100_dboard_iface::get_clock_rates(unit_t unit){
}
double usrp_e100_dboard_iface::get_clock_rate(unit_t unit){
- return _clock_rates[unit];
+ switch(unit){
+ case UNIT_RX: return _clock->get_rx_clock_rate();
+ case UNIT_TX: return _clock->get_tx_clock_rate();
+ }
+ UHD_THROW_INVALID_CODE_PATH();
}
void usrp_e100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-07 22:29:41 +0000