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-rw-r--r--host/lib/usrp/b100/b100_impl.cpp14
-rw-r--r--host/lib/usrp/b100/b100_impl.hpp2
-rw-r--r--host/lib/usrp/b100/b100_regs.hpp42
-rw-r--r--host/lib/usrp/b100/dboard_iface.cpp71
-rw-r--r--host/lib/usrp/e100/dboard_iface.cpp71
-rw-r--r--host/lib/usrp/e100/e100_impl.cpp26
-rw-r--r--host/lib/usrp/e100/e100_impl.hpp3
-rw-r--r--host/lib/usrp/e100/e100_regs.hpp42
8 files changed, 58 insertions, 213 deletions
diff --git a/host/lib/usrp/b100/b100_impl.cpp b/host/lib/usrp/b100/b100_impl.cpp
index a047a9a53..6bebc75ab 100644
--- a/host/lib/usrp/b100/b100_impl.cpp
+++ b/host/lib/usrp/b100/b100_impl.cpp
@@ -457,13 +457,19 @@ void b100_impl::check_fw_compat(void){
}
void b100_impl::check_fpga_compat(void){
- const boost::uint16_t fpga_compat_num = _fpga_ctrl->peek16(B100_REG_MISC_COMPAT);
- if (fpga_compat_num != B100_FPGA_COMPAT_NUM){
+ const boost::uint32_t fpga_compat_num = _fpga_ctrl->peek32(B100_REG_RB_COMPAT);
+ boost::uint16_t fpga_major = fpga_compat_num >> 16, fpga_minor = fpga_compat_num & 0xffff;
+ if (fpga_major == 0){ //old version scheme
+ fpga_major = fpga_minor;
+ fpga_minor = 0;
+ }
+ if (fpga_major != B100_FPGA_COMPAT_NUM){
throw uhd::runtime_error(str(boost::format(
- "Expected FPGA compatibility number 0x%x, but got 0x%x:\n"
+ "Expected FPGA compatibility number %d, but got %d:\n"
"The FPGA build is not compatible with the host code build."
- ) % B100_FPGA_COMPAT_NUM % fpga_compat_num));
+ ) % int(B100_FPGA_COMPAT_NUM) % fpga_major));
}
+ _tree->create<std::string>("/mboards/0/fpga_version").set(str(boost::format("%u.%u") % fpga_major % fpga_minor));
}
double b100_impl::update_rx_codec_gain(const double gain){
diff --git a/host/lib/usrp/b100/b100_impl.hpp b/host/lib/usrp/b100/b100_impl.hpp
index 25badc967..0984260be 100644
--- a/host/lib/usrp/b100/b100_impl.hpp
+++ b/host/lib/usrp/b100/b100_impl.hpp
@@ -47,7 +47,7 @@ static const double B100_LINK_RATE_BPS = 256e6/8; //pratical link rate
static const std::string B100_FW_FILE_NAME = "usrp_b100_fw.ihx";
static const std::string B100_FPGA_FILE_NAME = "usrp_b100_fpga.bin";
static const boost::uint16_t B100_FW_COMPAT_NUM = 0x02;
-static const boost::uint16_t B100_FPGA_COMPAT_NUM = 0x05;
+static const boost::uint16_t B100_FPGA_COMPAT_NUM = 0x08;
static const boost::uint32_t B100_RX_SID_BASE = 2;
static const boost::uint32_t B100_TX_ASYNC_SID = 1;
static const double B100_DEFAULT_TICK_RATE = 64e6;
diff --git a/host/lib/usrp/b100/b100_regs.hpp b/host/lib/usrp/b100/b100_regs.hpp
index 5e24f9937..491e16eef 100644
--- a/host/lib/usrp/b100/b100_regs.hpp
+++ b/host/lib/usrp/b100/b100_regs.hpp
@@ -31,7 +31,6 @@
#define B100_REG_MISC_RX_LEN B100_REG_MISC_BASE + 10
#define B100_REG_MISC_TX_LEN B100_REG_MISC_BASE + 12
#define B100_REG_MISC_XFER_RATE B100_REG_MISC_BASE + 14
-#define B100_REG_MISC_COMPAT B100_REG_MISC_BASE + 16
/////////////////////////////////////////////////////
// Slave 1 -- UART
@@ -61,43 +60,6 @@
#define B100_REG_I2C_BASE B100_REG_SLAVE(3)
-////////////////////////////////////////////////
-// Slave 4 -- GPIO
-
-#define B100_REG_GPIO_BASE B100_REG_SLAVE(4)
-
-#define B100_REG_GPIO_RX_IO B100_REG_GPIO_BASE + 0
-#define B100_REG_GPIO_TX_IO B100_REG_GPIO_BASE + 2
-#define B100_REG_GPIO_RX_DDR B100_REG_GPIO_BASE + 4
-#define B100_REG_GPIO_TX_DDR B100_REG_GPIO_BASE + 6
-#define B100_REG_GPIO_RX_SEL B100_REG_GPIO_BASE + 8
-#define B100_REG_GPIO_TX_SEL B100_REG_GPIO_BASE + 10
-#define B100_REG_GPIO_RX_DBG B100_REG_GPIO_BASE + 12
-#define B100_REG_GPIO_TX_DBG B100_REG_GPIO_BASE + 14
-
-//possible bit values for sel when dbg is 0:
-#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg
-#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
-
-//possible bit values for sel when dbg is 1:
-#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric
-#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric
-
-///////////////////////////////////////////////////
-// Slave 6 -- ATR Controller
-// 16 regs
-
-#define B100_REG_ATR_BASE B100_REG_SLAVE(6)
-
-#define B100_REG_ATR_IDLE_RXSIDE B100_REG_ATR_BASE + 0
-#define B100_REG_ATR_IDLE_TXSIDE B100_REG_ATR_BASE + 2
-#define B100_REG_ATR_INTX_RXSIDE B100_REG_ATR_BASE + 4
-#define B100_REG_ATR_INTX_TXSIDE B100_REG_ATR_BASE + 6
-#define B100_REG_ATR_INRX_RXSIDE B100_REG_ATR_BASE + 8
-#define B100_REG_ATR_INRX_TXSIDE B100_REG_ATR_BASE + 10
-#define B100_REG_ATR_FULL_RXSIDE B100_REG_ATR_BASE + 12
-#define B100_REG_ATR_FULL_TXSIDE B100_REG_ATR_BASE + 14
-
///////////////////////////////////////////////////
// Slave 7 -- Readback Mux 32
@@ -108,6 +70,8 @@
#define B100_REG_RB_TIME_PPS_SECS B100_REG_RB_MUX_32_BASE + 8
#define B100_REG_RB_TIME_PPS_TICKS B100_REG_RB_MUX_32_BASE + 12
#define B100_REG_RB_MISC_TEST32 B100_REG_RB_MUX_32_BASE + 16
+#define B100_REG_RB_COMPAT B100_REG_RB_MUX_32_BASE + 24
+#define B100_REG_RB_GPIO B100_REG_RB_MUX_32_BASE + 28
////////////////////////////////////////////////////
// Slaves 8 & 9 -- Settings Bus
@@ -132,6 +96,8 @@
#define B100_SR_CLEAR_TX_FIFO 62 // 1 reg
#define B100_SR_GLOBAL_RESET 63 // 1 reg
+#define B100_SR_GPIO 128
+
#define B100_REG_SR_ADDR(n) (B100_REG_SLAVE(8) + (4*(n)))
#define B100_REG_SR_MISC_TEST32 B100_REG_SR_ADDR(B100_SR_REG_TEST32)
diff --git a/host/lib/usrp/b100/dboard_iface.cpp b/host/lib/usrp/b100/dboard_iface.cpp
index 229215a4e..39ad5c5ac 100644
--- a/host/lib/usrp/b100/dboard_iface.cpp
+++ b/host/lib/usrp/b100/dboard_iface.cpp
@@ -15,7 +15,7 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
-#include "wb_iface.hpp"
+#include "gpio_core_200.hpp"
#include <uhd/types/serial.hpp>
#include "b100_regs.hpp"
#include "clock_ctrl.hpp"
@@ -45,13 +45,11 @@ public:
_spi_iface = spi_iface;
_clock = clock;
_codec = codec;
+ _gpio = gpio_core_200::make(_wb_iface, B100_REG_SR_ADDR(B100_SR_GPIO), B100_REG_RB_GPIO);
//init the clock rate shadows
this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate());
this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate());
-
- _wb_iface->poke16(B100_REG_GPIO_RX_DBG, 0);
- _wb_iface->poke16(B100_REG_GPIO_TX_DBG, 0);
}
~b100_dboard_iface(void){
@@ -104,6 +102,7 @@ private:
spi_iface::sptr _spi_iface;
b100_clock_ctrl::sptr _clock;
b100_codec_ctrl::sptr _codec;
+ gpio_core_200::sptr _gpio;
};
/***********************************************************************
@@ -160,77 +159,27 @@ double b100_dboard_iface::get_codec_rate(unit_t){
* GPIO
**********************************************************************/
void b100_dboard_iface::_set_pin_ctrl(unit_t unit, boost::uint16_t value){
- UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption
- switch(unit){
- case UNIT_RX: _wb_iface->poke16(B100_REG_GPIO_RX_SEL, value); return;
- case UNIT_TX: _wb_iface->poke16(B100_REG_GPIO_TX_SEL, value); return;
- }
+ return _gpio->set_pin_ctrl(unit, value);
}
void b100_dboard_iface::_set_gpio_ddr(unit_t unit, boost::uint16_t value){
- switch(unit){
- case UNIT_RX: _wb_iface->poke16(B100_REG_GPIO_RX_DDR, value); return;
- case UNIT_TX: _wb_iface->poke16(B100_REG_GPIO_TX_DDR, value); return;
- }
+ return _gpio->set_gpio_ddr(unit, value);
}
void b100_dboard_iface::_set_gpio_out(unit_t unit, boost::uint16_t value){
- switch(unit){
- case UNIT_RX: _wb_iface->poke16(B100_REG_GPIO_RX_IO, value); return;
- case UNIT_TX: _wb_iface->poke16(B100_REG_GPIO_TX_IO, value); return;
- }
+ return _gpio->set_gpio_out(unit, value);
}
boost::uint16_t b100_dboard_iface::read_gpio(unit_t unit){
- switch(unit){
- case UNIT_RX: return _wb_iface->peek16(B100_REG_GPIO_RX_IO);
- case UNIT_TX: return _wb_iface->peek16(B100_REG_GPIO_TX_IO);
- default: UHD_THROW_INVALID_CODE_PATH();
- }
+ return _gpio->read_gpio(unit);
}
void b100_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){
- //define mapping of unit to atr regs to register address
- static const uhd::dict<
- unit_t, uhd::dict<atr_reg_t, boost::uint32_t>
- > unit_to_atr_to_addr = map_list_of
- (UNIT_RX, map_list_of
- (ATR_REG_IDLE, B100_REG_ATR_IDLE_RXSIDE)
- (ATR_REG_TX_ONLY, B100_REG_ATR_INTX_RXSIDE)
- (ATR_REG_RX_ONLY, B100_REG_ATR_INRX_RXSIDE)
- (ATR_REG_FULL_DUPLEX, B100_REG_ATR_FULL_RXSIDE)
- )
- (UNIT_TX, map_list_of
- (ATR_REG_IDLE, B100_REG_ATR_IDLE_TXSIDE)
- (ATR_REG_TX_ONLY, B100_REG_ATR_INTX_TXSIDE)
- (ATR_REG_RX_ONLY, B100_REG_ATR_INRX_TXSIDE)
- (ATR_REG_FULL_DUPLEX, B100_REG_ATR_FULL_TXSIDE)
- )
- ;
- _wb_iface->poke16(unit_to_atr_to_addr[unit][atr], value);
+ return _gpio->set_atr_reg(unit, atr, value);
}
-void b100_dboard_iface::set_gpio_debug(unit_t unit, int which){
- //set this unit to all outputs
- this->set_gpio_ddr(unit, 0xffff);
-
- //calculate the debug selections
- boost::uint32_t dbg_sels = 0x0;
- int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1;
- for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i;
-
- //set the debug on and which debug selection
- switch(unit){
- case UNIT_RX:
- _wb_iface->poke16(B100_REG_GPIO_RX_DBG, 0xffff);
- _wb_iface->poke16(B100_REG_GPIO_RX_SEL, dbg_sels);
- return;
-
- case UNIT_TX:
- _wb_iface->poke16(B100_REG_GPIO_TX_DBG, 0xffff);
- _wb_iface->poke16(B100_REG_GPIO_TX_SEL, dbg_sels);
- return;
- }
+void b100_dboard_iface::set_gpio_debug(unit_t, int){
+ throw uhd::not_implemented_error("no set_gpio_debug implemented");
}
/***********************************************************************
diff --git a/host/lib/usrp/e100/dboard_iface.cpp b/host/lib/usrp/e100/dboard_iface.cpp
index d45577bd9..6afc7bc48 100644
--- a/host/lib/usrp/e100/dboard_iface.cpp
+++ b/host/lib/usrp/e100/dboard_iface.cpp
@@ -15,7 +15,7 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
-#include "wb_iface.hpp"
+#include "gpio_core_200.hpp"
#include <uhd/types/serial.hpp>
#include "e100_regs.hpp"
#include "clock_ctrl.hpp"
@@ -45,13 +45,11 @@ public:
_spi_iface = spi_iface;
_clock = clock;
_codec = codec;
+ _gpio = gpio_core_200::make(_wb_iface, E100_REG_SR_ADDR(UE_SR_GPIO), E100_REG_RB_GPIO);
//init the clock rate shadows
this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate());
this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate());
-
- _wb_iface->poke16(E100_REG_GPIO_RX_DBG, 0);
- _wb_iface->poke16(E100_REG_GPIO_TX_DBG, 0);
}
~e100_dboard_iface(void){
@@ -104,6 +102,7 @@ private:
spi_iface::sptr _spi_iface;
e100_clock_ctrl::sptr _clock;
e100_codec_ctrl::sptr _codec;
+ gpio_core_200::sptr _gpio;
};
/***********************************************************************
@@ -160,77 +159,27 @@ double e100_dboard_iface::get_codec_rate(unit_t){
* GPIO
**********************************************************************/
void e100_dboard_iface::_set_pin_ctrl(unit_t unit, boost::uint16_t value){
- UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption
- switch(unit){
- case UNIT_RX: _wb_iface->poke16(E100_REG_GPIO_RX_SEL, value); return;
- case UNIT_TX: _wb_iface->poke16(E100_REG_GPIO_TX_SEL, value); return;
- }
+ return _gpio->set_pin_ctrl(unit, value);
}
void e100_dboard_iface::_set_gpio_ddr(unit_t unit, boost::uint16_t value){
- switch(unit){
- case UNIT_RX: _wb_iface->poke16(E100_REG_GPIO_RX_DDR, value); return;
- case UNIT_TX: _wb_iface->poke16(E100_REG_GPIO_TX_DDR, value); return;
- }
+ return _gpio->set_gpio_ddr(unit, value);
}
void e100_dboard_iface::_set_gpio_out(unit_t unit, boost::uint16_t value){
- switch(unit){
- case UNIT_RX: _wb_iface->poke16(E100_REG_GPIO_RX_IO, value); return;
- case UNIT_TX: _wb_iface->poke16(E100_REG_GPIO_TX_IO, value); return;
- }
+ return _gpio->set_gpio_out(unit, value);
}
boost::uint16_t e100_dboard_iface::read_gpio(unit_t unit){
- switch(unit){
- case UNIT_RX: return _wb_iface->peek16(E100_REG_GPIO_RX_IO);
- case UNIT_TX: return _wb_iface->peek16(E100_REG_GPIO_TX_IO);
- default: UHD_THROW_INVALID_CODE_PATH();
- }
+ return _gpio->read_gpio(unit);
}
void e100_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){
- //define mapping of unit to atr regs to register address
- static const uhd::dict<
- unit_t, uhd::dict<atr_reg_t, boost::uint32_t>
- > unit_to_atr_to_addr = map_list_of
- (UNIT_RX, map_list_of
- (ATR_REG_IDLE, E100_REG_ATR_IDLE_RXSIDE)
- (ATR_REG_TX_ONLY, E100_REG_ATR_INTX_RXSIDE)
- (ATR_REG_RX_ONLY, E100_REG_ATR_INRX_RXSIDE)
- (ATR_REG_FULL_DUPLEX, E100_REG_ATR_FULL_RXSIDE)
- )
- (UNIT_TX, map_list_of
- (ATR_REG_IDLE, E100_REG_ATR_IDLE_TXSIDE)
- (ATR_REG_TX_ONLY, E100_REG_ATR_INTX_TXSIDE)
- (ATR_REG_RX_ONLY, E100_REG_ATR_INRX_TXSIDE)
- (ATR_REG_FULL_DUPLEX, E100_REG_ATR_FULL_TXSIDE)
- )
- ;
- _wb_iface->poke16(unit_to_atr_to_addr[unit][atr], value);
+ return _gpio->set_atr_reg(unit, atr, value);
}
-void e100_dboard_iface::set_gpio_debug(unit_t unit, int which){
- //set this unit to all outputs
- this->set_gpio_ddr(unit, 0xffff);
-
- //calculate the debug selections
- boost::uint32_t dbg_sels = 0x0;
- int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1;
- for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i;
-
- //set the debug on and which debug selection
- switch(unit){
- case UNIT_RX:
- _wb_iface->poke16(E100_REG_GPIO_RX_DBG, 0xffff);
- _wb_iface->poke16(E100_REG_GPIO_RX_SEL, dbg_sels);
- return;
-
- case UNIT_TX:
- _wb_iface->poke16(E100_REG_GPIO_TX_DBG, 0xffff);
- _wb_iface->poke16(E100_REG_GPIO_TX_SEL, dbg_sels);
- return;
- }
+void e100_dboard_iface::set_gpio_debug(unit_t, int){
+ throw uhd::not_implemented_error("no set_gpio_debug implemented");
}
/***********************************************************************
diff --git a/host/lib/usrp/e100/e100_impl.cpp b/host/lib/usrp/e100/e100_impl.cpp
index 00916ec2b..8fe9081b1 100644
--- a/host/lib/usrp/e100/e100_impl.cpp
+++ b/host/lib/usrp/e100/e100_impl.cpp
@@ -167,15 +167,7 @@ e100_impl::e100_impl(const uhd::device_addr_t &device_addr){
);
//check that the compatibility is correct
- const boost::uint16_t fpga_compat_num = _fpga_ctrl->peek16(E100_REG_MISC_COMPAT);
- if (fpga_compat_num != E100_FPGA_COMPAT_NUM){
- throw uhd::runtime_error(str(boost::format(
- "\nPlease update the FPGA image for your device.\n"
- "See the application notes for USRP E-Series for instructions.\n"
- "Expected FPGA compatibility number 0x%x, but got 0x%x:\n"
- "The FPGA build is not compatible with the host code build."
- ) % E100_FPGA_COMPAT_NUM % fpga_compat_num));
- }
+ this->check_fpga_compat();
////////////////////////////////////////////////////////////////////
// Create controller objects
@@ -455,3 +447,19 @@ sensor_value_t e100_impl::get_ref_locked(void){
const bool lock = _clock_ctrl->get_locked();
return sensor_value_t("Ref", lock, "locked", "unlocked");
}
+
+void e100_impl::check_fpga_compat(void){
+ const boost::uint32_t fpga_compat_num = _fpga_ctrl->peek32(E100_REG_RB_COMPAT);
+ boost::uint16_t fpga_major = fpga_compat_num >> 16, fpga_minor = fpga_compat_num & 0xffff;
+ if (fpga_major == 0){ //old version scheme
+ fpga_major = fpga_minor;
+ fpga_minor = 0;
+ }
+ if (fpga_major != E100_FPGA_COMPAT_NUM){
+ throw uhd::runtime_error(str(boost::format(
+ "Expected FPGA compatibility number %d, but got %d:\n"
+ "The FPGA build is not compatible with the host code build."
+ ) % int(E100_FPGA_COMPAT_NUM) % fpga_major));
+ }
+ _tree->create<std::string>("/mboards/0/fpga_version").set(str(boost::format("%u.%u") % fpga_major % fpga_minor));
+}
diff --git a/host/lib/usrp/e100/e100_impl.hpp b/host/lib/usrp/e100/e100_impl.hpp
index 954d6bd93..f3e481b93 100644
--- a/host/lib/usrp/e100/e100_impl.hpp
+++ b/host/lib/usrp/e100/e100_impl.hpp
@@ -48,7 +48,7 @@ static const double E100_RX_LINK_RATE_BPS = 166e6/3/2*2;
static const double E100_TX_LINK_RATE_BPS = 166e6/3/1*2;
static const std::string E100_I2C_DEV_NODE = "/dev/i2c-3";
static const std::string E100_UART_DEV_NODE = "/dev/ttyO0";
-static const boost::uint16_t E100_FPGA_COMPAT_NUM = 0x06;
+static const boost::uint16_t E100_FPGA_COMPAT_NUM = 0x08;
static const boost::uint32_t E100_RX_SID_BASE = 2;
static const boost::uint32_t E100_TX_ASYNC_SID = 1;
static const double E100_DEFAULT_CLOCK_RATE = 64e6;
@@ -129,6 +129,7 @@ private:
void update_tx_subdev_spec(const uhd::usrp::subdev_spec_t &);
void update_clock_source(const std::string &);
uhd::sensor_value_t get_ref_locked(void);
+ void check_fpga_compat(void);
};
diff --git a/host/lib/usrp/e100/e100_regs.hpp b/host/lib/usrp/e100/e100_regs.hpp
index 28ef707dc..f24f5895b 100644
--- a/host/lib/usrp/e100/e100_regs.hpp
+++ b/host/lib/usrp/e100/e100_regs.hpp
@@ -31,7 +31,6 @@
#define E100_REG_MISC_RX_LEN E100_REG_MISC_BASE + 10
#define E100_REG_MISC_TX_LEN E100_REG_MISC_BASE + 12
#define E100_REG_MISC_XFER_RATE E100_REG_MISC_BASE + 14
-#define E100_REG_MISC_COMPAT E100_REG_MISC_BASE + 16
/////////////////////////////////////////////////////
// Slave 1 -- UART
@@ -67,43 +66,6 @@
#define E100_REG_ERR_BUFF E100_REG_SLAVE(5)
-////////////////////////////////////////////////
-// Slave 4 -- GPIO
-
-#define E100_REG_GPIO_BASE E100_REG_SLAVE(4)
-
-#define E100_REG_GPIO_RX_IO E100_REG_GPIO_BASE + 0
-#define E100_REG_GPIO_TX_IO E100_REG_GPIO_BASE + 2
-#define E100_REG_GPIO_RX_DDR E100_REG_GPIO_BASE + 4
-#define E100_REG_GPIO_TX_DDR E100_REG_GPIO_BASE + 6
-#define E100_REG_GPIO_RX_SEL E100_REG_GPIO_BASE + 8
-#define E100_REG_GPIO_TX_SEL E100_REG_GPIO_BASE + 10
-#define E100_REG_GPIO_RX_DBG E100_REG_GPIO_BASE + 12
-#define E100_REG_GPIO_TX_DBG E100_REG_GPIO_BASE + 14
-
-//possible bit values for sel when dbg is 0:
-#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg
-#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
-
-//possible bit values for sel when dbg is 1:
-#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric
-#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric
-
-///////////////////////////////////////////////////
-// Slave 6 -- ATR Controller
-// 16 regs
-
-#define E100_REG_ATR_BASE E100_REG_SLAVE(6)
-
-#define E100_REG_ATR_IDLE_RXSIDE E100_REG_ATR_BASE + 0
-#define E100_REG_ATR_IDLE_TXSIDE E100_REG_ATR_BASE + 2
-#define E100_REG_ATR_INTX_RXSIDE E100_REG_ATR_BASE + 4
-#define E100_REG_ATR_INTX_TXSIDE E100_REG_ATR_BASE + 6
-#define E100_REG_ATR_INRX_RXSIDE E100_REG_ATR_BASE + 8
-#define E100_REG_ATR_INRX_TXSIDE E100_REG_ATR_BASE + 10
-#define E100_REG_ATR_FULL_RXSIDE E100_REG_ATR_BASE + 12
-#define E100_REG_ATR_FULL_TXSIDE E100_REG_ATR_BASE + 14
-
///////////////////////////////////////////////////
// Slave 7 -- Readback Mux 32
@@ -115,6 +77,8 @@
#define E100_REG_RB_TIME_PPS_TICKS E100_REG_RB_MUX_32_BASE + 12
#define E100_REG_RB_MISC_TEST32 E100_REG_RB_MUX_32_BASE + 16
#define E100_REG_RB_ERR_STATUS E100_REG_RB_MUX_32_BASE + 20
+#define E100_REG_RB_COMPAT E100_REG_RB_MUX_32_BASE + 24
+#define E100_REG_RB_GPIO E100_REG_RB_MUX_32_BASE + 28
////////////////////////////////////////////////////
// Slave 8 -- Settings Bus
@@ -141,6 +105,8 @@
#define UE_SR_CLEAR_TX_FIFO 62 // 1 reg
#define UE_SR_GLOBAL_RESET 63 // 1 reg
+#define UE_SR_GPIO 128
+
#define E100_REG_SR_ADDR(n) (E100_REG_SLAVE(8) + (4*(n)))
#define E100_REG_SR_MISC_TEST32 E100_REG_SR_ADDR(UE_SR_REG_TEST32)
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 12:28:34 +0000