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-rw-r--r--host/lib/usrp/x300/x300_regs.hpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp
index c5ed1460b..80d275949 100644
--- a/host/lib/usrp/x300/x300_regs.hpp
+++ b/host/lib/usrp/x300/x300_regs.hpp
@@ -104,6 +104,7 @@ static const uint32_t X310_2942R_120MHz_PCIE_SSID_ADC_18 = 0x785C;
static const uint32_t X310_2943R_40MHz_PCIE_SSID_ADC_18 = 0x7855;
static const uint32_t X310_2943R_120MHz_PCIE_SSID_ADC_18 = 0x785D;
static const uint32_t X310_2944R_40MHz_PCIE_SSID_ADC_18 = 0x7856;
+static const uint32_t X310_2945R_PCIE_SSID_ADC_18 = 0x78EF;
static const uint32_t X310_2950R_40MHz_PCIE_SSID_ADC_18 = 0x7857;
static const uint32_t X310_2950R_120MHz_PCIE_SSID_ADC_18 = 0x785E;
static const uint32_t X310_2952R_40MHz_PCIE_SSID_ADC_18 = 0x7858;
@@ -111,6 +112,7 @@ static const uint32_t X310_2952R_120MHz_PCIE_SSID_ADC_18 = 0x785F;
static const uint32_t X310_2953R_40MHz_PCIE_SSID_ADC_18 = 0x7859;
static const uint32_t X310_2953R_120MHz_PCIE_SSID_ADC_18 = 0x7860;
static const uint32_t X310_2954R_40MHz_PCIE_SSID_ADC_18 = 0x785A;
+static const uint32_t X310_2955R_PCIE_SSID_ADC_18 = 0x78F0;
static const uint32_t FPGA_X3xx_SIG_VALUE = 0x58333030;