diff options
Diffstat (limited to 'host/lib/usrp/x300/x300_regs.hpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_regs.hpp | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp index d5dc8140c..f41afeb23 100644 --- a/host/lib/usrp/x300/x300_regs.hpp +++ b/host/lib/usrp/x300/x300_regs.hpp @@ -106,40 +106,40 @@ localparam ZPU_RB_ETH_TYPE1 = 5; static const uint32_t X300_PCIE_VID = 0x1093; static const uint32_t X300_PCIE_PID = 0xC4C4; -//Rev 0-6 motherboard/PCIe IDs -static const uint32_t X300_USRP_PCIE_SSID = 0x7736; -static const uint32_t X310_USRP_PCIE_SSID = 0x76CA; -static const uint32_t X310_2940R_40MHz_PCIE_SSID = 0x772B; -static const uint32_t X310_2940R_120MHz_PCIE_SSID = 0x77FB; -static const uint32_t X310_2942R_40MHz_PCIE_SSID = 0x772C; -static const uint32_t X310_2942R_120MHz_PCIE_SSID = 0x77FC; -static const uint32_t X310_2943R_40MHz_PCIE_SSID = 0x772D; -static const uint32_t X310_2943R_120MHz_PCIE_SSID = 0x77FD; -static const uint32_t X310_2944R_40MHz_PCIE_SSID = 0x772E; -static const uint32_t X310_2950R_40MHz_PCIE_SSID = 0x772F; -static const uint32_t X310_2950R_120MHz_PCIE_SSID = 0x77FE; -static const uint32_t X310_2952R_40MHz_PCIE_SSID = 0x7730; -static const uint32_t X310_2952R_120MHz_PCIE_SSID = 0x77FF; -static const uint32_t X310_2953R_40MHz_PCIE_SSID = 0x7731; -static const uint32_t X310_2953R_120MHz_PCIE_SSID = 0x7800; -static const uint32_t X310_2954R_40MHz_PCIE_SSID = 0x7732; -//Rev 7+ motherboard/PCIe IDs -static const uint32_t X300_USRP_PCIE_R7_SSID = 0x7861; -static const uint32_t X310_USRP_PCIE_R7_SSID = 0x7862; -static const uint32_t X310_2940R_40MHz_PCIE_R7_SSID = 0x7853; -static const uint32_t X310_2940R_120MHz_PCIE_R7_SSID = 0x785B; -static const uint32_t X310_2942R_40MHz_PCIE_R7_SSID = 0x7854; -static const uint32_t X310_2942R_120MHz_PCIE_R7_SSID = 0x785C; -static const uint32_t X310_2943R_40MHz_PCIE_R7_SSID = 0x7855; -static const uint32_t X310_2943R_120MHz_PCIE_R7_SSID = 0x785D; -static const uint32_t X310_2944R_40MHz_PCIE_R7_SSID = 0x7856; -static const uint32_t X310_2950R_40MHz_PCIE_R7_SSID = 0x7857; -static const uint32_t X310_2950R_120MHz_PCIE_R7_SSID = 0x785E; -static const uint32_t X310_2952R_40MHz_PCIE_R7_SSID = 0x7858; -static const uint32_t X310_2952R_120MHz_PCIE_R7_SSID = 0x785F; -static const uint32_t X310_2953R_40MHz_PCIE_R7_SSID = 0x7859; -static const uint32_t X310_2953R_120MHz_PCIE_R7_SSID = 0x7860; -static const uint32_t X310_2954R_40MHz_PCIE_R7_SSID = 0x785A; +//Rev 0-6 motherboard/PCIe IDs (ADC driven at 3.3V) +static const uint32_t X300_USRP_PCIE_SSID_ADC_33 = 0x7736; +static const uint32_t X310_USRP_PCIE_SSID_ADC_33 = 0x76CA; +static const uint32_t X310_2940R_40MHz_PCIE_SSID_ADC_33 = 0x772B; +static const uint32_t X310_2940R_120MHz_PCIE_SSID_ADC_33 = 0x77FB; +static const uint32_t X310_2942R_40MHz_PCIE_SSID_ADC_33 = 0x772C; +static const uint32_t X310_2942R_120MHz_PCIE_SSID_ADC_33 = 0x77FC; +static const uint32_t X310_2943R_40MHz_PCIE_SSID_ADC_33 = 0x772D; +static const uint32_t X310_2943R_120MHz_PCIE_SSID_ADC_33 = 0x77FD; +static const uint32_t X310_2944R_40MHz_PCIE_SSID_ADC_33 = 0x772E; +static const uint32_t X310_2950R_40MHz_PCIE_SSID_ADC_33 = 0x772F; +static const uint32_t X310_2950R_120MHz_PCIE_SSID_ADC_33 = 0x77FE; +static const uint32_t X310_2952R_40MHz_PCIE_SSID_ADC_33 = 0x7730; +static const uint32_t X310_2952R_120MHz_PCIE_SSID_ADC_33 = 0x77FF; +static const uint32_t X310_2953R_40MHz_PCIE_SSID_ADC_33 = 0x7731; +static const uint32_t X310_2953R_120MHz_PCIE_SSID_ADC_33 = 0x7800; +static const uint32_t X310_2954R_40MHz_PCIE_SSID_ADC_33 = 0x7732; +//Rev 7+ motherboard/PCIe IDs (ADCs driven at 1.8V) +static const uint32_t X300_USRP_PCIE_SSID_ADC_18 = 0x7861; +static const uint32_t X310_USRP_PCIE_SSID_ADC_18 = 0x7862; +static const uint32_t X310_2940R_40MHz_PCIE_SSID_ADC_18 = 0x7853; +static const uint32_t X310_2940R_120MHz_PCIE_SSID_ADC_18 = 0x785B; +static const uint32_t X310_2942R_40MHz_PCIE_SSID_ADC_18 = 0x7854; +static const uint32_t X310_2942R_120MHz_PCIE_SSID_ADC_18 = 0x785C; +static const uint32_t X310_2943R_40MHz_PCIE_SSID_ADC_18 = 0x7855; +static const uint32_t X310_2943R_120MHz_PCIE_SSID_ADC_18 = 0x785D; +static const uint32_t X310_2944R_40MHz_PCIE_SSID_ADC_18 = 0x7856; +static const uint32_t X310_2950R_40MHz_PCIE_SSID_ADC_18 = 0x7857; +static const uint32_t X310_2950R_120MHz_PCIE_SSID_ADC_18 = 0x785E; +static const uint32_t X310_2952R_40MHz_PCIE_SSID_ADC_18 = 0x7858; +static const uint32_t X310_2952R_120MHz_PCIE_SSID_ADC_18 = 0x785F; +static const uint32_t X310_2953R_40MHz_PCIE_SSID_ADC_18 = 0x7859; +static const uint32_t X310_2953R_120MHz_PCIE_SSID_ADC_18 = 0x7860; +static const uint32_t X310_2954R_40MHz_PCIE_SSID_ADC_18 = 0x785A; static const uint32_t FPGA_X3xx_SIG_VALUE = 0x58333030; |