aboutsummaryrefslogtreecommitdiffstats
path: root/host/lib/usrp/usrp_e/clock_ctrl.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'host/lib/usrp/usrp_e/clock_ctrl.cpp')
-rw-r--r--host/lib/usrp/usrp_e/clock_ctrl.cpp1
1 files changed, 0 insertions, 1 deletions
diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp
index 8a5bd1c6b..b53e880a2 100644
--- a/host/lib/usrp/usrp_e/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp
@@ -60,7 +60,6 @@ class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{
public:
usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){
_iface = iface;
- std::cout << "master_clock_rate: " << (master_clock_rate/1e6) << " MHz" << std::endl;
//init the clock gen registers
//Note: out0 should already be clocking the FPGA or this isnt going to work