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-rw-r--r--host/lib/usrp/usrp2/dsp_impl.cpp161
-rw-r--r--host/lib/usrp/usrp2/fw_common.h7
-rw-r--r--host/lib/usrp/usrp2/io_impl.cpp119
-rw-r--r--host/lib/usrp/usrp2/mboard_impl.cpp174
-rw-r--r--host/lib/usrp/usrp2/usrp2_impl.cpp144
-rw-r--r--host/lib/usrp/usrp2/usrp2_impl.hpp70
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.cpp51
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.hpp40
8 files changed, 379 insertions, 387 deletions
diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp
index 8340f7cdd..cdd559e94 100644
--- a/host/lib/usrp/usrp2/dsp_impl.cpp
+++ b/host/lib/usrp/usrp2/dsp_impl.cpp
@@ -1,5 +1,5 @@
//
-// Copyright 2010 Ettus Research LLC
+// Copyright 2010-2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -28,12 +28,79 @@
using namespace uhd;
using namespace uhd::usrp;
-static const size_t default_decim = 16;
-static const size_t default_interp = 16;
-
/***********************************************************************
- * DDC Helper Methods
+ * DSP impl and methods
**********************************************************************/
+struct usrp2_mboard_impl::dsp_impl{
+ uhd::dict<size_t, size_t> ddc_decim;
+ uhd::dict<size_t, double> ddc_freq;
+ uhd::dict<size_t, size_t> duc_interp;
+ uhd::dict<size_t, double> duc_freq;
+ std::vector<size_t> decim_and_interp_rates;
+ uhd::dict<size_t, bool> continuous_streaming;
+};
+
+void usrp2_mboard_impl::dsp_init(void){
+ //create new dsp impl
+ _dsp_impl = UHD_PIMPL_MAKE(dsp_impl, ());
+
+ //load the allowed decim/interp rates
+ //range(4, 128+1, 1) + range(130, 256+1, 2) + range(260, 512+1, 4)
+ for (size_t i = 4; i <= 128; i+=1){
+ _dsp_impl->decim_and_interp_rates.push_back(i);
+ }
+ for (size_t i = 130; i <= 256; i+=2){
+ _dsp_impl->decim_and_interp_rates.push_back(i);
+ }
+ for (size_t i = 260; i <= 512; i+=4){
+ _dsp_impl->decim_and_interp_rates.push_back(i);
+ }
+
+ //bind and initialize the rx dsps
+ for (size_t i = 0; i < NUM_RX_DSPS; i++){
+ _rx_dsp_proxies[str(boost::format("DSP%d")%i)] = wax_obj_proxy::make(
+ boost::bind(&usrp2_mboard_impl::ddc_get, this, _1, _2, i),
+ boost::bind(&usrp2_mboard_impl::ddc_set, this, _1, _2, i)
+ );
+
+ //initial config and update
+ ddc_set(DSP_PROP_FREQ_SHIFT, double(0), i);
+ ddc_set(DSP_PROP_HOST_RATE, double(get_master_clock_freq()/16), i);
+
+ //setup the rx control registers
+ _iface->poke32(_iface->regs.rx_ctrl[i].clear_overrun, 1); //reset
+ _iface->poke32(_iface->regs.rx_ctrl[i].nsamps_per_pkt, _device.get_max_recv_samps_per_packet());
+ _iface->poke32(_iface->regs.rx_ctrl[i].nchannels, 1);
+ _iface->poke32(_iface->regs.rx_ctrl[i].vrt_header, 0
+ | (0x1 << 28) //if data with stream id
+ | (0x1 << 26) //has trailer
+ | (0x3 << 22) //integer time other
+ | (0x1 << 20) //fractional time sample count
+ );
+ _iface->poke32(_iface->regs.rx_ctrl[i].vrt_stream_id, usrp2_impl::RECV_SID);
+ _iface->poke32(_iface->regs.rx_ctrl[i].vrt_trailer, 0);
+ _iface->poke32(_iface->regs.time64_tps, size_t(get_master_clock_freq()));
+ }
+
+ //bind and initialize the tx dsps
+ for (size_t i = 0; i < NUM_TX_DSPS; i++){
+ _tx_dsp_proxies[str(boost::format("DSP%d")%i)] = wax_obj_proxy::make(
+ boost::bind(&usrp2_mboard_impl::duc_get, this, _1, _2, i),
+ boost::bind(&usrp2_mboard_impl::duc_set, this, _1, _2, i)
+ );
+
+ //initial config and update
+ duc_set(DSP_PROP_FREQ_SHIFT, double(0), i);
+ duc_set(DSP_PROP_HOST_RATE, double(get_master_clock_freq()/16), i);
+
+ //init the tx control registers
+ _iface->poke32(_iface->regs.tx_ctrl_clear_state, 1); //reset
+ _iface->poke32(_iface->regs.tx_ctrl_num_chan, 0); //1 channel
+ _iface->poke32(_iface->regs.tx_ctrl_report_sid, usrp2_impl::ASYNC_SID);
+ _iface->poke32(_iface->regs.tx_ctrl_policy, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET);
+ }
+}
+
template <typename rate_type>
static rate_type pick_closest_rate(double exact_rate, const std::vector<rate_type> &rates){
unsigned closest_match = rates.front();
@@ -44,27 +111,28 @@ static rate_type pick_closest_rate(double exact_rate, const std::vector<rate_typ
return closest_match;
}
-void usrp2_mboard_impl::init_ddc_config(void){
- //create the ddc in the rx dsp dict
- _rx_dsp_proxy = wax_obj_proxy::make(
- boost::bind(&usrp2_mboard_impl::ddc_get, this, _1, _2),
- boost::bind(&usrp2_mboard_impl::ddc_set, this, _1, _2)
- );
+void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd, size_t which_dsp){
+ _dsp_impl->continuous_streaming[which_dsp] = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS;
+ _iface->poke32(_iface->regs.rx_ctrl[which_dsp].stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd));
+ _iface->poke32(_iface->regs.rx_ctrl[which_dsp].time_secs, boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
+ _iface->poke32(_iface->regs.rx_ctrl[which_dsp].time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
+}
- //initial config and update
- ddc_set(DSP_PROP_FREQ_SHIFT, double(0));
- ddc_set(DSP_PROP_HOST_RATE, double(get_master_clock_freq()/default_decim));
+void usrp2_mboard_impl::handle_overflow(size_t which_dsp){
+ if (_dsp_impl->continuous_streaming[which_dsp]){ //re-issue the stream command if already continuous
+ this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS, which_dsp);
+ }
}
/***********************************************************************
* DDC Properties
**********************************************************************/
-void usrp2_mboard_impl::ddc_get(const wax::obj &key_, wax::obj &val){
+void usrp2_mboard_impl::ddc_get(const wax::obj &key_, wax::obj &val, size_t which_dsp){
named_prop_t key = named_prop_t::extract(key_);
switch(key.as<dsp_prop_t>()){
case DSP_PROP_NAME:
- val = _iface->get_cname() + " ddc0";
+ val = str(boost::format("%s ddc%d") % _iface->get_cname() % which_dsp);
return;
case DSP_PROP_OTHERS:
@@ -72,11 +140,7 @@ void usrp2_mboard_impl::ddc_get(const wax::obj &key_, wax::obj &val){
return;
case DSP_PROP_FREQ_SHIFT:
- val = _ddc_freq;
- return;
-
- case DSP_PROP_FREQ_SHIFT_NAMES:
- val = prop_names_t(1, "");
+ val = _dsp_impl->ddc_freq[which_dsp];
return;
case DSP_PROP_CODEC_RATE:
@@ -84,37 +148,41 @@ void usrp2_mboard_impl::ddc_get(const wax::obj &key_, wax::obj &val){
return;
case DSP_PROP_HOST_RATE:
- val = get_master_clock_freq()/_ddc_decim;
+ val = get_master_clock_freq()/_dsp_impl->ddc_decim[which_dsp];
return;
default: UHD_THROW_PROP_GET_ERROR();
}
}
-void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val){
+void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_t which_dsp){
named_prop_t key = named_prop_t::extract(key_);
switch(key.as<dsp_prop_t>()){
+ case DSP_PROP_STREAM_CMD:
+ issue_ddc_stream_cmd(val.as<stream_cmd_t>(), which_dsp);
+ return;
+
case DSP_PROP_FREQ_SHIFT:{
double new_freq = val.as<double>();
- _iface->poke32(_iface->regs.dsp_rx_freq,
+ _iface->poke32(_iface->regs.dsp_rx[which_dsp].freq,
dsp_type1::calc_cordic_word_and_update(new_freq, get_master_clock_freq())
);
- _ddc_freq = new_freq; //shadow
+ _dsp_impl->ddc_freq[which_dsp] = new_freq; //shadow
}
return;
case DSP_PROP_HOST_RATE:{
double extact_rate = get_master_clock_freq()/val.as<double>();
- _ddc_decim = pick_closest_rate(extact_rate, _allowed_decim_and_interp_rates);
+ _dsp_impl->ddc_decim[which_dsp] = pick_closest_rate(extact_rate, _dsp_impl->decim_and_interp_rates);
//set the decimation
- _iface->poke32(_iface->regs.dsp_rx_decim_rate, dsp_type1::calc_cic_filter_word(_ddc_decim));
+ _iface->poke32(_iface->regs.dsp_rx[which_dsp].decim_rate, dsp_type1::calc_cic_filter_word(_dsp_impl->ddc_decim[which_dsp]));
//set the scaling
static const boost::int16_t default_rx_scale_iq = 1024;
- _iface->poke32(_iface->regs.dsp_rx_scale_iq,
+ _iface->poke32(_iface->regs.dsp_rx[which_dsp].scale_iq,
dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq)
);
}
@@ -125,29 +193,14 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val){
}
/***********************************************************************
- * DUC Helper Methods
- **********************************************************************/
-void usrp2_mboard_impl::init_duc_config(void){
- //create the duc in the tx dsp dict
- _tx_dsp_proxy = wax_obj_proxy::make(
- boost::bind(&usrp2_mboard_impl::duc_get, this, _1, _2),
- boost::bind(&usrp2_mboard_impl::duc_set, this, _1, _2)
- );
-
- //initial config and update
- duc_set(DSP_PROP_FREQ_SHIFT, double(0));
- duc_set(DSP_PROP_HOST_RATE, double(get_master_clock_freq()/default_interp));
-}
-
-/***********************************************************************
* DUC Properties
**********************************************************************/
-void usrp2_mboard_impl::duc_get(const wax::obj &key_, wax::obj &val){
+void usrp2_mboard_impl::duc_get(const wax::obj &key_, wax::obj &val, size_t which_dsp){
named_prop_t key = named_prop_t::extract(key_);
switch(key.as<dsp_prop_t>()){
case DSP_PROP_NAME:
- val = _iface->get_cname() + " duc0";
+ val = str(boost::format("%s duc%d") % _iface->get_cname() % which_dsp);
return;
case DSP_PROP_OTHERS:
@@ -155,11 +208,7 @@ void usrp2_mboard_impl::duc_get(const wax::obj &key_, wax::obj &val){
return;
case DSP_PROP_FREQ_SHIFT:
- val = _duc_freq;
- return;
-
- case DSP_PROP_FREQ_SHIFT_NAMES:
- val = prop_names_t(1, "");
+ val = _dsp_impl->duc_freq[which_dsp];
return;
case DSP_PROP_CODEC_RATE:
@@ -167,14 +216,14 @@ void usrp2_mboard_impl::duc_get(const wax::obj &key_, wax::obj &val){
return;
case DSP_PROP_HOST_RATE:
- val = get_master_clock_freq()/_duc_interp;
+ val = get_master_clock_freq()/_dsp_impl->duc_interp[which_dsp];
return;
default: UHD_THROW_PROP_GET_ERROR();
}
}
-void usrp2_mboard_impl::duc_set(const wax::obj &key_, const wax::obj &val){
+void usrp2_mboard_impl::duc_set(const wax::obj &key_, const wax::obj &val, size_t which_dsp){
named_prop_t key = named_prop_t::extract(key_);
switch(key.as<dsp_prop_t>()){
@@ -196,19 +245,19 @@ void usrp2_mboard_impl::duc_set(const wax::obj &key_, const wax::obj &val){
_iface->poke32(_iface->regs.dsp_tx_freq,
dsp_type1::calc_cordic_word_and_update(new_freq, codec_rate)
);
- _duc_freq = new_freq + dac_shift; //shadow
+ _dsp_impl->duc_freq[which_dsp] = new_freq + dac_shift; //shadow
}
return;
case DSP_PROP_HOST_RATE:{
double extact_rate = get_master_clock_freq()/val.as<double>();
- _duc_interp = pick_closest_rate(extact_rate, _allowed_decim_and_interp_rates);
+ _dsp_impl->duc_interp[which_dsp] = pick_closest_rate(extact_rate, _dsp_impl->decim_and_interp_rates);
//set the interpolation
- _iface->poke32(_iface->regs.dsp_tx_interp_rate, dsp_type1::calc_cic_filter_word(_duc_interp));
+ _iface->poke32(_iface->regs.dsp_tx_interp_rate, dsp_type1::calc_cic_filter_word(_dsp_impl->duc_interp[which_dsp]));
//set the scaling
- _iface->poke32(_iface->regs.dsp_tx_scale_iq, dsp_type1::calc_iq_scale_word(_duc_interp));
+ _iface->poke32(_iface->regs.dsp_tx_scale_iq, dsp_type1::calc_iq_scale_word(_dsp_impl->duc_interp[which_dsp]));
}
return;
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index a22f805e1..6eb047454 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -30,8 +30,8 @@ extern "C" {
#endif
//fpga and firmware compatibility numbers
-#define USRP2_FPGA_COMPAT_NUM 4
-#define USRP2_FW_COMPAT_NUM 8
+#define USRP2_FPGA_COMPAT_NUM 5
+#define USRP2_FW_COMPAT_NUM 9
//used to differentiate control packets over data port
#define USRP2_INVALID_VRT_HEADER 0
@@ -40,8 +40,9 @@ extern "C" {
// Dynamic and/or private ports: 49152-65535
#define USRP2_UDP_CTRL_PORT 49152
//#define USRP2_UDP_UPDATE_PORT 49154
-#define USRP2_UDP_DATA_PORT 49156
+#define USRP2_UDP_DSP0_PORT 49156
#define USRP2_UDP_ERR0_PORT 49157
+#define USRP2_UDP_DSP1_PORT 49158
////////////////////////////////////////////////////////////////////////
// I2C addresses
diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp
index b20b6652e..b4f3e0873 100644
--- a/host/lib/usrp/usrp2/io_impl.cpp
+++ b/host/lib/usrp/usrp2/io_impl.cpp
@@ -18,6 +18,7 @@
#include "../../transport/vrt_packet_handler.hpp"
#include "usrp2_impl.hpp"
#include "usrp2_regs.hpp"
+#include <uhd/usrp/mboard_props.hpp>
#include <uhd/utils/byteswap.hpp>
#include <uhd/utils/thread_priority.hpp>
#include <uhd/transport/bounded_buffer.hpp>
@@ -119,27 +120,26 @@ private:
**********************************************************************/
struct usrp2_impl::io_impl{
- io_impl(size_t send_frame_size, const std::vector<zero_copy_if::sptr> &xports):
- xports(xports),
+ io_impl(std::vector<zero_copy_if::sptr> &dsp_xports):
+ dsp_xports(dsp_xports), //the assumption is that all data transports should be identical
get_recv_buffs_fcn(boost::bind(&usrp2_impl::io_impl::get_recv_buffs, this, _1)),
get_send_buffs_fcn(boost::bind(&usrp2_impl::io_impl::get_send_buffs, this, _1)),
- packet_handler_recv_state(xports.size()),
- packet_handler_send_state(xports.size()),
async_msg_fifo(100/*messages deep*/)
{
- for (size_t i = 0; i < xports.size(); i++){
- fc_mons.push_back(flow_control_monitor::sptr(
- new flow_control_monitor(usrp2_impl::sram_bytes/send_frame_size)
- ));
- //init empty packet infos
- vrt::if_packet_info_t packet_info;
- packet_info.packet_count = 0xf;
- packet_info.has_tsi = true;
- packet_info.tsi = 0;
- packet_info.has_tsf = true;
- packet_info.tsf = 0;
- prev_infos.push_back(packet_info);
+ for (size_t i = 0; i < dsp_xports.size(); i++){
+ fc_mons.push_back(flow_control_monitor::sptr(new flow_control_monitor(
+ usrp2_impl::sram_bytes/dsp_xports.front()->get_send_frame_size()
+ )));;
}
+
+ //init empty packet infos
+ vrt::if_packet_info_t packet_info = vrt::if_packet_info_t();
+ packet_info.packet_count = 0xf;
+ packet_info.has_tsi = true;
+ packet_info.tsi = 0;
+ packet_info.has_tsf = true;
+ packet_info.tsf = 0;
+ prev_infos.resize(dsp_xports.size(), packet_info);
}
~io_impl(void){
@@ -149,15 +149,15 @@ struct usrp2_impl::io_impl{
}
bool get_send_buffs(vrt_packet_handler::managed_send_buffs_t &buffs){
- UHD_ASSERT_THROW(xports.size() == buffs.size());
+ UHD_ASSERT_THROW(send_map.size() == buffs.size());
//calculate the flow control word
const boost::uint32_t fc_word32 = packet_handler_send_state.next_packet_seq;
//grab a managed buffer for each index
for (size_t i = 0; i < buffs.size(); i++){
- if (not fc_mons[i]->check_fc_condition(fc_word32, send_timeout)) return false;
- buffs[i] = xports[i]->get_send_buff(send_timeout);
+ if (not fc_mons[send_map[i]]->check_fc_condition(fc_word32, send_timeout)) return false;
+ buffs[i] = dsp_xports[send_map[i]]->get_send_buff(send_timeout);
if (not buffs[i].get()) return false;
buffs[i]->cast<boost::uint32_t *>()[0] = uhd::htonx(fc_word32);
}
@@ -166,7 +166,10 @@ struct usrp2_impl::io_impl{
bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs);
- const std::vector<zero_copy_if::sptr> &xports;
+ std::vector<zero_copy_if::sptr> &dsp_xports;
+
+ //mappings from channel index to dsp xport
+ std::vector<size_t> send_map, recv_map;
//timeouts set on calls to recv/send (passed into get buffs methods)
double recv_timeout, send_timeout;
@@ -186,7 +189,7 @@ struct usrp2_impl::io_impl{
vrt_packet_handler::send_state packet_handler_send_state;
//methods and variables for the pirate crew
- void recv_pirate_loop(zero_copy_if::sptr, usrp2_mboard_impl::sptr, size_t);
+ void recv_pirate_loop(usrp2_mboard_impl::sptr, zero_copy_if::sptr, size_t);
boost::thread_group recv_pirate_crew;
bool recv_pirate_crew_raiding;
bounded_buffer<async_metadata_t> async_msg_fifo;
@@ -200,17 +203,18 @@ struct usrp2_impl::io_impl{
* - put async message packets into queue
**********************************************************************/
void usrp2_impl::io_impl::recv_pirate_loop(
- zero_copy_if::sptr zc_if_err0,
- usrp2_mboard_impl::sptr mboard,
- size_t index
+ usrp2_mboard_impl::sptr mboard, zero_copy_if::sptr err_xport, size_t index
){
set_thread_priority_safe();
recv_pirate_crew_raiding = true;
spawn_mutex.unlock();
+ //store a reference to the flow control monitor (offset by max dsps)
+ flow_control_monitor &fc_mon = *(this->fc_mons[index*usrp2_mboard_impl::MAX_NUM_DSPS]);
+
while(recv_pirate_crew_raiding){
- managed_recv_buffer::sptr buff = zc_if_err0->get_recv_buff();
+ managed_recv_buffer::sptr buff = err_xport->get_recv_buff();
if (not buff.get()) continue; //ignore timeout/error buffers
try{
@@ -235,7 +239,7 @@ void usrp2_impl::io_impl::recv_pirate_loop(
//catch the flow control packets and react
if (metadata.event_code == 0){
boost::uint32_t fc_word32 = (vrt_hdr + if_packet_info.num_header_words32)[1];
- this->fc_mons[index]->update_fc_condition(uhd::ntohx(fc_word32));
+ fc_mon.update_fc_condition(uhd::ntohx(fc_word32));
continue;
}
@@ -258,27 +262,52 @@ void usrp2_impl::io_impl::recv_pirate_loop(
**********************************************************************/
void usrp2_impl::io_init(void){
- //the assumption is that all data transports should be identical
- const size_t send_frame_size = _data_transports.front()->get_send_frame_size();
-
//create new io impl
- _io_impl = UHD_PIMPL_MAKE(io_impl, (send_frame_size, _data_transports));
+ _io_impl = UHD_PIMPL_MAKE(io_impl, (dsp_xports));
//create a new pirate thread for each zc if (yarr!!)
- for (size_t i = 0; i < _data_transports.size(); i++){
+ for (size_t i = 0; i < _mboards.size(); i++){
//lock the unlocked mutex (non-blocking)
_io_impl->spawn_mutex.lock();
//spawn a new pirate to plunder the recv booty
_io_impl->recv_pirate_crew.create_thread(boost::bind(
&usrp2_impl::io_impl::recv_pirate_loop,
- _io_impl.get(), _err0_transports.at(i),
- _mboards.at(i), i
+ _io_impl.get(), _mboards.at(i), err_xports.at(i), i
));
//block here until the spawned thread unlocks
_io_impl->spawn_mutex.lock();
//exit loop iteration in an unlocked condition
_io_impl->spawn_mutex.unlock();
}
+
+ //update mapping here since it didnt b4 when io init not called first
+ update_xport_channel_mapping();
+}
+
+void usrp2_impl::update_xport_channel_mapping(void){
+ if (_io_impl.get() == NULL) return; //not inited yet
+
+ _io_impl->recv_map.clear();
+ _io_impl->send_map.clear();
+
+ for (size_t i = 0; i < _mboards.size(); i++){
+
+ subdev_spec_t rx_subdev_spec = _mboards[i]->get_link()[MBOARD_PROP_RX_SUBDEV_SPEC].as<subdev_spec_t>();
+ for (size_t j = 0; j < rx_subdev_spec.size(); j++){
+ _io_impl->recv_map.push_back(i*usrp2_mboard_impl::MAX_NUM_DSPS+j);
+ //std::cout << "recv_map.back() " << _io_impl->recv_map.back() << std::endl;
+ }
+
+ subdev_spec_t tx_subdev_spec = _mboards[i]->get_link()[MBOARD_PROP_TX_SUBDEV_SPEC].as<subdev_spec_t>();
+ for (size_t j = 0; j < tx_subdev_spec.size(); j++){
+ _io_impl->send_map.push_back(i*usrp2_mboard_impl::MAX_NUM_DSPS+j);
+ //std::cout << "send_map.back() " << _io_impl->send_map.back() << std::endl;
+ }
+
+ }
+
+ _io_impl->packet_handler_recv_state = vrt_packet_handler::recv_state(_io_impl->recv_map.size());
+ _io_impl->packet_handler_send_state = vrt_packet_handler::send_state(_io_impl->send_map.size());
}
/***********************************************************************
@@ -300,7 +329,7 @@ size_t usrp2_impl::get_max_send_samps_per_packet(void) const{
+ vrt_send_header_offset_words32*sizeof(boost::uint32_t)
- sizeof(vrt::if_packet_info_t().cid) //no class id ever used
;
- const size_t bpp = _data_transports.front()->get_send_frame_size() - hdr_size;
+ const size_t bpp = dsp_xports.front()->get_send_frame_size() - hdr_size;
return bpp/_tx_otw_type.get_sample_size();
}
@@ -383,14 +412,15 @@ UHD_INLINE bool usrp2_impl::io_impl::get_recv_buffs(
vrt_packet_handler::managed_recv_buffs_t &buffs
){
if (buffs.size() == 1){
- buffs[0] = xports[0]->get_recv_buff(recv_timeout);
+ buffs[0] = dsp_xports[recv_map[0]]->get_recv_buff(recv_timeout);
if (buffs[0].get() == NULL) return false;
bool clear, msg; time_spec_t time; //unused variables
//call extract_packet_info to handle printing the overflows
- extract_packet_info(buffs[0], this->prev_infos[0], time, clear, msg);
+ extract_packet_info(buffs[0], this->prev_infos[recv_map[0]], time, clear, msg);
return true;
}
//-------------------- begin alignment logic ---------------------//
+ UHD_ASSERT_THROW(recv_map.size() == buffs.size());
boost::system_time exit_time = boost::get_system_time() + to_time_dur(recv_timeout);
managed_recv_buffer::sptr buff_tmp;
alignment_indexes indexes_to_do;
@@ -404,9 +434,9 @@ UHD_INLINE bool usrp2_impl::io_impl::get_recv_buffs(
//do an initial pop to load an initial sequence id
size_t index = indexes_to_do.front();
- buff_tmp = xports[index]->get_recv_buff(from_time_dur(exit_time - boost::get_system_time()));
+ buff_tmp = dsp_xports[recv_map[index]]->get_recv_buff(from_time_dur(exit_time - boost::get_system_time()));
if (buff_tmp.get() == NULL) return false;
- extract_packet_info(buff_tmp, this->prev_infos[index], expected_time, clear, msg);
+ extract_packet_info(buff_tmp, this->prev_infos[recv_map[index]], expected_time, clear, msg);
if (clear) goto got_clear;
buffs[index] = buff_tmp;
if (msg) return handle_msg_packet(buffs, index);
@@ -417,10 +447,10 @@ UHD_INLINE bool usrp2_impl::io_impl::get_recv_buffs(
//pop an element off for this index
index = indexes_to_do.front();
- buff_tmp = xports[index]->get_recv_buff(from_time_dur(exit_time - boost::get_system_time()));
+ buff_tmp = dsp_xports[recv_map[index]]->get_recv_buff(from_time_dur(exit_time - boost::get_system_time()));
if (buff_tmp.get() == NULL) return false;
time_spec_t this_time;
- extract_packet_info(buff_tmp, this->prev_infos[index], this_time, clear, msg);
+ extract_packet_info(buff_tmp, this->prev_infos[recv_map[index]], this_time, clear, msg);
if (clear) goto got_clear;
buffs[index] = buff_tmp;
if (msg) return handle_msg_packet(buffs, index);
@@ -458,13 +488,14 @@ size_t usrp2_impl::get_max_recv_samps_per_packet(void) const{
+ sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer
- sizeof(vrt::if_packet_info_t().cid) //no class id ever used
;
- const size_t bpp = _data_transports.front()->get_recv_frame_size() - hdr_size;
+ const size_t bpp = dsp_xports.front()->get_recv_frame_size() - hdr_size;
return bpp/_rx_otw_type.get_sample_size();
}
-static void handle_overflow(std::vector<usrp2_mboard_impl::sptr> &mboards, size_t chan){
+void usrp2_impl::handle_overflow(size_t chan){
std::cerr << "O" << std::flush;
- mboards.at(chan/mboards.size())->handle_overflow();
+ ldiv_t indexes = ldiv(chan, usrp2_mboard_impl::NUM_RX_DSPS);
+ _mboards.at(indexes.quot)->handle_overflow(indexes.rem);
}
size_t usrp2_impl::recv(
@@ -481,6 +512,6 @@ size_t usrp2_impl::recv(
_mboards.front()->get_master_clock_freq(), //master clock tick rate
uhd::transport::vrt::if_hdr_unpack_be,
_io_impl->get_recv_buffs_fcn,
- boost::bind(&handle_overflow, boost::ref(_mboards), _1)
+ boost::bind(&usrp2_impl::handle_overflow, this, _1)
);
}
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 397fae636..34a2b7c69 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -21,8 +21,8 @@
#include <uhd/usrp/misc_utils.hpp>
#include <uhd/usrp/dsp_utils.hpp>
#include <uhd/usrp/mboard_props.hpp>
-#include <uhd/utils/assert.hpp>
#include <uhd/utils/byteswap.hpp>
+#include <uhd/utils/assert.hpp>
#include <uhd/utils/algorithm.hpp>
#include <boost/bind.hpp>
#include <iostream>
@@ -33,35 +33,55 @@ static const size_t mimo_clock_sync_delay_cycles = 137;
using namespace uhd;
using namespace uhd::usrp;
+using namespace uhd::transport;
/***********************************************************************
- * Structors
+ * Helpers
**********************************************************************/
-usrp2_mboard_impl::usrp2_mboard_impl(
- size_t index,
- transport::udp_simple::sptr ctrl_transport,
- transport::zero_copy_if::sptr data_transport,
- transport::zero_copy_if::sptr err0_transport,
- const device_addr_t &device_args,
- size_t recv_samps_per_packet
-):
- _index(index),
- _iface(usrp2_iface::make(ctrl_transport))
-{
+static void init_xport(zero_copy_if::sptr xport){
//Send a small data packet so the usrp2 knows the udp source port.
//This setup must happen before further initialization occurs
//or the async update packets will cause ICMP destination unreachable.
- transport::managed_send_buffer::sptr send_buff;
static const boost::uint32_t data[2] = {
uhd::htonx(boost::uint32_t(0 /* don't care seq num */)),
uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER))
};
- send_buff = data_transport->get_send_buff();
- std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
- send_buff->commit(sizeof(data));
- send_buff = err0_transport->get_send_buff();
+
+ transport::managed_send_buffer::sptr send_buff = xport->get_send_buff();
std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
send_buff->commit(sizeof(data));
+}
+
+/***********************************************************************
+ * Structors
+ **********************************************************************/
+usrp2_mboard_impl::usrp2_mboard_impl(
+ const device_addr_t &device_addr,
+ size_t index, usrp2_impl &device
+):
+ _index(index), _device(device),
+ _iface(usrp2_iface::make(udp_simple::make_connected(
+ device_addr["addr"], boost::lexical_cast<std::string>(USRP2_UDP_CTRL_PORT)
+ )))
+{
+ //construct transports for dsp and async errors
+ std::cout << "Making transport for DSP0..." << std::endl;
+ device.dsp_xports.push_back(udp_zero_copy::make(
+ device_addr["addr"], boost::lexical_cast<std::string>(USRP2_UDP_DSP0_PORT), device_addr
+ ));
+ init_xport(device.dsp_xports.back());
+
+ std::cout << "Making transport for DSP1..." << std::endl;
+ device.dsp_xports.push_back(udp_zero_copy::make(
+ device_addr["addr"], boost::lexical_cast<std::string>(USRP2_UDP_DSP1_PORT), device_addr
+ ));
+ init_xport(device.dsp_xports.back());
+
+ std::cout << "Making transport for ERR0..." << std::endl;
+ device.err_xports.push_back(udp_zero_copy::make(
+ device_addr["addr"], boost::lexical_cast<std::string>(USRP2_UDP_ERR0_PORT), device_addr_t()
+ ));
+ init_xport(device.err_xports.back());
//contruct the interfaces to mboard perifs
_clock_ctrl = usrp2_clock_ctrl::make(_iface);
@@ -72,66 +92,30 @@ usrp2_mboard_impl::usrp2_mboard_impl(
//if(_gps_ctrl->gps_detected()) std::cout << "GPS time: " << _gps_ctrl->get_time() << std::endl;
- //TODO move to dsp impl...
- //load the allowed decim/interp rates
- //_USRP2_RATES = range(4, 128+1, 1) + range(130, 256+1, 2) + range(260, 512+1, 4)
- _allowed_decim_and_interp_rates.clear();
- for (size_t i = 4; i <= 128; i+=1){
- _allowed_decim_and_interp_rates.push_back(i);
- }
- for (size_t i = 130; i <= 256; i+=2){
- _allowed_decim_and_interp_rates.push_back(i);
- }
- for (size_t i = 260; i <= 512; i+=4){
- _allowed_decim_and_interp_rates.push_back(i);
- }
-
- //setup the vrt rx registers
- _iface->poke32(_iface->regs.rx_ctrl_clear_overrun, 1); //reset
- _iface->poke32(_iface->regs.rx_ctrl_nsamps_per_pkt, recv_samps_per_packet);
- _iface->poke32(_iface->regs.rx_ctrl_nchannels, 1);
- _iface->poke32(_iface->regs.rx_ctrl_vrt_header, 0
- | (0x1 << 28) //if data with stream id
- | (0x1 << 26) //has trailer
- | (0x3 << 22) //integer time other
- | (0x1 << 20) //fractional time sample count
- );
- _iface->poke32(_iface->regs.rx_ctrl_vrt_stream_id, usrp2_impl::RECV_SID);
- _iface->poke32(_iface->regs.rx_ctrl_vrt_trailer, 0);
- _iface->poke32(_iface->regs.time64_tps, size_t(get_master_clock_freq()));
-
- //init the tx control registers
- _iface->poke32(_iface->regs.tx_ctrl_clear_state, 1); //reset
- _iface->poke32(_iface->regs.tx_ctrl_num_chan, 0); //1 channel
- _iface->poke32(_iface->regs.tx_ctrl_report_sid, usrp2_impl::ASYNC_SID);
- _iface->poke32(_iface->regs.tx_ctrl_policy, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET);
+ //init the dsp stuff (before setting update packets)
+ dsp_init();
//setting the cycles per update (disabled by default)
- const double ups_per_sec = device_args.cast<double>("ups_per_sec", 0.0);
+ const double ups_per_sec = device_addr.cast<double>("ups_per_sec", 0.0);
if (ups_per_sec > 0.0){
const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec);
_iface->poke32(_iface->regs.tx_ctrl_cycles_per_up, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up);
}
//setting the packets per update (enabled by default)
- const double ups_per_fifo = device_args.cast<double>("ups_per_fifo", 8.0);
+ size_t send_frame_size = device.dsp_xports[0]->get_send_frame_size();
+ const double ups_per_fifo = device_addr.cast<double>("ups_per_fifo", 8.0);
if (ups_per_fifo > 0.0){
- const size_t packets_per_up = size_t(usrp2_impl::sram_bytes/ups_per_fifo/data_transport->get_send_frame_size());
+ const size_t packets_per_up = size_t(usrp2_impl::sram_bytes/ups_per_fifo/send_frame_size);
_iface->poke32(_iface->regs.tx_ctrl_packets_per_up, U2_FLAG_TX_CTRL_UP_ENB | packets_per_up);
}
- //init the ddc
- init_ddc_config();
-
- //init the duc
- init_duc_config();
-
//initialize the clock configuration
- if (device_args.has_key("mimo_mode")){
- if (device_args["mimo_mode"] == "master"){
+ if (device_addr.has_key("mimo_mode")){
+ if (device_addr["mimo_mode"] == "master"){
_mimo_clocking_mode_is_master = true;
}
- else if (device_args["mimo_mode"] == "slave"){
+ else if (device_addr["mimo_mode"] == "slave"){
_mimo_clocking_mode_is_master = false;
}
else throw std::runtime_error(
@@ -158,13 +142,18 @@ usrp2_mboard_impl::usrp2_mboard_impl(
(*this)[MBOARD_PROP_RX_SUBDEV_SPEC] = subdev_spec_t();
(*this)[MBOARD_PROP_TX_SUBDEV_SPEC] = subdev_spec_t();
+ //------------------------------------------------------------------
//This is a hack/fix for the lingering packet problem.
stream_cmd_t stream_cmd(stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE);
- stream_cmd.num_samps = 1;
- this->issue_ddc_stream_cmd(stream_cmd);
- data_transport->get_recv_buff().get(); //recv with timeout for lingering
- data_transport->get_recv_buff().get(); //recv with timeout for expected
- _iface->poke32(_iface->regs.rx_ctrl_clear_overrun, 1); //resets sequence
+ for (size_t i = 0; i < NUM_RX_DSPS; i++){
+ size_t index = device.dsp_xports.size() - NUM_RX_DSPS + i;
+ stream_cmd.num_samps = 1;
+ this->issue_ddc_stream_cmd(stream_cmd, i);
+ device.dsp_xports.at(index)->get_recv_buff(0.01).get(); //recv with timeout for lingering
+ device.dsp_xports.at(index)->get_recv_buff(0.01).get(); //recv with timeout for expected
+ _iface->poke32(_iface->regs.rx_ctrl[i].clear_overrun, 1); //resets sequence
+ }
+ //------------------------------------------------------------------
}
usrp2_mboard_impl::~usrp2_mboard_impl(void){
@@ -265,19 +254,6 @@ void usrp2_mboard_impl::set_time_spec(const time_spec_t &time_spec, bool now){
_iface->poke32(_iface->regs.time64_secs, boost::uint32_t(time_spec.get_full_secs()));
}
-void usrp2_mboard_impl::handle_overflow(void){
- if (_continuous_streaming){ //re-issue the stream command if already continuous
- this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
- }
-}
-
-void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
- _continuous_streaming = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS;
- _iface->poke32(_iface->regs.rx_ctrl_stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd));
- _iface->poke32(_iface->regs.rx_ctrl_time_secs, boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
- _iface->poke32(_iface->regs.rx_ctrl_time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
-}
-
/***********************************************************************
* MBoard Get Properties
**********************************************************************/
@@ -314,21 +290,19 @@ void usrp2_mboard_impl::get(const wax::obj &key_, wax::obj &val){
return;
case MBOARD_PROP_RX_DSP:
- UHD_ASSERT_THROW(key.name == "");
- val = _rx_dsp_proxy->get_link();
+ val = _rx_dsp_proxies[key.name]->get_link();
return;
case MBOARD_PROP_RX_DSP_NAMES:
- val = prop_names_t(1, "");
+ val = _rx_dsp_proxies.keys();
return;
case MBOARD_PROP_TX_DSP:
- UHD_ASSERT_THROW(key.name == "");
- val = _tx_dsp_proxy->get_link();
+ val = _tx_dsp_proxies[key.name]->get_link();
return;
case MBOARD_PROP_TX_DSP_NAMES:
- val = prop_names_t(1, "");
+ val = _tx_dsp_proxies.keys();
return;
case MBOARD_PROP_CLOCK_CONFIG:
@@ -391,30 +365,32 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){
set_time_spec(val.as<time_spec_t>(), false);
return;
- case MBOARD_PROP_STREAM_CMD:
- issue_ddc_stream_cmd(val.as<stream_cmd_t>());
- return;
-
case MBOARD_PROP_RX_SUBDEV_SPEC:
_rx_subdev_spec = val.as<subdev_spec_t>();
verify_rx_subdev_spec(_rx_subdev_spec, this->get_link());
//sanity check
- UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1);
+ UHD_ASSERT_THROW(_rx_subdev_spec.size() <= NUM_RX_DSPS);
//set the mux
- _iface->poke32(_iface->regs.dsp_rx_mux, dsp_type1::calc_rx_mux_word(
- _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
- ));
+ for (size_t i = 0; i < _rx_subdev_spec.size(); i++){
+ if (_rx_subdev_spec.size() >= 1) _iface->poke32(_iface->regs.dsp_rx[i].mux, dsp_type1::calc_rx_mux_word(
+ _dboard_manager->get_rx_subdev(_rx_subdev_spec[i].sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
+ ));
+ }
+ _device.update_xport_channel_mapping();
return;
case MBOARD_PROP_TX_SUBDEV_SPEC:
_tx_subdev_spec = val.as<subdev_spec_t>();
verify_tx_subdev_spec(_tx_subdev_spec, this->get_link());
//sanity check
- UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1);
+ UHD_ASSERT_THROW(_tx_subdev_spec.size() <= NUM_TX_DSPS);
//set the mux
- _iface->poke32(_iface->regs.dsp_tx_mux, dsp_type1::calc_tx_mux_word(
- _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
- ));
+ for (size_t i = 0; i < _rx_subdev_spec.size(); i++){
+ _iface->poke32(_iface->regs.dsp_tx_mux, dsp_type1::calc_tx_mux_word(
+ _dboard_manager->get_tx_subdev(_tx_subdev_spec[i].sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
+ ));
+ }
+ _device.update_xport_channel_mapping();
return;
case MBOARD_PROP_EEPROM_MAP:
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index 9ce0f7359..95031d211 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -22,14 +22,13 @@
#include <uhd/utils/assert.hpp>
#include <uhd/utils/static.hpp>
#include <uhd/utils/warning.hpp>
-#include <boost/algorithm/string.hpp> //for split
+#include <uhd/utils/byteswap.hpp>
#include <boost/assign/list_of.hpp>
#include <boost/format.hpp>
#include <boost/foreach.hpp>
#include <boost/lexical_cast.hpp>
-#include <boost/regex.hpp>
#include <boost/bind.hpp>
-#include <boost/asio.hpp> //htonl and ntohl
+#include <boost/asio/ip/address_v4.hpp>
#include <iostream>
#include <vector>
@@ -39,66 +38,11 @@ using namespace uhd::transport;
namespace asio = boost::asio;
/***********************************************************************
- * Helper Functions
- **********************************************************************/
-template <class T> std::string num2str(T num){
- return boost::lexical_cast<std::string>(num);
-}
-
-//! separate indexed device addresses into a vector of device addresses
-device_addrs_t sep_indexed_dev_addrs(const device_addr_t &dev_addr){
- //------------ support old deprecated way and print warning --------
- if (dev_addr.has_key("addr") and not dev_addr["addr"].empty()){
- std::vector<std::string> addrs; boost::split(addrs, dev_addr["addr"], boost::is_any_of(" "));
- if (addrs.size() > 1){
- device_addr_t fixed_dev_addr = dev_addr;
- fixed_dev_addr.pop("addr");
- for (size_t i = 0; i < addrs.size(); i++){
- fixed_dev_addr[str(boost::format("addr%d") % i)] = addrs[i];
- }
- uhd::warning::post(
- "addr = <space separated list of ip addresses> is deprecated.\n"
- "To address a multi-device, use multiple <key><index> = <val>.\n"
- "See the USRP-NXXX application notes. Two device example:\n"
- " addr0 = 192.168.10.2\n"
- " addr1 = 192.168.10.3\n"
- );
- return sep_indexed_dev_addrs(fixed_dev_addr);
- }
- }
- //------------------------------------------------------------------
- device_addrs_t dev_addrs;
- BOOST_FOREACH(const std::string &key, dev_addr.keys()){
- boost::cmatch matches;
- if (not boost::regex_match(key.c_str(), matches, boost::regex("^(\\D+)(\\d*)$"))){
- throw std::runtime_error("unknown key format: " + key);
- }
- std::string key_part(matches[1].first, matches[1].second);
- std::string num_part(matches[2].first, matches[2].second);
- size_t num = (num_part.empty())? 0 : boost::lexical_cast<size_t>(num_part);
- dev_addrs.resize(std::max(num+1, dev_addrs.size()));
- dev_addrs[num][key_part] = dev_addr[key];
- }
- return dev_addrs;
-}
-
-//! combine a vector in device addresses into an indexed device address
-device_addr_t combine_dev_addr_vector(const device_addrs_t &dev_addrs){
- device_addr_t dev_addr;
- for (size_t i = 0; i < dev_addrs.size(); i++){
- BOOST_FOREACH(const std::string &key, dev_addrs[i].keys()){
- dev_addr[str(boost::format("%s%d") % key % i)] = dev_addrs[i][key];
- }
- }
- return dev_addr;
-}
-
-/***********************************************************************
* Discovery over the udp transport
**********************************************************************/
static device_addrs_t usrp2_find(const device_addr_t &hint_){
//handle the multi-device discovery
- device_addrs_t hints = sep_indexed_dev_addrs(hint_);
+ device_addrs_t hints = separate_device_addr(hint_);
if (hints.size() > 1){
device_addrs_t found_devices;
BOOST_FOREACH(const device_addr_t &hint_i, hints){
@@ -108,7 +52,7 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
) % hint_i.to_string()));
found_devices.push_back(found_devices_i[0]);
}
- return device_addrs_t(1, combine_dev_addr_vector(found_devices));
+ return device_addrs_t(1, combine_device_addrs(found_devices));
}
//initialize the hint for a single device case
@@ -147,8 +91,8 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
//send a hello control packet
usrp2_ctrl_data_t ctrl_data_out;
- ctrl_data_out.proto_ver = htonl(USRP2_FW_COMPAT_NUM);
- ctrl_data_out.id = htonl(USRP2_CTRL_ID_WAZZUP_BRO);
+ ctrl_data_out.proto_ver = uhd::htonx<boost::uint32_t>(USRP2_FW_COMPAT_NUM);
+ ctrl_data_out.id = uhd::htonx<boost::uint32_t>(USRP2_CTRL_ID_WAZZUP_BRO);
udp_transport->send(boost::asio::buffer(&ctrl_data_out, sizeof(ctrl_data_out)));
//loop and recieve until the timeout
@@ -157,9 +101,9 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
while(true){
size_t len = udp_transport->recv(asio::buffer(usrp2_ctrl_data_in_mem));
//std::cout << len << "\n";
- if (len > offsetof(usrp2_ctrl_data_t, data) and ntohl(ctrl_data_in->id) == USRP2_CTRL_ID_WAZZUP_DUDE){
+ if (len > offsetof(usrp2_ctrl_data_t, data) and uhd::ntohx(ctrl_data_in->id) == USRP2_CTRL_ID_WAZZUP_DUDE){
//make a boost asio ipv4 with the raw addr in host byte order
- boost::asio::ip::address_v4 ip_addr(ntohl(ctrl_data_in->data.ip_addr));
+ boost::asio::ip::address_v4 ip_addr(uhd::ntohx(ctrl_data_in->data.ip_addr));
device_addr_t new_addr;
new_addr["type"] = "usrp2";
new_addr["addr"] = ip_addr.to_string();
@@ -167,9 +111,9 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
//This operation can throw due to compatibility mismatch.
//In this case, the discovered device will be ignored.
try{
- mboard_eeprom_t mb_eeprom = usrp2_iface::make(
- udp_simple::make_connected(new_addr["addr"], num2str(USRP2_UDP_CTRL_PORT))
- )->mb_eeprom;
+ mboard_eeprom_t mb_eeprom = usrp2_iface::make(udp_simple::make_connected(
+ new_addr["addr"], boost::lexical_cast<std::string>(USRP2_UDP_CTRL_PORT)
+ ))->mb_eeprom;
new_addr["name"] = mb_eeprom["name"];
new_addr["serial"] = mb_eeprom["serial"];
if (
@@ -197,40 +141,21 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
/***********************************************************************
* Make
**********************************************************************/
-static device::sptr usrp2_make(const device_addr_t &device_addr){
+static device::sptr usrp2_make(const device_addr_t &_device_addr){
+ device_addr_t device_addr = _device_addr;
//setup the dsp transport hints (default to a large recv buff)
- device_addr_t dsp_xport_hints = device_addr;
- if (not dsp_xport_hints.has_key("recv_buff_size")){
- //only enable on platforms that are happy with the large buffer resize
- #if defined(UHD_PLATFORM_LINUX) || defined(UHD_PLATFORM_WIN32)
+ if (not device_addr.has_key("recv_buff_size")){
+ #if defined(UHD_PLATFORM_MACOS) || defined(UHD_PLATFORM_BSD)
+ //limit buffer resize on macos or it will error
+ device_addr["recv_buff_size"] = "1e6";
+ #elif defined(UHD_PLATFORM_LINUX) || defined(UHD_PLATFORM_WIN32)
//set to half-a-second of buffering at max rate
- dsp_xport_hints["recv_buff_size"] = "50e6";
- #endif /*defined(UHD_PLATFORM_LINUX) || defined(UHD_PLATFORM_WIN32)*/
- }
-
- //create a ctrl and data transport for each address
- std::vector<udp_simple::sptr> ctrl_transports;
- std::vector<zero_copy_if::sptr> data_transports;
- std::vector<zero_copy_if::sptr> err0_transports;
- const device_addrs_t device_addrs = sep_indexed_dev_addrs(device_addr);
-
- BOOST_FOREACH(const device_addr_t &dev_addr_i, device_addrs){
- ctrl_transports.push_back(udp_simple::make_connected(
- dev_addr_i["addr"], num2str(USRP2_UDP_CTRL_PORT)
- ));
- data_transports.push_back(udp_zero_copy::make(
- dev_addr_i["addr"], num2str(USRP2_UDP_DATA_PORT), dsp_xport_hints
- ));
- err0_transports.push_back(udp_zero_copy::make(
- dev_addr_i["addr"], num2str(USRP2_UDP_ERR0_PORT), device_addr_t()
- ));
+ device_addr["recv_buff_size"] = "50e6";
+ #endif
}
- //create the usrp2 implementation guts
- return device::sptr(new usrp2_impl(
- ctrl_transports, data_transports, err0_transports, device_addrs
- ));
+ return device::sptr(new usrp2_impl(device_addr));
}
UHD_STATIC_BLOCK(register_usrp2_device){
@@ -240,15 +165,9 @@ UHD_STATIC_BLOCK(register_usrp2_device){
/***********************************************************************
* Structors
**********************************************************************/
-usrp2_impl::usrp2_impl(
- std::vector<udp_simple::sptr> ctrl_transports,
- std::vector<zero_copy_if::sptr> data_transports,
- std::vector<zero_copy_if::sptr> err0_transports,
- const device_addrs_t &device_args
-):
- _data_transports(data_transports),
- _err0_transports(err0_transports)
-{
+usrp2_impl::usrp2_impl(const device_addr_t &device_addr){
+ device_addrs_t device_args = separate_device_addr(device_addr);
+
//setup rx otw type
_rx_otw_type.width = 16;
_rx_otw_type.shift = 0;
@@ -263,13 +182,16 @@ usrp2_impl::usrp2_impl(
//create a new mboard handler for each control transport
for(size_t i = 0; i < device_args.size(); i++){
- _mboards.push_back(usrp2_mboard_impl::sptr(new usrp2_mboard_impl(
- i, ctrl_transports[i], data_transports[i],
- err0_transports[i], device_args[i],
- this->get_max_recv_samps_per_packet()
- )));
+ device_addr_t dev_addr_i = device_args[i];
+ BOOST_FOREACH(const std::string &key, device_addr.keys()){
+ if (dev_addr_i.has_key(key)) continue;
+ dev_addr_i[key] = device_addr[key];
+ }
+ _mboards.push_back(usrp2_mboard_impl::sptr(
+ new usrp2_mboard_impl(dev_addr_i, i, *this)
+ ));
//use an empty name when there is only one mboard
- std::string name = (ctrl_transports.size() > 1)? boost::lexical_cast<std::string>(i) : "";
+ std::string name = (device_args.size() > 1)? boost::lexical_cast<std::string>(i) : "";
_mboard_dict[name] = _mboards.back();
}
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index 337f842d6..0676cecf2 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -71,6 +71,8 @@ private:
void set(const wax::obj &key, const wax::obj &val){return _set(key, val);}
};
+class usrp2_impl;
+
/*!
* USRP2 mboard implementation guts:
* The implementation details are encapsulated here.
@@ -80,14 +82,14 @@ class usrp2_mboard_impl : public wax::obj{
public:
typedef boost::shared_ptr<usrp2_mboard_impl> sptr;
+ static const size_t NUM_RX_DSPS = 2;
+ static const size_t NUM_TX_DSPS = 1;
+ static const size_t MAX_NUM_DSPS = 2;
+
//structors
usrp2_mboard_impl(
- size_t index,
- uhd::transport::udp_simple::sptr,
- uhd::transport::zero_copy_if::sptr,
- uhd::transport::zero_copy_if::sptr,
- const uhd::device_addr_t &device_args,
- size_t recv_samps_per_packet
+ const uhd::device_addr_t &device_addr,
+ size_t index, usrp2_impl &device
);
~usrp2_mboard_impl(void);
@@ -95,11 +97,11 @@ public:
return _clock_ctrl->get_master_clock_rate();
}
- void handle_overflow(void);
+ void handle_overflow(size_t);
private:
size_t _index;
- bool _continuous_streaming;
+ usrp2_impl &_device;
bool _mimo_clocking_mode_is_master;
//interfaces
@@ -147,27 +149,20 @@ private:
wax_obj_proxy::sptr _tx_dboard_proxy;
uhd::usrp::dboard_eeprom_t _tx_db_eeprom;
- //methods and shadows for the ddc dsp
- std::vector<size_t> _allowed_decim_and_interp_rates;
- size_t _ddc_decim;
- double _ddc_freq;
- void init_ddc_config(void);
- void issue_ddc_stream_cmd(const uhd::stream_cmd_t &stream_cmd);
-
- //methods and shadows for the duc dsp
- size_t _duc_interp;
- double _duc_freq;
- void init_duc_config(void);
+ //methods and shadows for the dsps
+ UHD_PIMPL_DECL(dsp_impl) _dsp_impl;
+ void dsp_init(void);
+ void issue_ddc_stream_cmd(const uhd::stream_cmd_t &, size_t);
//properties interface for ddc
- void ddc_get(const wax::obj &, wax::obj &);
- void ddc_set(const wax::obj &, const wax::obj &);
- wax_obj_proxy::sptr _rx_dsp_proxy;
+ void ddc_get(const wax::obj &, wax::obj &, size_t);
+ void ddc_set(const wax::obj &, const wax::obj &, size_t);
+ uhd::dict<std::string, wax_obj_proxy::sptr> _rx_dsp_proxies;
//properties interface for duc
- void duc_get(const wax::obj &, wax::obj &);
- void duc_set(const wax::obj &, const wax::obj &);
- wax_obj_proxy::sptr _tx_dsp_proxy;
+ void duc_get(const wax::obj &, wax::obj &, size_t);
+ void duc_set(const wax::obj &, const wax::obj &, size_t);
+ uhd::dict<std::string, wax_obj_proxy::sptr> _tx_dsp_proxies;
};
@@ -182,19 +177,7 @@ public:
static const boost::uint32_t RECV_SID = 1;
static const boost::uint32_t ASYNC_SID = 2;
- /*!
- * Create a new usrp2 impl base.
- * \param ctrl_transports the udp transports for control
- * \param data_transports the udp transports for data
- * \param err0_transports the udp transports for error
- * \param device_args optional misc device parameters
- */
- usrp2_impl(
- std::vector<uhd::transport::udp_simple::sptr> ctrl_transports,
- std::vector<uhd::transport::zero_copy_if::sptr> data_transports,
- std::vector<uhd::transport::zero_copy_if::sptr> err0_transports,
- const uhd::device_addrs_t &device_args
- );
+ usrp2_impl(const uhd::device_addr_t &);
~usrp2_impl(void);
@@ -213,6 +196,14 @@ public:
size_t get_max_recv_samps_per_packet(void) const;
bool recv_async_msg(uhd::async_metadata_t &, double);
+ void update_xport_channel_mapping(void);
+
+ //public frame sizes, set by mboard, used by io impl
+ size_t recv_frame_size, send_frame_size;
+
+ std::vector<uhd::transport::zero_copy_if::sptr> dsp_xports;
+ std::vector<uhd::transport::zero_copy_if::sptr> err_xports;
+
private:
//device properties interface
void get(const wax::obj &, wax::obj &);
@@ -223,11 +214,10 @@ private:
uhd::dict<std::string, usrp2_mboard_impl::sptr> _mboard_dict;
//io impl methods and members
- std::vector<uhd::transport::zero_copy_if::sptr> _data_transports;
- std::vector<uhd::transport::zero_copy_if::sptr> _err0_transports;
uhd::otw_type_t _rx_otw_type, _tx_otw_type;
UHD_PIMPL_DECL(io_impl) _io_impl;
void io_init(void);
+ void handle_overflow(size_t);
};
#endif /* INCLUDED_USRP2_IMPL_HPP */
diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp
index 84907c32e..66c3ac137 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.cpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.cpp
@@ -38,8 +38,10 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
x.sr_udp_sm = 96;
x.sr_tx_dsp = 208;
x.sr_tx_ctrl = 224;
- x.sr_rx_dsp = 160;
- x.sr_rx_ctrl = 176;
+ x.sr_rx_dsp0 = 160;
+ x.sr_rx_ctrl0 = 176;
+ x.sr_rx_dsp1 = 240;
+ x.sr_rx_ctrl1 = 32;
x.sr_time64 = 192;
x.sr_simtimer = 198;
x.sr_last = 255;
@@ -68,12 +70,18 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
x.dsp_tx_scale_iq = sr_addr(misc_output_base, x.sr_tx_dsp + 1);
x.dsp_tx_interp_rate = sr_addr(misc_output_base, x.sr_tx_dsp + 2);
x.dsp_tx_mux = sr_addr(misc_output_base, x.sr_tx_dsp + 4);
- x.dsp_rx_freq = sr_addr(misc_output_base, x.sr_rx_dsp + 0);
- x.dsp_rx_scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp + 1);
- x.dsp_rx_decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp + 2);
- x.dsp_rx_dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp + 3);
- x.dsp_rx_dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp + 4);
- x.dsp_rx_mux = sr_addr(misc_output_base, x.sr_rx_dsp + 5);
+ x.dsp_rx[0].freq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 0);
+ x.dsp_rx[0].scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 1);
+ x.dsp_rx[0].decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp0 + 2);
+ x.dsp_rx[0].dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp0 + 3);
+ x.dsp_rx[0].dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp0 + 4);
+ x.dsp_rx[0].mux = sr_addr(misc_output_base, x.sr_rx_dsp0 + 5);
+ x.dsp_rx[1].freq = sr_addr(misc_output_base, x.sr_rx_dsp1 + 0);
+ x.dsp_rx[1].scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp1 + 1);
+ x.dsp_rx[1].decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp1 + 2);
+ x.dsp_rx[1].dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp1 + 3);
+ x.dsp_rx[1].dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp1 + 4);
+ x.dsp_rx[1].mux = sr_addr(misc_output_base, x.sr_rx_dsp1 + 5);
x.gpio_io = gpio_base + 0;
x.gpio_ddr = gpio_base + 4;
x.gpio_tx_sel = gpio_base + 8;
@@ -86,15 +94,24 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
x.atr_inrx_rxside = atr_base + 10;
x.atr_full_txside = atr_base + 12;
x.atr_full_rxside = atr_base + 14;
- x.rx_ctrl_stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl + 0);
- x.rx_ctrl_time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl + 1);
- x.rx_ctrl_time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl + 2);
- x.rx_ctrl_clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl + 3);
- x.rx_ctrl_vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl + 4);
- x.rx_ctrl_vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl + 5);
- x.rx_ctrl_vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl + 6);
- x.rx_ctrl_nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl + 7);
- x.rx_ctrl_nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl + 8);
+ x.rx_ctrl[0].stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 0);
+ x.rx_ctrl[0].time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 1);
+ x.rx_ctrl[0].time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 2);
+ x.rx_ctrl[0].clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 3);
+ x.rx_ctrl[0].vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 4);
+ x.rx_ctrl[0].vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 5);
+ x.rx_ctrl[0].vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 6);
+ x.rx_ctrl[0].nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 7);
+ x.rx_ctrl[0].nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 8);
+ x.rx_ctrl[1].stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 0);
+ x.rx_ctrl[1].time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 1);
+ x.rx_ctrl[1].time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 2);
+ x.rx_ctrl[1].clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 3);
+ x.rx_ctrl[1].vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 4);
+ x.rx_ctrl[1].vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 5);
+ x.rx_ctrl[1].vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 6);
+ x.rx_ctrl[1].nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 7);
+ x.rx_ctrl[1].nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 8);
x.tx_ctrl_num_chan = sr_addr(misc_output_base, x.sr_tx_ctrl + 0);
x.tx_ctrl_clear_state = sr_addr(misc_output_base, x.sr_tx_ctrl + 1);
x.tx_ctrl_report_sid = sr_addr(misc_output_base, x.sr_tx_ctrl + 2);
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 977b342cb..01f5ee65a 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -38,8 +38,10 @@ typedef struct {
int sr_udp_sm;
int sr_tx_dsp;
int sr_tx_ctrl;
- int sr_rx_dsp;
- int sr_rx_ctrl;
+ int sr_rx_dsp0;
+ int sr_rx_ctrl0;
+ int sr_rx_dsp1;
+ int sr_rx_ctrl1;
int sr_time64;
int sr_simtimer;
int sr_last;
@@ -68,12 +70,14 @@ typedef struct {
int dsp_tx_scale_iq;
int dsp_tx_interp_rate;
int dsp_tx_mux;
- int dsp_rx_freq;
- int dsp_rx_scale_iq;
- int dsp_rx_decim_rate;
- int dsp_rx_dcoffset_i;
- int dsp_rx_dcoffset_q;
- int dsp_rx_mux;
+ struct{
+ int freq;
+ int scale_iq;
+ int decim_rate;
+ int dcoffset_i;
+ int dcoffset_q;
+ int mux;
+ } dsp_rx[2];
int gpio_base;
int gpio_io;
int gpio_ddr;
@@ -88,15 +92,17 @@ typedef struct {
int atr_inrx_rxside;
int atr_full_txside;
int atr_full_rxside;
- int rx_ctrl_stream_cmd;
- int rx_ctrl_time_secs;
- int rx_ctrl_time_ticks;
- int rx_ctrl_clear_overrun;
- int rx_ctrl_vrt_header;
- int rx_ctrl_vrt_stream_id;
- int rx_ctrl_vrt_trailer;
- int rx_ctrl_nsamps_per_pkt;
- int rx_ctrl_nchannels;
+ struct{
+ int stream_cmd;
+ int time_secs;
+ int time_ticks;
+ int clear_overrun;
+ int vrt_header;
+ int vrt_stream_id;
+ int vrt_trailer;
+ int nsamps_per_pkt;
+ int nchannels;
+ } rx_ctrl[2];
int tx_ctrl_num_chan;
int tx_ctrl_clear_state;
int tx_ctrl_report_sid;