diff options
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 132 |
1 files changed, 66 insertions, 66 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 0f675357b..589fa71a3 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -64,23 +64,23 @@ ///////////////////////////////////////////////// // Misc Control //////////////////////////////////////////////// -#define FR_MISC_CTRL_CLOCK _SR_ADDR(0) -#define FR_MISC_CTRL_SERDES _SR_ADDR(1) -#define FR_MISC_CTRL_ADC _SR_ADDR(2) -#define FR_MISC_CTRL_LEDS _SR_ADDR(3) -#define FR_MISC_CTRL_PHY _SR_ADDR(4) // LSB is reset line to eth phy -#define FR_MISC_CTRL_DBG_MUX _SR_ADDR(5) -#define FR_MISC_CTRL_RAM_PAGE _SR_ADDR(6) // FIXME should go somewhere else... -#define FR_MISC_CTRL_FLUSH_ICACHE _SR_ADDR(7) // Flush the icache -#define FR_MISC_CTRL_LED_SRC _SR_ADDR(8) // HW or SW control for LEDs - -#define FRF_MISC_CTRL_SERDES_ENABLE 8 -#define FRF_MISC_CTRL_SERDES_PRBSEN 4 -#define FRF_MISC_CTRL_SERDES_LOOPEN 2 -#define FRF_MISC_CTRL_SERDES_RXEN 1 - -#define FRF_MISC_CTRL_ADC_ON 0x0F -#define FRF_MISC_CTRL_ADC_OFF 0x00 +#define U2_REG_MISC_CTRL_CLOCK _SR_ADDR(0) +#define U2_REG_MISC_CTRL_SERDES _SR_ADDR(1) +#define U2_REG_MISC_CTRL_ADC _SR_ADDR(2) +#define U2_REG_MISC_CTRL_LEDS _SR_ADDR(3) +#define U2_REG_MISC_CTRL_PHY _SR_ADDR(4) // LSB is reset line to eth phy +#define U2_REG_MISC_CTRL_DBG_MUX _SR_ADDR(5) +#define U2_REG_MISC_CTRL_RAM_PAGE _SR_ADDR(6) // FIXME should go somewhere else... +#define U2_REG_MISC_CTRL_FLUSH_ICACHE _SR_ADDR(7) // Flush the icache +#define U2_REG_MISC_CTRL_LED_SRC _SR_ADDR(8) // HW or SW control for LEDs + +#define U2_FLAG_MISC_CTRL_SERDES_ENABLE 8 +#define U2_FLAG_MISC_CTRL_SERDES_PRBSEN 4 +#define U2_FLAG_MISC_CTRL_SERDES_LOOPEN 2 +#define U2_FLAG_MISC_CTRL_SERDES_RXEN 1 + +#define U2_FLAG_MISC_CTRL_ADC_ON 0x0F +#define U2_FLAG_MISC_CTRL_ADC_OFF 0x00 ///////////////////////////////////////////////// // VITA49 64 bit time (write only) @@ -101,26 +101,26 @@ * * </pre> */ -#define FR_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS -#define FR_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS -#define FR_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above -#define FR_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define U2_REG_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS +#define U2_REG_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS +#define U2_REG_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above +#define U2_REG_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) //pps flags (see above) -#define FRF_TIME64_PPS_NEGEDGE (0 << 0) -#define FRF_TIME64_PPS_POSEDGE (1 << 0) -#define FRF_TIME64_PPS_SMA (0 << 1) -#define FRF_TIME64_PPS_MIMO (1 << 1) +#define U2_FLAG_TIME64_PPS_NEGEDGE (0 << 0) +#define U2_FLAG_TIME64_PPS_POSEDGE (1 << 0) +#define U2_FLAG_TIME64_PPS_SMA (0 << 1) +#define U2_FLAG_TIME64_PPS_MIMO (1 << 1) -#define FRF_TIME64_LATCH_NOW 1 -#define FRF_TIME64_LATCH_NEXT_PPS 0 +#define U2_FLAG_TIME64_LATCH_NOW 1 +#define U2_FLAG_TIME64_LATCH_NEXT_PPS 0 ///////////////////////////////////////////////// // DSP TX Regs //////////////////////////////////////////////// -#define FR_DSP_TX_FREQ _SR_ADDR(SR_TX_DSP + 0) -#define FR_DSP_TX_SCALE_IQ _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q} -#define FR_DSP_TX_INTERP_RATE _SR_ADDR(SR_TX_DSP + 2) +#define U2_REG_DSP_TX_FREQ _SR_ADDR(SR_TX_DSP + 0) +#define U2_REG_DSP_TX_SCALE_IQ _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q} +#define U2_REG_DSP_TX_INTERP_RATE _SR_ADDR(SR_TX_DSP + 2) /*! * \brief output mux configuration. @@ -156,17 +156,17 @@ * The default value is 0x10 * </pre> */ -#define FR_DSP_TX_MUX _SR_ADDR(SR_TX_DSP + 4) +#define U2_REG_DSP_TX_MUX _SR_ADDR(SR_TX_DSP + 4) ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// -#define FR_DSP_RX_FREQ _SR_ADDR(SR_RX_DSP + 0) -#define FR_DSP_RX_SCALE_IQ _SR_ADDR(SR_RX_DSP + 1) // {scale_i,scale_q} -#define FR_DSP_RX_DECIM_RATE _SR_ADDR(SR_RX_DSP + 2) -#define FR_DSP_RX_DCOFFSET_I _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits, +#define U2_REG_DSP_RX_FREQ _SR_ADDR(SR_RX_DSP + 0) +#define U2_REG_DSP_RX_SCALE_IQ _SR_ADDR(SR_RX_DSP + 1) // {scale_i,scale_q} +#define U2_REG_DSP_RX_DECIM_RATE _SR_ADDR(SR_RX_DSP + 2) +#define U2_REG_DSP_RX_DCOFFSET_I _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic -#define FR_DSP_RX_DCOFFSET_Q _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define U2_REG_DSP_RX_DCOFFSET_Q _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits /*! * \brief input mux configuration. * @@ -188,7 +188,7 @@ * The default value is 0x4 * </pre> */ -#define FR_DSP_RX_MUX _SR_ADDR(SR_RX_DSP + 5) // called adc_mux in dsp_core_rx.v +#define U2_REG_DSP_RX_MUX _SR_ADDR(SR_RX_DSP + 5) // called adc_mux in dsp_core_rx.v //////////////////////////////////////////////// // GPIO, Slave 4 @@ -196,52 +196,52 @@ // // These go to the daughterboard i/o pins // -#define FR_GPIO_BASE 0xC800 +#define U2_REG_GPIO_BASE 0xC800 -#define FR_GPIO_IO FR_GPIO_BASE + 0 // 32 bits, gpio io pins (tx high 16 bits, rx low 16 bits) -#define FR_GPIO_DDR FR_GPIO_BASE + 4 // 32 bits, gpio ddr, 1 means output (tx high 16 bits, rx low 16 bits) -#define FR_GPIO_TX_SEL FR_GPIO_BASE + 8 // 16 2-bit fields select which source goes to TX DB -#define FR_GPIO_RX_SEL FR_GPIO_BASE + 12 // 16 2-bit fields select which source goes to RX DB +#define U2_REG_GPIO_IO U2_REG_GPIO_BASE + 0 // 32 bits, gpio io pins (tx high 16 bits, rx low 16 bits) +#define U2_REG_GPIO_DDR U2_REG_GPIO_BASE + 4 // 32 bits, gpio ddr, 1 means output (tx high 16 bits, rx low 16 bits) +#define U2_REG_GPIO_TX_SEL U2_REG_GPIO_BASE + 8 // 16 2-bit fields select which source goes to TX DB +#define U2_REG_GPIO_RX_SEL U2_REG_GPIO_BASE + 12 // 16 2-bit fields select which source goes to RX DB // each 2-bit sel field is layed out this way -#define FRF_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register -#define FRF_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic -#define FRF_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric -#define FRF_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric +#define U2_FLAG_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register +#define U2_FLAG_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define U2_FLAG_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric +#define U2_FLAG_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric /////////////////////////////////////////////////// // ATR Controller, Slave 11 //////////////////////////////////////////////// -#define FR_ATR_BASE 0xE400 +#define U2_REG_ATR_BASE 0xE400 -#define FR_ATR_IDLE_TXSIDE FR_ATR_BASE + 0 -#define FR_ATR_IDLE_RXSIDE FR_ATR_BASE + 2 -#define FR_ATR_INTX_TXSIDE FR_ATR_BASE + 4 -#define FR_ATR_INTX_RXSIDE FR_ATR_BASE + 6 -#define FR_ATR_INRX_TXSIDE FR_ATR_BASE + 8 -#define FR_ATR_INRX_RXSIDE FR_ATR_BASE + 10 -#define FR_ATR_FULL_TXSIDE FR_ATR_BASE + 12 -#define FR_ATR_FULL_RXSIDE FR_ATR_BASE + 14 +#define U2_REG_ATR_IDLE_TXSIDE U2_REG_ATR_BASE + 0 +#define U2_REG_ATR_IDLE_RXSIDE U2_REG_ATR_BASE + 2 +#define U2_REG_ATR_INTX_TXSIDE U2_REG_ATR_BASE + 4 +#define U2_REG_ATR_INTX_RXSIDE U2_REG_ATR_BASE + 6 +#define U2_REG_ATR_INRX_TXSIDE U2_REG_ATR_BASE + 8 +#define U2_REG_ATR_INRX_RXSIDE U2_REG_ATR_BASE + 10 +#define U2_REG_ATR_FULL_TXSIDE U2_REG_ATR_BASE + 12 +#define U2_REG_ATR_FULL_RXSIDE U2_REG_ATR_BASE + 14 /////////////////////////////////////////////////// // VITA RX CTRL regs /////////////////////////////////////////////////// // The following 3 are logically a single command register. // They are clocked into the underlying fifo when time_ticks is written. -#define FR_RX_CTRL_STREAM_CMD _SR_ADDR(SR_RX_CTRL + 0) // {now, chain, num_samples(30) -#define FR_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1) -#define FR_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2) +#define U2_REG_RX_CTRL_STREAM_CMD _SR_ADDR(SR_RX_CTRL + 0) // {now, chain, num_samples(30) +#define U2_REG_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1) +#define U2_REG_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2) -#define FR_RX_CTRL_CLEAR_OVERRUN _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun -#define FR_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter -#define FR_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet. -#define FR_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6) -#define FR_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7) -#define FR_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources +#define U2_REG_RX_CTRL_CLEAR_OVERRUN _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun +#define U2_REG_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter +#define U2_REG_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet. +#define U2_REG_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6) +#define U2_REG_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7) +#define U2_REG_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources //helpful macros for dealing with stream cmd -#define FR_RX_CTRL_MAX_SAMPS_PER_CMD 0x1fffffff -#define FR_RX_CTRL_MAKE_CMD(nsamples, now, chain, reload) \ +#define U2_REG_RX_CTRL_MAX_SAMPS_PER_CMD 0x1fffffff +#define U2_REG_RX_CTRL_MAKE_CMD(nsamples, now, chain, reload) \ ((((now) & 0x1) << 31) | (((chain) & 0x1) << 30) | (((reload) & 0x1) << 29) | ((nsamples) & 0x1fffffff)) #endif /* INCLUDED_USRP2_REGS_HPP */ |