1 files changed, 71 insertions, 34 deletions

diff --git a/host/lib/usrp/usrp2/clock_ctrl.cpp b/host/lib/usrp/usrp2/clock_ctrl.cpp
index b9be037c0..5ed8ec079 100644
--- a/host/lib/usrp/usrp2/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp2/clock_ctrl.cpp
@@ -18,6 +18,7 @@
 #include "clock_ctrl.hpp"
 #include "ad9510_regs.hpp"
 #include "usrp2_regs.hpp" //spi slave constants
+#include "usrp2_clk_regs.hpp"
 #include <uhd/utils/assert.hpp>
 #include <boost/cstdint.hpp>
 
@@ -29,10 +30,12 @@ using namespace uhd;
 class usrp2_clock_ctrl_impl : public usrp2_clock_ctrl{
 public:
     usrp2_clock_ctrl_impl(usrp2_iface::sptr iface){
-        _iface = iface;
+        _iface = iface; //_iface has get_hw_rev(), which lets us know if it's a USRP2+ (>=0x80) or USRP2 (<0x80).
+
+        clk_regs = usrp2_clk_regs_t(_iface->get_hw_rev());
 
         _ad9510_regs.cp_current_setting = ad9510_regs_t::CP_CURRENT_SETTING_3_0MA;
-        this->write_reg(0x09);
+        this->write_reg(clk_regs.pll_3);
 
         // Setup the clock registers to 100MHz:
         //  This was already done by the firmware (or the host couldnt communicate).
@@ -42,20 +45,20 @@ public:
 
         _ad9510_regs.pll_power_down = ad9510_regs_t::PLL_POWER_DOWN_NORMAL;
         _ad9510_regs.prescaler_value = ad9510_regs_t::PRESCALER_VALUE_DIV2;
-        this->write_reg(0x0A);
+        this->write_reg(clk_regs.pll_4);
 
         _ad9510_regs.acounter = 0;
-        this->write_reg(0x04);
+        this->write_reg(clk_regs.acounter);
 
         _ad9510_regs.bcounter_msb = 0;
         _ad9510_regs.bcounter_lsb = 5;
-        this->write_reg(0x05);
-        this->write_reg(0x06);
+        this->write_reg(clk_regs.bcounter_msb);
+        this->write_reg(clk_regs.bcounter_lsb);
 
         _ad9510_regs.ref_counter_msb = 0;
         _ad9510_regs.ref_counter_lsb = 1; // r divider = 1
-        this->write_reg(0x0B);
-        this->write_reg(0x0C);
+        this->write_reg(clk_regs.ref_counter_msb);
+        this->write_reg(clk_regs.ref_counter_lsb);
 
         /* regs will be updated in commands below */
 
@@ -76,11 +79,12 @@ public:
     }
 
     //uses output clock 7 (cmos)
+    //this clock is the same between USRP2 and USRP2+ and so this fn does not get a switch statement
     void enable_rx_dboard_clock(bool enb){
         _ad9510_regs.power_down_lvds_cmos_out7 = enb? 0 : 1;
         _ad9510_regs.lvds_cmos_select_out7 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT7_CMOS;
         _ad9510_regs.output_level_lvds_out7 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT7_1_75MA;
-        this->write_reg(0x43);
+        this->write_reg(clk_regs.output(clk_regs.rx_db));
         this->update_regs();
     }
 
@@ -96,8 +100,8 @@ public:
         _ad9510_regs.divider_low_cycles_out7 = low - 1;
         _ad9510_regs.divider_high_cycles_out7 = high - 1;
         //write the registers
-        this->write_reg(0x56);
-        this->write_reg(0x57);
+        this->write_reg(clk_regs.div_lo(clk_regs.rx_db));
+        this->write_reg(clk_regs.div_hi(clk_regs.rx_db));
         this->update_regs();
     }
 
@@ -107,29 +111,50 @@ public:
         return rates;
     }
 
-    //uses output clock 6 (cmos)
+    //uses output clock 6 (cmos) on USRP2 and output clock 5 (cmos) on USRP2+
     void enable_tx_dboard_clock(bool enb){
-        _ad9510_regs.power_down_lvds_cmos_out6 = enb? 0 : 1;
-        _ad9510_regs.lvds_cmos_select_out6 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT6_CMOS;
-        _ad9510_regs.output_level_lvds_out6 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT6_1_75MA;
-        this->write_reg(0x42);
+        switch(clk_regs.tx_db) {
+        case 5: //USRP2+
+          _ad9510_regs.power_down_lvds_cmos_out5 = enb? 0 : 1;
+          _ad9510_regs.lvds_cmos_select_out5 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT5_CMOS;
+          _ad9510_regs.output_level_lvds_out5 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT5_1_75MA;
+          break;
+        case 6: //USRP2
+          _ad9510_regs.power_down_lvds_cmos_out6 = enb? 0 : 1;
+          _ad9510_regs.lvds_cmos_select_out6 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT6_CMOS;
+          _ad9510_regs.output_level_lvds_out6 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT6_1_75MA;
+          break;
+        }
+
+        this->write_reg(clk_regs.output(clk_regs.tx_db));
         this->update_regs();
     }
 
     void set_rate_tx_dboard_clock(double rate){
         assert_has(get_rates_tx_dboard_clock(), rate, "tx dboard clock rate");
         size_t divider = size_t(rate/get_master_clock_rate());
-        //bypass when the divider ratio is one
-        _ad9510_regs.bypass_divider_out6 = (divider == 1)? 1 : 0;
         //calculate the low and high dividers
         size_t high = divider/2;
         size_t low = divider - high;
-        //set the registers (divider - 1)
-        _ad9510_regs.divider_low_cycles_out6 = low - 1;
-        _ad9510_regs.divider_high_cycles_out6 = high - 1;
+
+        switch(clk_regs.tx_db) {
+        case 5: //USRP2+
+          _ad9510_regs.bypass_divider_out5 = (divider == 1)? 1 : 0;
+          _ad9510_regs.divider_low_cycles_out5 = low - 1;
+          _ad9510_regs.divider_high_cycles_out5 = high - 1;
+          break;
+        case 6: //USRP2
+          //bypass when the divider ratio is one
+          _ad9510_regs.bypass_divider_out6 = (divider == 1)? 1 : 0;
+          //set the registers (divider - 1)
+          _ad9510_regs.divider_low_cycles_out6 = low - 1;
+          _ad9510_regs.divider_high_cycles_out6 = high - 1;
+          break;
+        }
+
         //write the registers
-        this->write_reg(0x54);
-        this->write_reg(0x55);
+        this->write_reg(clk_regs.div_hi(clk_regs.tx_db));
+        this->write_reg(clk_regs.div_lo(clk_regs.tx_db));
         this->update_regs();
     }
 
@@ -147,7 +172,7 @@ public:
             ad9510_regs_t::CHARGE_PUMP_MODE_3STATE ;
         _ad9510_regs.pll_mux_control = ad9510_regs_t::PLL_MUX_CONTROL_DLD_HIGH;
         _ad9510_regs.pfd_polarity = ad9510_regs_t::PFD_POLARITY_POS;
-        this->write_reg(0x08);
+        this->write_reg(clk_regs.pll_2);
         this->update_regs();
     }
 
@@ -170,32 +195,44 @@ private:
      */
     void update_regs(void){
         _ad9510_regs.update_registers = 1;
-        this->write_reg(0x5a);
+        this->write_reg(clk_regs.update);
     }
 
     //uses output clock 3 (pecl)
+    //this is the same between USRP2 and USRP2+ and doesn't get a switch statement
     void enable_dac_clock(bool enb){
         _ad9510_regs.power_down_lvpecl_out3 = (enb)?
             ad9510_regs_t::POWER_DOWN_LVPECL_OUT3_NORMAL :
             ad9510_regs_t::POWER_DOWN_LVPECL_OUT3_SAFE_PD;
         _ad9510_regs.output_level_lvpecl_out3 = ad9510_regs_t::OUTPUT_LEVEL_LVPECL_OUT3_810MV;
         _ad9510_regs.bypass_divider_out3 = 1;
-        this->write_reg(0x3F);
-        this->write_reg(0x4F);
+        this->write_reg(clk_regs.output(clk_regs.dac));
+        this->write_reg(clk_regs.div_hi(clk_regs.dac));
         this->update_regs();
     }
 
-    //uses output clock 4 (lvds)
+    //uses output clock 4 (lvds) on USRP2 and output clock 2 (lvpecl) on USRP2+
     void enable_adc_clock(bool enb){
-        _ad9510_regs.power_down_lvds_cmos_out4 = enb? 0 : 1;
-        _ad9510_regs.lvds_cmos_select_out4 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT4_LVDS;
-        _ad9510_regs.output_level_lvds_out4 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT4_1_75MA;
-        _ad9510_regs.bypass_divider_out4 = 1;
-        this->write_reg(0x40);
-        this->write_reg(0x51);
+        switch(clk_regs.adc) {
+        case 2:
+          _ad9510_regs.power_down_lvpecl_out2 = enb? ad9510_regs_t::POWER_DOWN_LVPECL_OUT2_NORMAL : ad9510_regs_t::POWER_DOWN_LVPECL_OUT2_SAFE_PD;
+          _ad9510_regs.output_level_lvpecl_out2 = ad9510_regs_t::OUTPUT_LEVEL_LVPECL_OUT2_500MV;
+          _ad9510_regs.bypass_divider_out2 = 1;
+          break;
+        case 4:
+          _ad9510_regs.power_down_lvds_cmos_out4 = enb? 0 : 1;
+          _ad9510_regs.lvds_cmos_select_out4 = ad9510_regs_t::LVDS_CMOS_SELECT_OUT4_LVDS;
+          _ad9510_regs.output_level_lvds_out4 = ad9510_regs_t::OUTPUT_LEVEL_LVDS_OUT4_1_75MA;
+          _ad9510_regs.bypass_divider_out4 = 1;
+          break;
+        }
+
+        this->write_reg(clk_regs.output(clk_regs.adc));
+        this->write_reg(clk_regs.div_hi(clk_regs.adc));
         this->update_regs();
     }
 
+    usrp2_clk_regs_t clk_regs;
     usrp2_iface::sptr _iface;
     ad9510_regs_t _ad9510_regs;
 };