9 files changed, 1021 insertions, 56 deletions
diff --git a/host/lib/usrp/cores/CMakeLists.txt b/host/lib/usrp/cores/CMakeLists.txt
index f28ae040f..7a0f6cc93 100644
--- a/host/lib/usrp/cores/CMakeLists.txt
+++ b/host/lib/usrp/cores/CMakeLists.txt
@@ -40,4 +40,6 @@ LIBUHD_APPEND_SOURCES(
     ${CMAKE_CURRENT_SOURCE_DIR}/rx_dsp_core_3000.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/tx_dsp_core_3000.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/radio_ctrl_core_3000.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/gpio_atr_3000.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/dma_fifo_core_3000.cpp
 )
diff --git a/host/lib/usrp/cores/dma_fifo_core_3000.cpp b/host/lib/usrp/cores/dma_fifo_core_3000.cpp
new file mode 100644
index 000000000..1a9d5dd5c
--- /dev/null
+++ b/host/lib/usrp/cores/dma_fifo_core_3000.cpp
@@ -0,0 +1,397 @@
+//
+// Copyright 2015 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "dma_fifo_core_3000.hpp"
+#include <uhd/exception.hpp>
+#include <boost/thread/thread.hpp> //sleep
+#include <uhd/utils/soft_register.hpp>
+#include <uhd/utils/msg.hpp>
+
+using namespace uhd;
+
+#define SR_DRAM_BIST_BASE 16
+
+dma_fifo_core_3000::~dma_fifo_core_3000(void) {
+    /* NOP */
+}
+
+class dma_fifo_core_3000_impl : public dma_fifo_core_3000
+{
+protected:
+    class rb_addr_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(ADDR, /*width*/ 3, /*shift*/ 0);  //[2:0]
+
+        static const boost::uint32_t RB_FIFO_STATUS     = 0;
+        static const boost::uint32_t RB_BIST_STATUS     = 1;
+        static const boost::uint32_t RB_BIST_XFER_CNT   = 2;
+        static const boost::uint32_t RB_BIST_CYC_CNT    = 3;
+
+        rb_addr_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 0)
+        {
+            //Initial values
+            set(ADDR, RB_FIFO_STATUS);
+        }
+    };
+
+    class fifo_ctrl_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(CLEAR_FIFO,           /*width*/  1, /*shift*/  0);  //[0]
+        UHD_DEFINE_SOFT_REG_FIELD(RD_SUPPRESS_EN,       /*width*/  1, /*shift*/  1);  //[1]
+        UHD_DEFINE_SOFT_REG_FIELD(BURST_TIMEOUT,        /*width*/ 12, /*shift*/  4);  //[15:4]
+        UHD_DEFINE_SOFT_REG_FIELD(RD_SUPPRESS_THRESH,   /*width*/ 16, /*shift*/ 16);  //[31:16]
+
+        fifo_ctrl_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 4)
+        {
+            //Initial values
+            set(CLEAR_FIFO, 1);
+            set(RD_SUPPRESS_EN, 0);
+            set(BURST_TIMEOUT, 256);
+            set(RD_SUPPRESS_THRESH, 0);
+        }
+    };
+
+    class base_addr_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(BASE_ADDR, /*width*/ 30, /*shift*/ 0);  //[29:0]
+
+        base_addr_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 8)
+        {
+            //Initial values
+            set(BASE_ADDR, 0x00000000);
+        }
+    };
+
+    class addr_mask_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(ADDR_MASK, /*width*/ 30, /*shift*/ 0);  //[29:0]
+
+        addr_mask_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 12)
+        {
+            //Initial values
+            set(ADDR_MASK, 0xFF000000);
+        }
+    };
+
+    class bist_ctrl_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(GO,               /*width*/ 1, /*shift*/ 0);  //[0]
+        UHD_DEFINE_SOFT_REG_FIELD(CONTINUOUS_MODE,  /*width*/ 1, /*shift*/ 1);  //[1]
+        UHD_DEFINE_SOFT_REG_FIELD(TEST_PATT,        /*width*/ 2, /*shift*/ 4);  //[5:4]
+
+        static const boost::uint32_t TEST_PATT_ZERO_ONE     = 0;
+        static const boost::uint32_t TEST_PATT_CHECKERBOARD = 1;
+        static const boost::uint32_t TEST_PATT_COUNT        = 2;
+        static const boost::uint32_t TEST_PATT_COUNT_INV    = 3;
+
+        bist_ctrl_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 16)
+        {
+            //Initial values
+            set(GO, 0);
+            set(CONTINUOUS_MODE, 0);
+            set(TEST_PATT, TEST_PATT_ZERO_ONE);
+        }
+    };
+
+    class bist_cfg_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(MAX_PKTS,         /*width*/ 18, /*shift*/ 0);  //[17:0]
+        UHD_DEFINE_SOFT_REG_FIELD(MAX_PKT_SIZE,     /*width*/ 13, /*shift*/ 18); //[30:18]
+        UHD_DEFINE_SOFT_REG_FIELD(PKT_SIZE_RAMP,    /*width*/ 1,  /*shift*/ 31); //[31]
+
+        bist_cfg_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 20)
+        {
+            //Initial values
+            set(MAX_PKTS, 0);
+            set(MAX_PKT_SIZE, 0);
+            set(PKT_SIZE_RAMP, 0);
+        }
+    };
+
+    class bist_delay_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(TX_PKT_DELAY,     /*width*/ 16, /*shift*/ 0);  //[15:0]
+        UHD_DEFINE_SOFT_REG_FIELD(RX_SAMP_DELAY,    /*width*/  8, /*shift*/ 16); //[23:16]
+
+        bist_delay_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 24)
+        {
+            //Initial values
+            set(TX_PKT_DELAY, 0);
+            set(RX_SAMP_DELAY, 0);
+        }
+    };
+
+    class bist_sid_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(SID,     /*width*/ 32, /*shift*/ 0);  //[31:0]
+
+        bist_sid_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 28)
+        {
+            //Initial values
+            set(SID, 0);
+        }
+    };
+
+public:
+    class fifo_readback {
+    public:
+        fifo_readback(wb_iface::sptr iface,  const size_t base, const size_t rb_addr) :
+            _iface(iface), _addr_reg(base), _rb_addr(rb_addr)
+        {
+            _addr_reg.initialize(*iface, true);
+        }
+
+        bool is_fifo_instantiated() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_FIFO_STATUS);
+            return _iface->peek32(_rb_addr) & 0x80000000;
+        }
+
+        boost::uint32_t get_occupied_cnt() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_FIFO_STATUS);
+            return _iface->peek32(_rb_addr) & 0x7FFFFFF;
+        }
+
+        boost::uint32_t is_fifo_busy() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_FIFO_STATUS);
+            return _iface->peek32(_rb_addr) & 0x40000000;
+        }
+
+        struct bist_status_t {
+            bool running;
+            bool finished;
+            boost::uint8_t error;
+        };
+
+        bist_status_t get_bist_status() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BIST_STATUS);
+            boost::uint32_t st32 = _iface->peek32(_rb_addr) & 0xF;
+            bist_status_t status;
+            status.running = st32 & 0x1;
+            status.finished = st32 & 0x2;
+            status.error = static_cast<boost::uint8_t>((st32>>2) & 0x3);
+            return status;
+        }
+
+        bool is_ext_bist_supported() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BIST_STATUS);
+            return _iface->peek32(_rb_addr) & 0x80000000;
+        }
+
+        double get_xfer_ratio() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            boost::uint32_t xfer_cnt = 0, cyc_cnt = 0;
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BIST_XFER_CNT);
+            xfer_cnt = _iface->peek32(_rb_addr);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BIST_CYC_CNT);
+            cyc_cnt = _iface->peek32(_rb_addr);
+            return (static_cast<double>(xfer_cnt)/cyc_cnt);
+        }
+
+    private:
+        wb_iface::sptr  _iface;
+        rb_addr_reg_t   _addr_reg;
+        const size_t    _rb_addr;
+        boost::mutex    _mutex;
+    };
+
+public:
+    dma_fifo_core_3000_impl(wb_iface::sptr iface, const size_t base, const size_t readback):
+        _iface(iface), _base(base), _fifo_readback(iface, base, readback),
+        _fifo_ctrl_reg(base), _base_addr_reg(base), _addr_mask_reg(base),
+        _bist_ctrl_reg(base), _bist_cfg_reg(base), _bist_delay_reg(base), _bist_sid_reg(base)
+    {
+        _fifo_ctrl_reg.initialize(*iface, true);
+        _base_addr_reg.initialize(*iface, true);
+        _addr_mask_reg.initialize(*iface, true);
+        _bist_ctrl_reg.initialize(*iface, true);
+        _bist_cfg_reg.initialize(*iface, true);
+        _has_ext_bist = _fifo_readback.is_ext_bist_supported();
+        if (_has_ext_bist) {
+            _bist_delay_reg.initialize(*iface, true);
+            _bist_sid_reg.initialize(*iface, true);
+        }
+        flush();
+    }
+
+    virtual void flush() {
+        //Clear the FIFO and hold it in that state
+        _fifo_ctrl_reg.write(fifo_ctrl_reg_t::CLEAR_FIFO, 1);
+        //Re-arm the FIFO
+        _wait_for_fifo_empty();
+        _fifo_ctrl_reg.write(fifo_ctrl_reg_t::CLEAR_FIFO, 0);
+    }
+
+    virtual void resize(const boost::uint32_t base_addr, const boost::uint32_t size) {
+        //Validate parameters
+        if (size < 8192) throw uhd::runtime_error("DMA FIFO must be larger than 8KiB");
+        boost::uint32_t size_mask = size - 1;
+        if (size & size_mask) throw uhd::runtime_error("DMA FIFO size must be a power of 2");
+
+        //Clear the FIFO and hold it in that state
+        _fifo_ctrl_reg.write(fifo_ctrl_reg_t::CLEAR_FIFO, 1);
+        //Write base address and mask
+        _base_addr_reg.write(base_addr_reg_t::BASE_ADDR, base_addr);
+        _addr_mask_reg.write(addr_mask_reg_t::ADDR_MASK, ~size_mask);
+
+        //Re-arm the FIFO
+        flush();
+    }
+
+    virtual boost::uint32_t get_bytes_occupied() {
+        return _fifo_readback.get_occupied_cnt() * 8;
+    }
+
+    virtual bool ext_bist_supported() {
+        return _fifo_readback.is_ext_bist_supported();
+    }
+
+    virtual boost::uint8_t run_bist(bool finite = true, boost::uint32_t timeout_ms = 500) {
+        return run_ext_bist(finite, 0, 0, 0, timeout_ms);
+    }
+
+    virtual boost::uint8_t run_ext_bist(
+        bool finite,
+        boost::uint32_t rx_samp_delay,
+        boost::uint32_t tx_pkt_delay,
+        boost::uint32_t sid,
+        boost::uint32_t timeout_ms = 500
+    ) {
+        boost::lock_guard<boost::mutex> lock(_mutex);
+
+        _wait_for_bist_done(timeout_ms, true);          //Stop previous BIST and wait (if running)
+        _bist_ctrl_reg.write(bist_ctrl_reg_t::GO, 0);   //Reset
+
+        _bist_cfg_reg.set(bist_cfg_reg_t::MAX_PKTS, (2^18)-1);
+        _bist_cfg_reg.set(bist_cfg_reg_t::MAX_PKT_SIZE, 8000);
+        _bist_cfg_reg.set(bist_cfg_reg_t::PKT_SIZE_RAMP, 0);
+        _bist_cfg_reg.flush();
+
+        if (_has_ext_bist) {
+            _bist_delay_reg.set(bist_delay_reg_t::RX_SAMP_DELAY, rx_samp_delay);
+            _bist_delay_reg.set(bist_delay_reg_t::TX_PKT_DELAY, tx_pkt_delay);
+            _bist_delay_reg.flush();
+
+            _bist_sid_reg.write(bist_sid_reg_t::SID, sid);
+        } else {
+            if (rx_samp_delay != 0 || tx_pkt_delay != 0 || sid != 0) {
+                throw uhd::not_implemented_error(
+                    "dma_fifo_core_3000: Runtime delay and SID support only available on FPGA images with extended BIST enabled");
+            }
+        }
+
+        _bist_ctrl_reg.set(bist_ctrl_reg_t::TEST_PATT, bist_ctrl_reg_t::TEST_PATT_COUNT);
+        _bist_ctrl_reg.set(bist_ctrl_reg_t::CONTINUOUS_MODE, finite ? 0 : 1);
+        _bist_ctrl_reg.write(bist_ctrl_reg_t::GO, 1);
+
+        if (!finite) {
+            boost::this_thread::sleep(boost::posix_time::milliseconds(timeout_ms));
+        }
+
+        _wait_for_bist_done(timeout_ms, !finite);
+        if (!_fifo_readback.get_bist_status().finished) {
+            throw uhd::runtime_error("dma_fifo_core_3000: DRAM BIST state machine is in a bad state.");
+        }
+
+        return _fifo_readback.get_bist_status().error;
+    }
+
+    virtual double get_bist_throughput(double fifo_clock_rate) {
+        if (_has_ext_bist) {
+            _wait_for_bist_done(1000);
+            static const double BYTES_PER_CYC = 8;
+            return _fifo_readback.get_xfer_ratio() * fifo_clock_rate * BYTES_PER_CYC;
+        } else {
+            throw uhd::not_implemented_error(
+                "dma_fifo_core_3000: Throughput counter only available on FPGA images with extended BIST enabled");
+        }
+    }
+
+private:
+    void _wait_for_fifo_empty()
+    {
+        boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time();
+        boost::posix_time::time_duration elapsed;
+
+        while (_fifo_readback.is_fifo_busy()) {
+            boost::this_thread::sleep(boost::posix_time::microsec(1000));
+            elapsed = boost::posix_time::microsec_clock::local_time() - start_time;
+            if (elapsed.total_milliseconds() > 100) break;
+        }
+    }
+
+    void _wait_for_bist_done(boost::uint32_t timeout_ms, bool force_stop = false)
+    {
+        boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time();
+        boost::posix_time::time_duration elapsed;
+
+        while (_fifo_readback.get_bist_status().running) {
+            if (force_stop) {
+                _bist_ctrl_reg.write(bist_ctrl_reg_t::GO, 0);
+                force_stop = false;
+            }
+            boost::this_thread::sleep(boost::posix_time::microsec(1000));
+            elapsed = boost::posix_time::microsec_clock::local_time() - start_time;
+            if (elapsed.total_milliseconds() > timeout_ms) break;
+        }
+    }
+
+private:
+    wb_iface::sptr  _iface;
+    const size_t    _base;
+    boost::mutex    _mutex;
+    bool            _has_ext_bist;
+
+    fifo_readback       _fifo_readback;
+    fifo_ctrl_reg_t     _fifo_ctrl_reg;
+    base_addr_reg_t     _base_addr_reg;
+    addr_mask_reg_t     _addr_mask_reg;
+    bist_ctrl_reg_t     _bist_ctrl_reg;
+    bist_cfg_reg_t      _bist_cfg_reg;
+    bist_delay_reg_t    _bist_delay_reg;
+    bist_sid_reg_t      _bist_sid_reg;
+};
+
+//
+// Static make function
+//
+dma_fifo_core_3000::sptr dma_fifo_core_3000::make(wb_iface::sptr iface, const size_t set_base, const size_t rb_addr)
+{
+    if (check(iface, set_base, rb_addr)) {
+        return sptr(new dma_fifo_core_3000_impl(iface, set_base, rb_addr));
+    } else {
+        throw uhd::runtime_error("");
+    }
+}
+
+bool dma_fifo_core_3000::check(wb_iface::sptr iface, const size_t set_base, const size_t rb_addr)
+{
+    dma_fifo_core_3000_impl::fifo_readback fifo_rb(iface, set_base, rb_addr);
+    return fifo_rb.is_fifo_instantiated();
+}
diff --git a/host/lib/usrp/cores/dma_fifo_core_3000.hpp b/host/lib/usrp/cores/dma_fifo_core_3000.hpp
new file mode 100644
index 000000000..41430e5c3
--- /dev/null
+++ b/host/lib/usrp/cores/dma_fifo_core_3000.hpp
@@ -0,0 +1,86 @@
+//
+// Copyright 2015 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_LIBUHD_USRP_DMA_FIFO_CORE_3000_HPP
+#define INCLUDED_LIBUHD_USRP_DMA_FIFO_CORE_3000_HPP
+
+#include <uhd/config.hpp>
+#include <boost/shared_ptr.hpp>
+#include <boost/noncopyable.hpp>
+#include <uhd/types/wb_iface.hpp>
+
+
+class dma_fifo_core_3000 : boost::noncopyable
+{
+public:
+    typedef boost::shared_ptr<dma_fifo_core_3000> sptr;
+    virtual ~dma_fifo_core_3000(void) = 0;
+
+    /*!
+     * Create a DMA FIFO controller using the given bus, settings and readback base
+     * Throws uhd::runtime_error if a DMA FIFO is not instantiated in the FPGA
+     */
+    static sptr make(uhd::wb_iface::sptr iface, const size_t set_base, const size_t rb_addr);
+
+    /*!
+     * Check if a DMA FIFO is instantiated in the FPGA
+     */
+    static bool check(uhd::wb_iface::sptr iface, const size_t set_base, const size_t rb_addr);
+
+    /*!
+     * Flush the DMA FIFO. Will clear all contents.
+     */
+    virtual void flush() = 0;
+
+    /*!
+     * Resize and rebase the DMA FIFO. Will clear all contents.
+     */
+    virtual void resize(const boost::uint32_t base_addr, const boost::uint32_t size) = 0;
+
+    /*!
+     * Get the (approx) number of bytes currently in the DMA FIFO
+     */
+    virtual boost::uint32_t get_bytes_occupied() = 0;
+
+    /*!
+     * Run the built-in-self-test routine for the DMA FIFO
+     */
+    virtual boost::uint8_t run_bist(bool finite = true, boost::uint32_t timeout_ms = 500) = 0;
+
+    /*!
+     * Is extended BIST supported
+     */
+    virtual bool ext_bist_supported() = 0;
+
+    /*!
+     * Run the built-in-self-test routine for the DMA FIFO (extended BIST only)
+     */
+    virtual boost::uint8_t run_ext_bist(
+        bool finite,
+        boost::uint32_t rx_samp_delay,
+        boost::uint32_t tx_pkt_delay,
+        boost::uint32_t sid,
+        boost::uint32_t timeout_ms = 500) = 0;
+
+    /*!
+     * Get the throughput measured from the last invocation of the BIST (extended BIST only)
+     */
+    virtual double get_bist_throughput(double fifo_clock_rate) = 0;
+
+};
+
+#endif /* INCLUDED_LIBUHD_USRP_DMA_FIFO_CORE_3000_HPP */
diff --git a/host/lib/usrp/cores/gpio_atr_3000.cpp b/host/lib/usrp/cores/gpio_atr_3000.cpp
new file mode 100644
index 000000000..3e0aa1f03
--- /dev/null
+++ b/host/lib/usrp/cores/gpio_atr_3000.cpp
@@ -0,0 +1,297 @@
+//
+// Copyright 2011,2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "gpio_atr_3000.hpp"
+#include <uhd/types/dict.hpp>
+#include <uhd/utils/soft_register.hpp>
+
+using namespace uhd;
+using namespace usrp;
+
+//-------------------------------------------------------------
+// gpio_atr_3000
+//-------------------------------------------------------------
+
+#define REG_ATR_IDLE_OFFSET     (base + 0)
+#define REG_ATR_RX_OFFSET       (base + 4)
+#define REG_ATR_TX_OFFSET       (base + 8)
+#define REG_ATR_FDX_OFFSET      (base + 12)
+#define REG_DDR_OFFSET          (base + 16)
+#define REG_ATR_DISABLE_OFFSET  (base + 20)
+
+namespace uhd { namespace usrp { namespace gpio_atr {
+
+class gpio_atr_3000_impl : public gpio_atr_3000{
+public:
+    gpio_atr_3000_impl(
+        wb_iface::sptr iface,
+        const wb_iface::wb_addr_type base,
+        const wb_iface::wb_addr_type rb_addr = READBACK_DISABLED
+    ):
+        _iface(iface), _rb_addr(rb_addr),
+        _atr_idle_reg(REG_ATR_IDLE_OFFSET, _atr_disable_reg),
+        _atr_rx_reg(REG_ATR_RX_OFFSET),
+        _atr_tx_reg(REG_ATR_TX_OFFSET),
+        _atr_fdx_reg(REG_ATR_FDX_OFFSET),
+        _ddr_reg(REG_DDR_OFFSET),
+        _atr_disable_reg(REG_ATR_DISABLE_OFFSET)
+    {
+        _atr_idle_reg.initialize(*_iface, true);
+        _atr_rx_reg.initialize(*_iface, true);
+        _atr_tx_reg.initialize(*_iface, true);
+        _atr_fdx_reg.initialize(*_iface, true);
+        _ddr_reg.initialize(*_iface, true);
+        _atr_disable_reg.initialize(*_iface, true);
+    }
+
+    virtual void set_atr_mode(const gpio_atr_mode_t mode, const boost::uint32_t mask)
+    {
+        //Each bit in the "ATR Disable" register determines whether the respective bit in the GPIO
+        //output bus is driven by the ATR engine or a static register.
+        //For each bit position, a 1 means that the bit is static and 0 means that the bit
+        //is driven by the ATR state machine.
+        //This setting will only get applied to all bits in the "mask" that are 1. All other
+        //bits will retain their old value.
+        _atr_disable_reg.set_with_mask((mode==MODE_ATR) ? ~MASK_SET_ALL : MASK_SET_ALL, mask);
+        _atr_disable_reg.flush();
+    }
+
+    virtual void set_gpio_ddr(const gpio_ddr_t dir, const boost::uint32_t mask)
+    {
+        //Each bit in the "DDR" register determines whether the respective bit in the GPIO
+        //bus is an input or an output.
+        //For each bit position, a 1 means that the bit is an output and 0 means that the bit
+        //is an input.
+        //This setting will only get applied to all bits in the "mask" that are 1. All other
+        //bits will retain their old value.
+        _ddr_reg.set_with_mask((dir==DDR_INPUT) ? ~MASK_SET_ALL : MASK_SET_ALL, mask);
+        _ddr_reg.flush();
+    }
+
+    virtual void set_atr_reg(const gpio_atr_reg_t atr, const boost::uint32_t value, const boost::uint32_t mask = MASK_SET_ALL)
+    {
+        //Set the value of the specified ATR register. For bits with ATR Disable set to 1,
+        //the IDLE register will hold the output state
+        //This setting will only get applied to all bits in the "mask" that are 1. All other
+        //bits will retain their old value.
+        masked_reg_t* reg = NULL;
+        switch (atr) {
+            case ATR_REG_IDLE:          reg = &_atr_idle_reg; break;
+            case ATR_REG_RX_ONLY:       reg = &_atr_rx_reg;   break;
+            case ATR_REG_TX_ONLY:       reg = &_atr_tx_reg;   break;
+            case ATR_REG_FULL_DUPLEX:   reg = &_atr_fdx_reg;  break;
+            default:                    reg = &_atr_idle_reg; break;
+        }
+        //For protection we only write to bits that have the mode ATR by masking the user
+        //specified "mask" with ~atr_disable.
+        reg->set_with_mask(value, mask);
+        reg->flush();
+    }
+
+    virtual void set_gpio_out(const boost::uint32_t value, const boost::uint32_t mask = MASK_SET_ALL) {
+        //Set the value of the specified GPIO output register.
+        //This setting will only get applied to all bits in the "mask" that are 1. All other
+        //bits will retain their old value.
+
+        //For protection we only write to bits that have the mode GPIO by masking the user
+        //specified "mask" with atr_disable.
+        _atr_idle_reg.set_gpio_out_with_mask(value, mask);
+        _atr_idle_reg.flush();
+    }
+
+    virtual boost::uint32_t read_gpio()
+    {
+        //Read the state of the GPIO pins
+        //If a pin is configured as an input, reads the actual value of the pin
+        //If a pin is configured as an output, reads the last value written to the pin
+        if (_rb_addr != READBACK_DISABLED) {
+            return _iface->peek32(_rb_addr);
+        } else {
+            throw uhd::runtime_error("read_gpio not supported for write-only interface.");
+        }
+    }
+
+    inline virtual void set_gpio_attr(const gpio_attr_t attr, const boost::uint32_t value)
+    {
+        //An attribute based API to configure all settings for the GPIO bus in one function
+        //call. This API does not have a mask so it configures all bits at the same time.
+        switch (attr)
+        {
+        case GPIO_CTRL:
+            set_atr_mode(MODE_ATR, value);   //Configure mode=ATR for all bits that are set
+            set_atr_mode(MODE_GPIO, ~value); //Configure mode=GPIO for all bits that are unset
+            break;
+        case GPIO_DDR:
+            set_gpio_ddr(DDR_OUTPUT, value); //Configure as output for all bits that are set
+            set_gpio_ddr(DDR_INPUT, ~value); //Configure as input for all bits that are unset
+            break;
+        case GPIO_OUT:
+            //Only set bits that are driven statically
+            set_gpio_out(value);
+            break;
+        case GPIO_ATR_0X:
+            //Only set bits that are driven by the ATR engine
+            set_atr_reg(ATR_REG_IDLE, value);
+            break;
+        case GPIO_ATR_RX:
+            //Only set bits that are driven by the ATR engine
+            set_atr_reg(ATR_REG_RX_ONLY, value);
+            break;
+        case GPIO_ATR_TX:
+            //Only set bits that are driven by the ATR engine
+            set_atr_reg(ATR_REG_TX_ONLY, value);
+            break;
+        case GPIO_ATR_XX:
+            //Only set bits that are driven by the ATR engine
+            set_atr_reg(ATR_REG_FULL_DUPLEX, value);
+            break;
+        default:
+            UHD_THROW_INVALID_CODE_PATH();
+        }
+    }
+
+private:
+    //Special RB addr value to indicate no readback
+    //This value is invalid as a real address because it is not a multiple of 4
+    static const wb_iface::wb_addr_type READBACK_DISABLED = 0xFFFFFFFF;
+
+    class masked_reg_t : public uhd::soft_reg32_wo_t {
+    public:
+        masked_reg_t(const wb_iface::wb_addr_type offset): uhd::soft_reg32_wo_t(offset) {
+            set(REGISTER, 0);
+        }
+
+        virtual void set_with_mask(const boost::uint32_t value, const boost::uint32_t mask) {
+            set(REGISTER, (value&mask)|(get(REGISTER)&(~mask)));
+        }
+
+        virtual void flush() {
+            uhd::soft_reg32_wo_t::flush();
+        }
+    };
+
+    class atr_idle_reg_t : public masked_reg_t {
+    public:
+        atr_idle_reg_t(const wb_iface::wb_addr_type offset, masked_reg_t& atr_disable_reg):
+            masked_reg_t(offset),
+            _atr_idle_cache(0), _gpio_out_cache(0),
+            _atr_disable_reg(atr_disable_reg)
+        { }
+
+        virtual void set_with_mask(const boost::uint32_t value, const boost::uint32_t mask) {
+            _atr_idle_cache = (value&mask)|(_atr_idle_cache&(~mask));
+        }
+
+        void set_gpio_out_with_mask(const boost::uint32_t value, const boost::uint32_t mask) {
+            _gpio_out_cache = (value&mask)|(_gpio_out_cache&(~mask));
+        }
+
+        virtual void flush() {
+            set(REGISTER,
+                (_atr_idle_cache & (~_atr_disable_reg.get(REGISTER))) |
+                (_gpio_out_cache & _atr_disable_reg.get(REGISTER))
+            );
+            masked_reg_t::flush();
+        }
+
+    private:
+        boost::uint32_t _atr_idle_cache;
+        boost::uint32_t _gpio_out_cache;
+        masked_reg_t&   _atr_disable_reg;
+    };
+
+    wb_iface::sptr          _iface;
+    wb_iface::wb_addr_type  _rb_addr;
+    atr_idle_reg_t          _atr_idle_reg;
+    masked_reg_t            _atr_rx_reg;
+    masked_reg_t            _atr_tx_reg;
+    masked_reg_t            _atr_fdx_reg;
+    masked_reg_t            _ddr_reg;
+    masked_reg_t            _atr_disable_reg;
+};
+
+gpio_atr_3000::sptr gpio_atr_3000::make(
+    wb_iface::sptr iface, const wb_iface::wb_addr_type base, const wb_iface::wb_addr_type rb_addr
+) {
+    return sptr(new gpio_atr_3000_impl(iface, base, rb_addr));
+}
+
+gpio_atr_3000::sptr gpio_atr_3000::make_write_only(
+    wb_iface::sptr iface, const wb_iface::wb_addr_type base
+) {
+    gpio_atr_3000::sptr gpio_iface(new gpio_atr_3000_impl(iface, base));
+    gpio_iface->set_gpio_ddr(DDR_OUTPUT, MASK_SET_ALL);
+    return gpio_iface;
+}
+
+//-------------------------------------------------------------
+// db_gpio_atr_3000
+//-------------------------------------------------------------
+
+class db_gpio_atr_3000_impl : public gpio_atr_3000_impl, public db_gpio_atr_3000 {
+public:
+    db_gpio_atr_3000_impl(wb_iface::sptr iface, const wb_iface::wb_addr_type base, const wb_iface::wb_addr_type rb_addr):
+        gpio_atr_3000_impl(iface, base, rb_addr) { /* NOP */ }
+
+    inline void set_pin_ctrl(const db_unit_t unit, const boost::uint16_t value)
+    {
+        gpio_atr_3000_impl::set_atr_mode(MODE_ATR,  compute_mask(unit, value));
+        gpio_atr_3000_impl::set_atr_mode(MODE_GPIO, compute_mask(unit, ~value));
+    }
+
+    inline void set_gpio_ddr(const db_unit_t unit, const boost::uint16_t value)
+    {
+        gpio_atr_3000_impl::set_gpio_ddr(DDR_OUTPUT, compute_mask(unit, value));
+        gpio_atr_3000_impl::set_gpio_ddr(DDR_INPUT,  compute_mask(unit, ~value));
+    }
+
+    inline void set_atr_reg(const db_unit_t unit, const gpio_atr_reg_t atr, const boost::uint16_t value)
+    {
+        gpio_atr_3000_impl::set_atr_reg(atr,
+            static_cast<boost::uint32_t>(value) << compute_shift(unit),
+            compute_mask(unit, 0xFFFF));
+    }
+
+    inline void set_gpio_out(const db_unit_t unit, const boost::uint16_t value)
+    {
+        gpio_atr_3000_impl::set_gpio_out(
+            static_cast<boost::uint32_t>(value) << compute_shift(unit),
+            compute_mask(unit, 0xFFFF));
+    }
+
+    inline boost::uint16_t read_gpio(const db_unit_t unit)
+    {
+        return boost::uint16_t(gpio_atr_3000_impl::read_gpio() >> compute_shift(unit));
+    }
+
+private:
+    inline boost::uint32_t compute_shift(const db_unit_t unit) {
+        return (unit == dboard_iface::UNIT_RX) ? 0 : 16;
+    }
+
+    inline boost::uint32_t compute_mask(const db_unit_t unit, const boost::uint16_t mask) {
+        return static_cast<boost::uint32_t>(mask) << (compute_shift(unit));
+    }
+};
+
+db_gpio_atr_3000::sptr db_gpio_atr_3000::make(
+    wb_iface::sptr iface, const wb_iface::wb_addr_type base, const wb_iface::wb_addr_type rb_addr
+) {
+    return sptr(new db_gpio_atr_3000_impl(iface, base, rb_addr));
+}
+
+}}}
diff --git a/host/lib/usrp/cores/gpio_atr_3000.hpp b/host/lib/usrp/cores/gpio_atr_3000.hpp
new file mode 100644
index 000000000..b30cd3b85
--- /dev/null
+++ b/host/lib/usrp/cores/gpio_atr_3000.hpp
@@ -0,0 +1,175 @@
+//
+// Copyright 2011,2014,2015 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_LIBUHD_USRP_GPIO_CORE_3000_HPP
+#define INCLUDED_LIBUHD_USRP_GPIO_CORE_3000_HPP
+
+#include <uhd/config.hpp>
+#include <uhd/usrp/dboard_iface.hpp>
+#include <uhd/usrp/gpio_defs.hpp>
+#include <boost/shared_ptr.hpp>
+#include <uhd/types/wb_iface.hpp>
+
+namespace uhd { namespace usrp { namespace gpio_atr {
+
+class gpio_atr_3000 : boost::noncopyable {
+public:
+    typedef boost::shared_ptr<gpio_atr_3000> sptr;
+
+    static const boost::uint32_t MASK_SET_ALL = 0xFFFFFFFF;
+
+    virtual ~gpio_atr_3000(void) {};
+
+    /*!
+     * Create a read-write GPIO ATR interface object
+     *
+     * \param iface register iface to GPIO ATR registers
+     * \param base base settings offset for GPIO ATR registers
+     * \param base readback offset for GPIO ATR registers
+     */
+    static sptr make(
+        uhd::wb_iface::sptr iface,
+        const uhd::wb_iface::wb_addr_type base,
+        const uhd::wb_iface::wb_addr_type rb_addr);
+
+    /*!
+     * Create a write-only GPIO ATR interface object
+     *
+     * \param iface register iface to GPIO ATR registers
+     * \param base base settings offset for GPIO ATR registers
+     */
+    static sptr make_write_only(
+        uhd::wb_iface::sptr iface, const uhd::wb_iface::wb_addr_type base);
+
+    /*!
+     * Select the ATR mode for all bits in the mask
+     *
+     * \param mode the mode to apply {ATR = outputs driven by ATR state machine, GPIO = outputs static}
+     * \param mask apply the mode to all non-zero bits in the mask
+     */
+    virtual void set_atr_mode(const gpio_atr_mode_t mode, const boost::uint32_t mask) = 0;
+
+    /*!
+     * Select the data direction for all bits in the mask
+     *
+     * \param dir the direction {OUTPUT, INPUT}
+     * \param mask apply the mode to all non-zero bits in the mask
+     */
+    virtual void set_gpio_ddr(const gpio_ddr_t dir, const boost::uint32_t mask) = 0;
+
+    /*!
+     * Write the specified (masked) value to the ATR register
+     *
+     * \param atr the type of ATR register to write to {IDLE, RX, TX, FDX}
+     * \param value the value to write
+     * \param mask only writes to the bits where mask is non-zero
+     */
+    virtual void set_atr_reg(const gpio_atr_reg_t atr, const boost::uint32_t value, const boost::uint32_t mask = MASK_SET_ALL) = 0;
+
+    /*!
+     * Write to a static GPIO output
+     *
+     * \param value the value to write
+     * \param mask only writes to the bits where mask is non-zero
+     */
+    virtual void set_gpio_out(const boost::uint32_t value, const boost::uint32_t mask = MASK_SET_ALL) = 0;
+
+    /*!
+     * Read the state of the GPIO pins
+     * If a pin is configured as an input, reads the actual value of the pin
+     * If a pin is configured as an output, reads the last value written to the pin
+     *
+     * \return the value read back
+     */
+    virtual boost::uint32_t read_gpio() = 0;
+
+    /*!
+     * Set a GPIO attribute
+     *
+     * \param attr the attribute to set
+     * \param value the value to write to the attribute
+     */
+    virtual void set_gpio_attr(const gpio_attr_t attr, const boost::uint32_t value) = 0;
+};
+
+class db_gpio_atr_3000 {
+public:
+    typedef boost::shared_ptr<db_gpio_atr_3000> sptr;
+
+    typedef uhd::usrp::dboard_iface::unit_t db_unit_t;
+
+    virtual ~db_gpio_atr_3000(void) {};
+
+    /*!
+     * Create a read-write GPIO ATR interface object for a daughterboard connector
+     *
+     * \param iface register iface to GPIO ATR registers
+     * \param base base settings offset for GPIO ATR registers
+     * \param base readback offset for GPIO ATR registers
+     */
+    static sptr make(
+        uhd::wb_iface::sptr iface,
+        const uhd::wb_iface::wb_addr_type base,
+        const uhd::wb_iface::wb_addr_type rb_addr);
+
+    /*!
+     * Configure the GPIO mode for all pins in the daughterboard connector
+     *
+     * \param unit the side of the daughterboard interface to configure (TX or RX)
+     * \param value if value[i] is 1, the i'th bit is in ATR mode otherwise it is in GPIO mode
+     */
+    virtual void set_pin_ctrl(const db_unit_t unit, const boost::uint16_t value) = 0;
+
+    /*!
+     * Configure the direction for all pins in the daughterboard connector
+     *
+     * \param unit the side of the daughterboard interface to configure (TX or RX)
+     * \param value if value[i] is 1, the i'th bit is an output otherwise it is an input
+     */
+    virtual void set_gpio_ddr(const db_unit_t unit, const boost::uint16_t value) = 0;
+
+    /*!
+     * Write the specified value to the ATR register (all bits)
+     *
+     * \param atr the type of ATR register to write to {IDLE, RX, TX, FDX}
+     * \param unit the side of the daughterboard interface to configure (TX or RX)
+     * \param value the value to write
+     */
+    virtual void set_atr_reg(const db_unit_t unit, const gpio_atr_reg_t atr, const boost::uint16_t value) = 0;
+
+    /*!
+     * Write the specified value to the GPIO register (all bits)
+     *
+     * \param atr the type of ATR register to write to {IDLE, RX, TX, FDX}
+     * \param value the value to write
+     */
+    virtual void set_gpio_out(const db_unit_t unit, const boost::uint16_t value) = 0;
+
+    /*!
+     * Read the state of the GPIO pins
+     * If a pin is configured as an input, reads the actual value of the pin
+     * If a pin is configured as an output, reads the last value written to the pin
+     *
+     * \param unit the side of the daughterboard interface to configure (TX or RX)
+     * \return the value read back
+     */
+    virtual boost::uint16_t read_gpio(const db_unit_t unit) = 0;
+};
+
+}}} //namespaces
+
+#endif /* INCLUDED_LIBUHD_USRP_GPIO_CORE_3000_HPP */
diff --git a/host/lib/usrp/cores/gpio_core_200.cpp b/host/lib/usrp/cores/gpio_core_200.cpp
index 4f1c25a0b..05a689845 100644
--- a/host/lib/usrp/cores/gpio_core_200.cpp
+++ b/host/lib/usrp/cores/gpio_core_200.cpp
@@ -77,10 +77,10 @@ private:
     }
 
     void update(void){
-        this->update(dboard_iface::ATR_REG_IDLE, REG_GPIO_IDLE);
-        this->update(dboard_iface::ATR_REG_TX_ONLY, REG_GPIO_TX_ONLY);
-        this->update(dboard_iface::ATR_REG_RX_ONLY, REG_GPIO_RX_ONLY);
-        this->update(dboard_iface::ATR_REG_FULL_DUPLEX, REG_GPIO_BOTH);
+        this->update(gpio_atr::ATR_REG_IDLE, REG_GPIO_IDLE);
+        this->update(gpio_atr::ATR_REG_TX_ONLY, REG_GPIO_TX_ONLY);
+        this->update(gpio_atr::ATR_REG_RX_ONLY, REG_GPIO_RX_ONLY);
+        this->update(gpio_atr::ATR_REG_FULL_DUPLEX, REG_GPIO_BOTH);
     }
 
     void update(const atr_reg_t atr, const size_t addr){
@@ -122,17 +122,17 @@ public:
     }
 
     void set_atr_reg(const atr_reg_t atr, const boost::uint32_t value){
-        if (atr == dboard_iface::ATR_REG_IDLE)        _iface->poke32(REG_GPIO_IDLE, value);
-        if (atr == dboard_iface::ATR_REG_TX_ONLY)     _iface->poke32(REG_GPIO_TX_ONLY, value);
-        if (atr == dboard_iface::ATR_REG_RX_ONLY)     _iface->poke32(REG_GPIO_RX_ONLY, value);
-        if (atr == dboard_iface::ATR_REG_FULL_DUPLEX) _iface->poke32(REG_GPIO_BOTH, value);
+        if (atr == gpio_atr::ATR_REG_IDLE)        _iface->poke32(REG_GPIO_IDLE, value);
+        if (atr == gpio_atr::ATR_REG_TX_ONLY)     _iface->poke32(REG_GPIO_TX_ONLY, value);
+        if (atr == gpio_atr::ATR_REG_RX_ONLY)     _iface->poke32(REG_GPIO_RX_ONLY, value);
+        if (atr == gpio_atr::ATR_REG_FULL_DUPLEX) _iface->poke32(REG_GPIO_BOTH, value);
     }
 
     void set_all_regs(const boost::uint32_t value){
-        this->set_atr_reg(dboard_iface::ATR_REG_IDLE,        value);
-        this->set_atr_reg(dboard_iface::ATR_REG_TX_ONLY,     value);
-        this->set_atr_reg(dboard_iface::ATR_REG_RX_ONLY,     value);
-        this->set_atr_reg(dboard_iface::ATR_REG_FULL_DUPLEX, value);
+        this->set_atr_reg(gpio_atr::ATR_REG_IDLE,        value);
+        this->set_atr_reg(gpio_atr::ATR_REG_TX_ONLY,     value);
+        this->set_atr_reg(gpio_atr::ATR_REG_RX_ONLY,     value);
+        this->set_atr_reg(gpio_atr::ATR_REG_FULL_DUPLEX, value);
     }
 
 private:
diff --git a/host/lib/usrp/cores/gpio_core_200.hpp b/host/lib/usrp/cores/gpio_core_200.hpp
index e22834fd9..c60507792 100644
--- a/host/lib/usrp/cores/gpio_core_200.hpp
+++ b/host/lib/usrp/cores/gpio_core_200.hpp
@@ -20,6 +20,7 @@
 
 #include <uhd/config.hpp>
 #include <uhd/usrp/dboard_iface.hpp>
+#include <uhd/usrp/gpio_defs.hpp>
 #include <boost/assign.hpp>
 #include <boost/cstdint.hpp>
 #include <boost/utility.hpp>
@@ -27,28 +28,6 @@
 #include <uhd/types/wb_iface.hpp>
 #include <map>
 
-typedef enum {
-    GPIO_CTRL,
-    GPIO_DDR,
-    GPIO_OUT,
-    GPIO_ATR_0X,
-    GPIO_ATR_RX,
-    GPIO_ATR_TX,
-    GPIO_ATR_XX
-} gpio_attr_t;
-
-typedef std::map<gpio_attr_t,std::string> gpio_attr_map_t;
-static const gpio_attr_map_t gpio_attr_map =
-    boost::assign::map_list_of
-        (GPIO_CTRL,   "CTRL")
-        (GPIO_DDR,    "DDR")
-        (GPIO_OUT,    "OUT")
-        (GPIO_ATR_0X, "ATR_0X")
-        (GPIO_ATR_RX, "ATR_RX")
-        (GPIO_ATR_TX, "ATR_TX")
-        (GPIO_ATR_XX, "ATR_XX")
-;
-
 class gpio_core_200 : boost::noncopyable{
 public:
     typedef boost::shared_ptr<gpio_core_200> sptr;
diff --git a/host/lib/usrp/cores/tx_vita_core_3000.cpp b/host/lib/usrp/cores/tx_vita_core_3000.cpp
index 71a2b7e21..c76b384d9 100644
--- a/host/lib/usrp/cores/tx_vita_core_3000.cpp
+++ b/host/lib/usrp/cores/tx_vita_core_3000.cpp
@@ -18,9 +18,11 @@
 #include "tx_vita_core_3000.hpp"
 #include <uhd/utils/safe_call.hpp>
 
-#define REG_CTRL_ERROR_POLICY           _base + 0
-#define REG_DEFRAMER_CYCLE_FC_UPS       _base + 2*4 + 0
-#define REG_DEFRAMER_PACKET_FC_UPS      _base + 2*4 + 4
+#define REG_CTRL_ERROR_POLICY       (_base + 0)
+#define REG_FC_PRE_RADIO_RESP_BASE  (_base + 2*4)
+#define REG_FC_PRE_FIFO_RESP_BASE   (_base + 4*4)
+#define REG_CTRL_FC_CYCLE_OFFSET    (0*4)
+#define REG_CTRL_FC_PACKET_OFFSET   (1*4)
 
 using namespace uhd;
 
@@ -32,12 +34,22 @@ struct tx_vita_core_3000_impl : tx_vita_core_3000
 {
     tx_vita_core_3000_impl(
         wb_iface::sptr iface,
-        const size_t base
+        const size_t base,
+        fc_monitor_loc fc_location
     ):
         _iface(iface),
-        _base(base)
+        _base(base),
+        _fc_base((fc_location==FC_PRE_RADIO or fc_location==FC_DEFAULT) ?
+                    REG_FC_PRE_RADIO_RESP_BASE : REG_FC_PRE_FIFO_RESP_BASE),
+        _fc_location(fc_location)
     {
-        this->set_tick_rate(1); //init to non zero
+        if (fc_location != FC_DEFAULT) {
+            //Turn off the other FC monitoring module
+            const size_t other_fc_base = (fc_location==FC_PRE_RADIO) ?
+                    REG_FC_PRE_FIFO_RESP_BASE : REG_FC_PRE_RADIO_RESP_BASE;
+            _iface->poke32(other_fc_base + REG_CTRL_FC_CYCLE_OFFSET, 0);
+            _iface->poke32(other_fc_base + REG_CTRL_FC_PACKET_OFFSET, 0);
+        }
         this->set_underflow_policy("next_packet");
         this->clear();
     }
@@ -56,11 +68,6 @@ struct tx_vita_core_3000_impl : tx_vita_core_3000
         this->set_underflow_policy(_policy); //clears the seq
     }
 
-    void set_tick_rate(const double rate)
-    {
-        _tick_rate = rate;
-    }
-
     void set_underflow_policy(const std::string &policy)
     {
         if (policy == "next_packet")
@@ -89,23 +96,35 @@ struct tx_vita_core_3000_impl : tx_vita_core_3000
 
     void configure_flow_control(const size_t cycs_per_up, const size_t pkts_per_up)
     {
-        if (cycs_per_up == 0) _iface->poke32(REG_DEFRAMER_CYCLE_FC_UPS, 0);
-        else _iface->poke32(REG_DEFRAMER_CYCLE_FC_UPS, (1 << 31) | ((cycs_per_up) & 0xffffff));
+        if (cycs_per_up == 0) _iface->poke32(_fc_base + REG_CTRL_FC_CYCLE_OFFSET, 0);
+        else _iface->poke32(_fc_base + REG_CTRL_FC_CYCLE_OFFSET, (1 << 31) | ((cycs_per_up) & 0xffffff));
 
-        if (pkts_per_up == 0) _iface->poke32(REG_DEFRAMER_PACKET_FC_UPS, 0);
-        else _iface->poke32(REG_DEFRAMER_PACKET_FC_UPS, (1 << 31) | ((pkts_per_up) & 0xffff));
+        if (pkts_per_up == 0) _iface->poke32(_fc_base + REG_CTRL_FC_PACKET_OFFSET, 0);
+        else _iface->poke32(_fc_base + REG_CTRL_FC_PACKET_OFFSET, (1 << 31) | ((pkts_per_up) & 0xffff));
     }
 
-    wb_iface::sptr _iface;
-    const size_t _base;
-    double _tick_rate;
-    std::string _policy;
+    wb_iface::sptr  _iface;
+    const size_t    _base;
+    const size_t    _fc_base;
+    std::string     _policy;
+    fc_monitor_loc  _fc_location;
+
 };
 
 tx_vita_core_3000::sptr tx_vita_core_3000::make(
     wb_iface::sptr iface,
+    const size_t base,
+    fc_monitor_loc fc_location
+)
+{
+    return tx_vita_core_3000::sptr(new tx_vita_core_3000_impl(iface, base, fc_location));
+}
+
+tx_vita_core_3000::sptr tx_vita_core_3000::make_no_radio_buff(
+    wb_iface::sptr iface,
     const size_t base
 )
 {
-    return tx_vita_core_3000::sptr(new tx_vita_core_3000_impl(iface, base));
+    //No internal radio buffer so only pre-radio monitoring is supported.
+    return tx_vita_core_3000::sptr(new tx_vita_core_3000_impl(iface, base, FC_DEFAULT));
 }
diff --git a/host/lib/usrp/cores/tx_vita_core_3000.hpp b/host/lib/usrp/cores/tx_vita_core_3000.hpp
index 4c0052d4f..bd0f20ba4 100644
--- a/host/lib/usrp/cores/tx_vita_core_3000.hpp
+++ b/host/lib/usrp/cores/tx_vita_core_3000.hpp
@@ -32,17 +32,27 @@ class tx_vita_core_3000 : boost::noncopyable
 public:
     typedef boost::shared_ptr<tx_vita_core_3000> sptr;
 
+    enum fc_monitor_loc {
+        FC_DEFAULT,
+        FC_PRE_RADIO,
+        FC_PRE_FIFO
+    };
+
     virtual ~tx_vita_core_3000(void) = 0;
 
     static sptr make(
         uhd::wb_iface::sptr iface,
+        const size_t base,
+        fc_monitor_loc fc_location = FC_PRE_RADIO
+    );
+
+    static sptr make_no_radio_buff(
+        uhd::wb_iface::sptr iface,
         const size_t base
     );
 
     virtual void clear(void) = 0;
 
-    virtual void set_tick_rate(const double rate) = 0;
-
     virtual void setup(const uhd::stream_args_t &stream_args) = 0;
 
     virtual void configure_flow_control(const size_t cycs_per_up, const size_t pkts_per_up) = 0;