diff options
Diffstat (limited to 'host/lib/usrp/common')
| -rw-r--r-- | host/lib/usrp/common/ad9361_ctrl.hpp | 6 | ||||
| -rw-r--r-- | host/lib/usrp/common/ad9361_driver/ad9361_device.cpp | 5 | ||||
| -rw-r--r-- | host/lib/usrp/common/ad9361_driver/ad9361_device.h | 1 | 
3 files changed, 8 insertions, 4 deletions
| diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp index 5c438ee9c..8cd75d539 100644 --- a/host/lib/usrp/common/ad9361_ctrl.hpp +++ b/host/lib/usrp/common/ad9361_ctrl.hpp @@ -89,8 +89,10 @@ public:      //! get the clock rate range for the frontend      static uhd::meta_range_t get_clock_rate_range(void)      { -        //return uhd::meta_range_t(220e3, 61.44e6); -        return uhd::meta_range_t(5e6, ad9361_device_t::AD9361_MAX_CLOCK_RATE); //5 MHz DCM low end +        return uhd::meta_range_t( +                ad9361_device_t::AD9361_MIN_CLOCK_RATE, +                ad9361_device_t::AD9361_MAX_CLOCK_RATE +        );      }      //! set the filter bandwidth for the frontend's analog low pass diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp index 0a8a61575..bb25379c0 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp @@ -91,6 +91,7 @@ int get_num_taps(int max_num_taps) {  }  const double ad9361_device_t::AD9361_MAX_GAIN        = 89.75; +const double ad9361_device_t::AD9361_MIN_CLOCK_RATE  = 220e3;  const double ad9361_device_t::AD9361_MAX_CLOCK_RATE  = 61.44e6;  const double ad9361_device_t::AD9361_CAL_VALID_WINDOW = 100e6;  // Max bandwdith is due to filter rolloff in analog filter stage @@ -770,7 +771,7 @@ void ad9361_device_t::_calibrate_rf_dc_offset()      size_t count = 0;      _io_iface->poke8(0x016, 0x02);      while (_io_iface->peek8(0x016) & 0x02) { -        if (count > 100) { +        if (count > 200) {              throw uhd::runtime_error("[ad9361_device_t] RF DC Offset Calibration Failure");              break;          } @@ -821,7 +822,7 @@ void ad9361_device_t::_calibrate_rx_quadrature()      size_t count = 0;      _io_iface->poke8(0x016, 0x20);      while (_io_iface->peek8(0x016) & 0x20) { -        if (count > 100) { +        if (count > 1000) {              throw uhd::runtime_error("[ad9361_device_t] Rx Quadrature Calibration Failure");              break;          } diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h index 66bc2e8b9..73b1d9a35 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h @@ -157,6 +157,7 @@ public:      //Constants      static const double AD9361_MAX_GAIN;      static const double AD9361_MAX_CLOCK_RATE; +    static const double AD9361_MIN_CLOCK_RATE;      static const double AD9361_CAL_VALID_WINDOW;      static const double AD9361_RECOMMENDED_MAX_BANDWIDTH;      static const double DEFAULT_RX_FREQ; | 
