2 files changed, 17 insertions, 2 deletions

diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
index 0a8a61575..095017bb6 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
@@ -91,6 +91,7 @@ int get_num_taps(int max_num_taps) {
 }
 
 const double ad9361_device_t::AD9361_MAX_GAIN        = 89.75;
+const double ad9361_device_t::AD9361_MIN_CLOCK_RATE  = 220e3;
 const double ad9361_device_t::AD9361_MAX_CLOCK_RATE  = 61.44e6;
 const double ad9361_device_t::AD9361_CAL_VALID_WINDOW = 100e6;
 // Max bandwdith is due to filter rolloff in analog filter stage
@@ -770,7 +771,7 @@ void ad9361_device_t::_calibrate_rf_dc_offset()
     size_t count = 0;
     _io_iface->poke8(0x016, 0x02);
     while (_io_iface->peek8(0x016) & 0x02) {
-        if (count > 100) {
+        if (count > 200) {
             throw uhd::runtime_error("[ad9361_device_t] RF DC Offset Calibration Failure");
             break;
         }
@@ -821,7 +822,7 @@ void ad9361_device_t::_calibrate_rx_quadrature()
     size_t count = 0;
     _io_iface->poke8(0x016, 0x20);
     while (_io_iface->peek8(0x016) & 0x20) {
-        if (count > 100) {
+        if (count > 1000) {
             throw uhd::runtime_error("[ad9361_device_t] Rx Quadrature Calibration Failure");
             break;
         }
@@ -1564,6 +1565,12 @@ void ad9361_device_t::initialize()
     _io_iface->poke8(0x000, 0x00);
     boost::this_thread::sleep(boost::posix_time::milliseconds(20));
 
+    /* Check device ID to make sure iface works */
+    boost::uint32_t device_id = (_io_iface->peek8(0x037) & 0x8);
+    if (device_id != 0x8) {
+        throw uhd::runtime_error(str(boost::format("[ad9361_device_t::initialize] Device ID readback failure. Expected: 0x8, Received: 0x%x") % device_id));
+    }
+
     /* There is not a WAT big enough for this. */
     _io_iface->poke8(0x3df, 0x01);
 
@@ -1773,6 +1780,10 @@ void ad9361_device_t::initialize()
     _io_iface->poke8(0x014, 0x21);
 }
 
+void ad9361_device_t::set_io_iface(ad9361_io::sptr io_iface)
+{
+    _io_iface = io_iface;
+}
 
 /* This function sets the RX / TX rate between AD9361 and the FPGA, and
  * thus determines the interpolation / decimation required in the FPGA to
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
index 66bc2e8b9..d0e8a7e39 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
@@ -75,6 +75,9 @@ public:
     /* Initialize the AD9361 codec. */
     void initialize();
 
+    /* Set SPI interface */
+    void set_io_iface(ad9361_io::sptr io_iface);
+
     /* This function sets the RX / TX rate between AD9361 and the FPGA, and
      * thus determines the interpolation / decimation required in the FPGA to
      * achieve the user's requested rate.
@@ -157,6 +160,7 @@ public:
     //Constants
     static const double AD9361_MAX_GAIN;
     static const double AD9361_MAX_CLOCK_RATE;
+    static const double AD9361_MIN_CLOCK_RATE;
     static const double AD9361_CAL_VALID_WINDOW;
     static const double AD9361_RECOMMENDED_MAX_BANDWIDTH;
     static const double DEFAULT_RX_FREQ;