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-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_client.h4
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_device.cpp34
2 files changed, 19 insertions, 19 deletions
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_client.h b/host/lib/usrp/common/ad9361_driver/ad9361_client.h
index 921045fbd..4fea53521 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_client.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_client.h
@@ -34,10 +34,10 @@ typedef enum {
/*!
* Clocking mode
*/
-typedef enum {
+enum class clocking_mode_t {
AD9361_XTAL_P_CLK_PATH,
AD9361_XTAL_N_CLK_PATH
-} clocking_mode_t;
+};
/*!
* Digital interface specific
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
index e2ed2c77d..e11079ae3 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
@@ -24,7 +24,7 @@
#include <cmath>
#include <uhd/exception.hpp>
#include <uhd/utils/log.hpp>
-#include <uhd/utils/msg.hpp>
+
#include <stdint.h>
#include <boost/date_time/posix_time/posix_time.hpp>
#include <boost/thread/thread.hpp>
@@ -321,7 +321,7 @@ double ad9361_device_t::_calibrate_baseband_rx_analog_filter(double req_rfbw)
double bbbw = req_rfbw / 2.0;
if(bbbw > _baseband_bw / 2.0)
{
- UHD_LOG << "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw;
+ UHD_LOGGER_DEBUG("AD936X")<< "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw;
bbbw = _baseband_bw / 2.0;
}
@@ -388,7 +388,7 @@ double ad9361_device_t::_calibrate_baseband_tx_analog_filter(double req_rfbw)
if(bbbw > _baseband_bw / 2.0)
{
- UHD_LOG << "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw;
+ UHD_LOGGER_DEBUG("AD936X")<< "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw;
bbbw = _baseband_bw / 2.0;
}
@@ -443,7 +443,7 @@ double ad9361_device_t::_calibrate_secondary_tx_filter(double req_rfbw)
if(bbbw > _baseband_bw / 2.0)
{
- UHD_LOG << "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw;
+ UHD_LOGGER_DEBUG("AD936X")<< "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw;
bbbw = _baseband_bw / 2.0;
}
@@ -539,7 +539,7 @@ double ad9361_device_t::_calibrate_rx_TIAs(double req_rfbw)
if(bbbw > _baseband_bw / 2.0)
{
- UHD_LOG << "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw;
+ UHD_LOGGER_DEBUG("AD936X")<< "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw;
bbbw = _baseband_bw / 2.0;
}
@@ -1169,7 +1169,7 @@ void ad9361_device_t::_setup_synth(direction_t direction, double vcorate)
* fed to the public set_clock_rate function. */
double ad9361_device_t::_tune_bbvco(const double rate)
{
- UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] rate=%.10f\n") % rate;
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::_tune_bbvco] rate=%.10f\n") % rate;
/* Let's not re-tune to the same frequency over and over... */
if (freq_is_nearly_equal(rate, _req_coreclk)) {
@@ -1197,13 +1197,13 @@ double ad9361_device_t::_tune_bbvco(const double rate)
if (i == 7)
throw uhd::runtime_error("[ad9361_device_t] _tune_bbvco: wrong vcorate");
- UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] vcodiv=%d vcorate=%.10f\n") % vcodiv % vcorate;
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::_tune_bbvco] vcodiv=%d vcorate=%.10f\n") % vcodiv % vcorate;
/* Fo = Fref * (Nint + Nfrac / mod) */
int nint = static_cast<int>(vcorate / fref);
- UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] (nint)=%.10f\n") % (vcorate / fref);
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::_tune_bbvco] (nint)=%.10f\n") % (vcorate / fref);
int nfrac = static_cast<int>(boost::math::round(((vcorate / fref) - (double) nint) * (double) modulus));
- UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] (nfrac)=%.10f\n") % (((vcorate / fref) - (double) nint) * (double) modulus);
- UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] nint=%d nfrac=%d\n") % nint % nfrac;
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::_tune_bbvco] (nfrac)=%.10f\n") % (((vcorate / fref) - (double) nint) * (double) modulus);
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::_tune_bbvco] nint=%d nfrac=%d\n") % nint % nfrac;
double actual_vcorate = fref
* ((double) nint + ((double) nfrac / (double) modulus));
@@ -1381,7 +1381,7 @@ double ad9361_device_t::_setup_rates(const double rate)
/* If we make it into this function, then we are tuning to a new rate.
* Store the new rate. */
_req_clock_rate = rate;
- UHD_LOG << boost::format("[ad9361_device_t::_setup_rates] rate=%.6d\n") % rate;
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::_setup_rates] rate=%.6d\n") % rate;
/* Set the decimation and interpolation values in the RX and TX chains.
* This also switches filters in / out. Note that all transmitters and
@@ -1467,7 +1467,7 @@ double ad9361_device_t::_setup_rates(const double rate)
throw uhd::runtime_error("[ad9361_device_t] [_setup_rates] INVALID_CODE_PATH");
}
- UHD_LOG << boost::format("[ad9361_device_t::_setup_rates] divfactor=%d\n") % divfactor;
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::_setup_rates] divfactor=%d\n") % divfactor;
/* Tune the BBPLL to get the ADC and DAC clocks. */
const double adcclk = _tune_bbvco(rate * divfactor);
@@ -1489,7 +1489,7 @@ double ad9361_device_t::_setup_rates(const double rate)
_io_iface->poke8(0x004, _regs.inputsel);
_io_iface->poke8(0x00A, _regs.bbpll);
- UHD_LOG << boost::format("[ad9361_device_t::_setup_rates] adcclk=%f\n") % adcclk;
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::_setup_rates] adcclk=%f\n") % adcclk;
_baseband_bw = (adcclk / divfactor);
/*
@@ -1583,11 +1583,11 @@ void ad9361_device_t::initialize()
/* Enable clocks. */
switch (_client_params->get_clocking_mode()) {
- case AD9361_XTAL_N_CLK_PATH: {
+ case clocking_mode_t::AD9361_XTAL_N_CLK_PATH: {
_io_iface->poke8(0x009, 0x17);
} break;
- case AD9361_XTAL_P_CLK_PATH: {
+ case clocking_mode_t::AD9361_XTAL_P_CLK_PATH: {
_io_iface->poke8(0x009, 0x07);
_io_iface->poke8(0x292, 0x08);
_io_iface->poke8(0x293, 0x80);
@@ -1798,7 +1798,7 @@ double ad9361_device_t::set_clock_rate(const double req_rate)
throw uhd::runtime_error("[ad9361_device_t] Requested master clock rate outside range");
}
- UHD_LOG << boost::format("[ad9361_device_t::set_clock_rate] req_rate=%.10f\n") % req_rate;
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::set_clock_rate] req_rate=%.10f\n") % req_rate;
/* UHD has a habit of requesting the same rate like four times when it
* starts up. This prevents that, and any bugs in user code that request
@@ -1840,7 +1840,7 @@ double ad9361_device_t::set_clock_rate(const double req_rate)
* all the hard work gets done. */
double rate = _setup_rates(req_rate);
- UHD_LOG << boost::format("[ad9361_device_t::set_clock_rate] rate=%.10f\n") % rate;
+ UHD_LOGGER_DEBUG("AD936X")<< boost::format("[ad9361_device_t::set_clock_rate] rate=%.10f\n") % rate;
/* Transition to the ALERT state and calibrate everything. */
_io_iface->poke8(0x015, 0x04); //dual synth mode, synth en ctrl en
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 11:28:05 +0000