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-rw-r--r--host/lib/ic_reg_maps/.gitignore2
-rw-r--r--host/lib/ic_reg_maps/CMakeLists.txt90
-rw-r--r--host/lib/ic_reg_maps/common.py196
-rwxr-xr-xhost/lib/ic_reg_maps/gen_ad5623_regs.py48
-rwxr-xr-xhost/lib/ic_reg_maps/gen_ad7922_regs.py54
-rwxr-xr-xhost/lib/ic_reg_maps/gen_ad9510_regs.py139
-rwxr-xr-xhost/lib/ic_reg_maps/gen_ad9522_regs.py185
-rwxr-xr-xhost/lib/ic_reg_maps/gen_ad9777_regs.py120
-rwxr-xr-xhost/lib/ic_reg_maps/gen_ad9862_regs.py246
-rwxr-xr-xhost/lib/ic_reg_maps/gen_adf4350_regs.py121
-rwxr-xr-xhost/lib/ic_reg_maps/gen_adf4360_regs.py89
-rwxr-xr-xhost/lib/ic_reg_maps/gen_ads62p44_regs.py124
-rwxr-xr-xhost/lib/ic_reg_maps/gen_max2112_regs.py181
-rwxr-xr-xhost/lib/ic_reg_maps/gen_max2118_regs.py126
-rwxr-xr-xhost/lib/ic_reg_maps/gen_max2829_regs.py133
-rw-r--r--host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py75
16 files changed, 1929 insertions, 0 deletions
diff --git a/host/lib/ic_reg_maps/.gitignore b/host/lib/ic_reg_maps/.gitignore
new file mode 100644
index 000000000..053049d05
--- /dev/null
+++ b/host/lib/ic_reg_maps/.gitignore
@@ -0,0 +1,2 @@
+/*.pyc
+/*.pyo
diff --git a/host/lib/ic_reg_maps/CMakeLists.txt b/host/lib/ic_reg_maps/CMakeLists.txt
new file mode 100644
index 000000000..ac051b843
--- /dev/null
+++ b/host/lib/ic_reg_maps/CMakeLists.txt
@@ -0,0 +1,90 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+#This file will be included by cmake, use absolute paths!
+
+INCLUDE_DIRECTORIES(${CMAKE_BINARY_DIR}/lib/ic_reg_maps)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_adf4350_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/adf4350_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_adf4360_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/adf4360_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ad9510_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ad9510_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ad9777_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ad9777_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ad5623_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ad5623_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ad7922_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ad7922_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_max2829_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/max2829_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_max2118_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/max2118_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_max2112_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/max2112_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_max2112_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/max2112_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ad9862_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ad9862_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ad9522_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ad9522_regs.hpp
+)
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ads62p44_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ads62p44_regs.hpp
+ )
+
+LIBUHD_PYTHON_GEN_SOURCE(
+ ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_tuner_4937di5_regs.py
+ ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/tuner_4937di5_regs.hpp
+)
diff --git a/host/lib/ic_reg_maps/common.py b/host/lib/ic_reg_maps/common.py
new file mode 100644
index 000000000..986093004
--- /dev/null
+++ b/host/lib/ic_reg_maps/common.py
@@ -0,0 +1,196 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+import re
+import sys
+import math
+from Cheetah.Template import Template
+
+COMMON_TMPL = """\
+#import time
+/***********************************************************************
+ * This file was generated by $file on $time.strftime("%c")
+ **********************************************************************/
+
+\#ifndef INCLUDED_$(name.upper())_HPP
+\#define INCLUDED_$(name.upper())_HPP
+
+\#include <uhd/config.hpp>
+\#include <boost/cstdint.hpp>
+\#include <stdexcept>
+\#include <set>
+
+class $(name)_t{
+public:
+ #for $reg in $regs
+ #if $reg.get_enums()
+ enum $reg.get_type(){
+ #for $i, $enum in enumerate($reg.get_enums())
+ #set $end_comma = ',' if $i < len($reg.get_enums())-1 else ''
+ $(reg.get_name().upper())_$(enum[0].upper()) = $enum[1]$end_comma
+ #end for
+ };
+ #end if
+ $reg.get_type() $reg.get_name();
+ #end for
+
+ $(name)_t(void){
+ _state = NULL;
+ #for $reg in $regs
+ $reg.get_name() = $reg.get_default();
+ #end for
+ }
+
+ ~$(name)_t(void){
+ delete _state;
+ }
+
+ $body
+
+ void save_state(void){
+ if (_state == NULL) _state = new $(name)_t();
+ #for $reg in $regs
+ _state->$reg.get_name() = this->$reg.get_name();
+ #end for
+ }
+
+ template<typename T> std::set<T> get_changed_addrs(void){
+ if (_state == NULL) throw std::runtime_error("no saved state");
+ //check each register for changes
+ std::set<T> addrs;
+ #for $reg in $regs
+ if(_state->$reg.get_name() != this->$reg.get_name()){
+ addrs.insert($reg.get_addr());
+ }
+ #end for
+ return addrs;
+ }
+
+ #for $mreg in $mregs
+ $mreg.get_type() get_$(mreg.get_name())(void){
+ return
+ #set $shift = 0
+ #for $reg in $mreg.get_regs()
+ ($(mreg.get_type())($reg.get_name() & $reg.get_mask()) << $shift) |
+ #set $shift = $shift + $reg.get_bit_width()
+ #end for
+ 0;
+ }
+
+ void set_$(mreg.get_name())($mreg.get_type() reg){
+ #set $shift = 0
+ #for $reg in $mreg.get_regs()
+ $reg.get_name() = (reg >> $shift) & $reg.get_mask();
+ #set $shift = $shift + $reg.get_bit_width()
+ #end for
+ }
+
+ #end for
+private:
+ $(name)_t *_state;
+};
+
+\#endif /* INCLUDED_$(name.upper())_HPP */
+"""
+
+def parse_tmpl(_tmpl_text, **kwargs):
+ return str(Template(_tmpl_text, kwargs))
+
+def to_num(arg): return int(eval(arg))
+
+class reg:
+ def __init__(self, reg_des):
+ try: self.parse(reg_des)
+ except Exception, e:
+ raise Exception, 'Error parsing register description: "%s"\nWhat: %s'%(reg_des, e)
+
+ def parse(self, reg_des):
+ x = re.match('^(\w*)\s*(\w*)\[(.*)\]\s*(\w*)\s*(.*)$', reg_des)
+ name, addr, bit_range, default, enums = x.groups()
+
+ #store variables
+ self._name = name
+ self._addr = to_num(addr)
+ if ':' in bit_range: self._addr_spec = sorted(map(int, bit_range.split(':')))
+ else: self._addr_spec = int(bit_range), int(bit_range)
+ self._default = to_num(default)
+
+ #extract enum
+ self._enums = list()
+ if enums:
+ enum_val = 0
+ for enum_str in map(str.strip, enums.split(',')):
+ if '=' in enum_str:
+ enum_name, enum_val = enum_str.split('=')
+ enum_val = to_num(enum_val)
+ else: enum_name = enum_str
+ self._enums.append((enum_name, enum_val))
+ enum_val += 1
+
+ def get_addr(self): return self._addr
+ def get_enums(self): return self._enums
+ def get_name(self): return self._name
+ def get_default(self):
+ for key, val in self.get_enums():
+ if val == self._default: return str.upper('%s_%s'%(self.get_name(), key))
+ return self._default
+ def get_type(self):
+ if self.get_enums(): return '%s_t'%self.get_name()
+ return 'boost::uint%d_t'%max(2**math.ceil(math.log(self.get_bit_width(), 2)), 8)
+ def get_shift(self): return self._addr_spec[0]
+ def get_mask(self): return hex(int('1'*self.get_bit_width(), 2))
+ def get_bit_width(self): return self._addr_spec[1] - self._addr_spec[0] + 1
+
+class mreg:
+ def __init__(self, mreg_des, regs):
+ try: self.parse(mreg_des, regs)
+ except Exception, e:
+ raise Exception, 'Error parsing meta register description: "%s"\nWhat: %s'%(mreg_des, e)
+
+ def parse(self, mreg_des, regs):
+ x = re.match('^~(\w*)\s+(.*)\s*$', mreg_des)
+ self._name, reg_names = x.groups()
+ regs_dict = dict([(reg.get_name(), reg) for reg in regs])
+ self._regs = [regs_dict[reg_name] for reg_name in map(str.strip, reg_names.split(','))]
+
+ def get_name(self): return self._name
+ def get_regs(self): return self._regs
+ def get_bit_width(self): return sum(map(reg.get_bit_width, self._regs))
+ def get_type(self):
+ return 'boost::uint%d_t'%max(2**math.ceil(math.log(self.get_bit_width(), 2)), 8)
+
+def generate(name, regs_tmpl, body_tmpl='', file=__file__, append=False):
+ #evaluate the regs template and parse each line into a register
+ regs = list(); mregs = list()
+ for entry in parse_tmpl(regs_tmpl).splitlines():
+ if entry.startswith('~'): mregs.append(mreg(entry, regs))
+ else: regs.append(reg(entry))
+
+ #evaluate the body template with the list of registers
+ body = '\n '.join(parse_tmpl(body_tmpl, regs=regs).splitlines())
+
+ #evaluate the code template with the parsed registers and arguments
+ code = parse_tmpl(COMMON_TMPL,
+ name=name,
+ regs=regs,
+ mregs=mregs,
+ body=body,
+ file=file,
+ )
+
+ #write the generated code to file specified by argv1
+ open(sys.argv[1], 'a' if append else 'w').write(code)
diff --git a/host/lib/ic_reg_maps/gen_ad5623_regs.py b/host/lib/ic_reg_maps/gen_ad5623_regs.py
new file mode 100755
index 000000000..e653921ba
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_ad5623_regs.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+data 0[4:15] 0
+addr 0[16:18] 0 DAC_A=0, DAC_B=1, ALL=7
+cmd 0[19:21] 0 wr_input_n, up_dac_n, wr_input_n_up_all, wr_up_dac_chan_n, power_down, reset, load_ldac
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint32_t get_reg(void){
+ boost::uint32_t reg = 0;
+ #for $reg in filter(lambda r: r.get_addr() == 0, $regs)
+ reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ return reg;
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='ad5623_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_ad7922_regs.py b/host/lib/ic_reg_maps/gen_ad7922_regs.py
new file mode 100755
index 000000000..5cec1924a
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_ad7922_regs.py
@@ -0,0 +1,54 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+result 0[0:11] 0
+mod 0[12] 0
+chn 0[13] 0
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint16_t get_reg(void){
+ boost::uint16_t reg = 0;
+ #for $reg in filter(lambda r: r.get_addr() == 0, $regs)
+ reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ return reg;
+}
+
+void set_reg(boost::uint16_t reg){
+ #for $reg in filter(lambda r: r.get_addr() == 0, $regs)
+ $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask());
+ #end for
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='ad7922_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_ad9510_regs.py b/host/lib/ic_reg_maps/gen_ad9510_regs.py
new file mode 100755
index 000000000..83236c921
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_ad9510_regs.py
@@ -0,0 +1,139 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+########################################################################
+## serial control port config
+########################################################################
+long_instruction 0[4] 1 8bits, 16bits
+soft_reset 0[5] 0
+lsb_first 0[6] 0 msb, lsb
+sdo_inactive 0[7] 0 active, inactive
+########################################################################
+## pll settings
+########################################################################
+acounter 4[0:5] 0
+bcounter_msb 5[0:4] 0
+bcounter_lsb 6[0:7] 0
+lor_enable 7[2] 0 enb, dis
+lor_ildd 7[5:6] 0 3cyc, 6cyc, 12cyc, 24cyc
+charge_pump_mode 8[0:1] 0 3state, pump_up, pump_down, normal
+pll_mux_control 8[2:5] 0 off, dld_high, ndiv, dld_low, rdiv, ald_nchan, acounter, prescaler, pfd_up, pfd_down, lor_high, 3state, ald_pchan, lor_lol_high, lor_lol_low, lor_low
+pfd_polarity 8[6] 0 neg, pos
+reset_all_counters 9[0] 0
+ncounter_reset 9[1] 0
+rcounter_reset 9[2] 0
+cp_current_setting 9[4:6] 0 0_60ma, 1_2ma, 1_8ma, 2_4ma, 3_0ma, 3_6ma, 4_2ma, 4_8ma
+pll_power_down 0xA[0:1] 0 normal=0, async_pd=1, sync_pd=3
+prescaler_value 0xA[2:4] 0 div1, div2, 2_3, 4_5, 8_9, 16_17, 32_33, div3
+b_counter_bypass 0xA[6] 0
+ref_counter_msb 0xB[0:5] 0
+ref_counter_lsb 0xC[0:7] 0
+antibacklash_pw 0xD[0:1] 0 1_3ns, 2_9ns, 6_0ns
+dld_window 0xD[5] 0 9_5ns, 3_5ns
+lock_detect_disable 0xD[6] 0 enb, dis
+########################################################################
+## fine delay adjust
+########################################################################
+#for $i, $o in ((5, 0), (6, 4))
+delay_control_out$i $hex(0x34+$o)[0] 0
+ramp_current_out$i $hex(0x35+$o)[0:2] 0 200ua, 400ua, 600ua, 800ua, 1000ua, 1200ua, 1400ua, 1600ua
+ramp_capacitor_out$i $hex(0x35+$o)[3:5] 0 4caps=0, 3caps=1, 2caps=3, 1cap=7
+delay_fine_adjust_out$i $hex(0x36+$o)[1:5] 0
+#end for
+########################################################################
+## outputs
+########################################################################
+#for $i, $o in ((0, 0), (1, 1), (2, 2), (3, 3))
+power_down_lvpecl_out$i $hex(0x3C+$o)[0:1] 0 normal, test, safe_pd, total_pd
+output_level_lvpecl_out$i $hex(0x3C+$o)[2:3] 2 500mv, 340mv, 810mv, 660mv
+#end for
+#for $i, $o in ((4, 0), (5, 1), (6, 2), (7, 3))
+power_down_lvds_cmos_out$i $hex(0x40+$o)[0] 0
+output_level_lvds_out$i $hex(0x40+$o)[1:2] 1 1_75ma, 3_5ma, 5_25ma, 7ma
+lvds_cmos_select_out$i $hex(0x40+$o)[3] 1 lvds, cmos
+inverted_cmos_driver_out$i $hex(0x40+$o)[4] 0 dis, enb
+#end for
+clock_select 45[0] 1 clk2_drives, clk1_drives
+clk1_power_down 45[1] 0
+clk2_power_down 45[2] 0
+prescaler_clock_pd 45[3] 0
+refin_power_down 45[4] 0
+all_clock_inputs_pd 45[5] 0
+########################################################################
+## dividers
+########################################################################
+#for $i, $o in ((0, 0), (1, 2), (2, 4), (3, 6), (4, 8), (5, 10), (6, 12), (7, 14))
+divider_high_cycles_out$i $hex(0x48+$o)[0:3] 0
+divider_low_cycles_out$i $hex(0x48+$o)[4:7] 0
+phase_offset_out$i $hex(0x49+$o)[0:3] 0
+start_out$i $hex(0x49+$o)[4] 0
+force_out$i $hex(0x49+$o)[5] 0
+nosync_out$i $hex(0x49+$o)[6] 0
+bypass_divider_out$i $hex(0x49+$o)[7] 0
+#end for
+########################################################################
+## function
+########################################################################
+sync_detect_enable 58[0] 0 dis, enb
+sync_select 58[1] 0 1_to_0_5, 0_5_to_1
+soft_sync 58[2] 0
+dist_power_down 58[3] 0
+sync_power_down 58[4] 0
+function_pin_select 58[5:6] 0 resetb, syncb, test, pdb
+update_registers 0x5A[0] 0
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint8_t get_reg(boost::uint16_t addr){
+ boost::uint8_t reg = 0;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return reg;
+}
+
+boost::uint32_t get_write_reg(boost::uint16_t addr){
+ return (boost::uint32_t(addr) << 8) | get_reg(addr);
+}
+
+boost::uint32_t get_read_reg(boost::uint16_t addr){
+ return (boost::uint32_t(addr) << 8) | (1 << 23);
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='ad9510_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py
new file mode 100755
index 000000000..a5debe568
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py
@@ -0,0 +1,185 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+sdo_active 0x000[7] 0 sdio, sdo_sdio
+lsb_first_addr_incr 0x000[6] 0 msb, lsb
+soft_reset 0x000[5] 0
+mirror 0x000[3:0] 0
+readback_active_registers 0x004[0] 0 buffer, active
+pfd_polarity 0x010[7] 0 pos, neg
+cp_current 0x010[6:4] 7 0_6ma, 1_2ma, 1_8ma, 2_4ma, 3_0ma, 3_6ma, 4_2ma, 4_8ma
+cp_mode 0x010[3:2] 3 high_imp, force_source, force_sink, normal
+pll_power_down 0x010[1:0] 1 normal=0, async=1, sync=3
+r_counter_lsb 0x011[7:0] 1
+r_counter_msb 0x012[5:0] 0
+~r_counter r_counter_lsb, r_counter_msb
+a_counter 0x013[5:0] 0
+b_counter_lsb 0x014[7:0] 3
+b_counter_msb 0x015[4:0] 0
+~b_counter b_counter_lsb, b_counter_msb
+set_cp_pin_to_vcp_2 0x016[7] 0 normal, vcp_2
+reset_r_counter 0x016[6] 0
+reset_a_and_b_counters 0x016[5] 0
+reset_all_counters 0x016[4] 0
+b_counter_bypass 0x016[3] 0 normal, div1
+prescaler_p 0x016[2:0] 6 div1, div2, div2_3, div4_5, div8_9, div16_17, div32_33, div3
+status_pin_control 0x017[7:2] 0
+antibacklash_pulse_width 0x017[1:0] 0 2_9ns, 1_3ns, 6_0ns
+enb_cmos_ref_input_dc_off 0x018[7] 0
+lock_detect_counter 0x018[6:5] 0 5cyc, 16cyc, 64cyc, 255cyc
+digital_lock_detect_window 0x018[4] 0 high_range, low_range
+disable_digital_lock_detect 0x018[3] 0 normal, disabled
+vco_calibration_divider 0x018[2:1] 3 div2, div4, div8, div16
+vco_calibration_now 0x018[0] 0
+r_a_b_counters_sync_pin_rst 0x019[7:6] 0 nothing, async, sync
+r_path_delay 0x019[5:3] 0
+n_path_delay 0x019[2:0] 0
+enable_status_pin_divider 0x01A[7] 0
+ref_freq_monitor_threshold 0x01A[6] 0 1_02mhz, 6khz
+ld_pin_control 0x01A[5:0] 0
+enable_vco_freq_monitor 0x01B[7] 0
+enable_ref2_freq_monitor 0x01B[6] 0
+enable_ref1_freq_monitor 0x01B[5] 0
+refmon_pin_control 0x01B[4:0] 0
+disable_switchover_deglitch 0x01C[7] 0
+select_ref 0x01C[6] 0 ref1, ref2
+use_ref_sel_pin 0x01C[5] 0 register, ref_sel
+enb_auto_ref_switchover 0x01C[4] 0 manual, auto
+stay_on_ref2 0x01C[3] 0 return_ref1, stay_ref2
+enable_ref2 0x01C[2] 0
+enable_ref1 0x01C[1] 0
+enable_differential_ref 0x01C[0] 0
+enb_stat_eeprom_at_stat_pin 0x01D[7] 1
+enable_xtal_osc 0x01D[6] 0
+enable_clock_doubler 0x01D[5] 0
+disable_pll_status_reg 0x01D[4] 0
+enable_ld_pin_comparator 0x01D[3] 0
+enable_external_holdover 0x01D[1] 0
+enable_holdover 0x01D[0] 0
+external_zero_delay_fcds 0x01E[4:3] 0
+enable_external_zero_delay 0x01E[2] 0
+enable_zero_delay 0x01E[1] 0
+########################################################################
+#for $i in range(12)
+#set $addr = ($i + 0x0F0)
+out$(i)_format $(addr)[7] 0 lvds, cmos
+out$(i)_cmos_configuration $(addr)[6:5] 3 off, a_on, b_on, ab_on
+out$(i)_polarity $(addr)[4:3] 0 lvds_a_non_b_inv=0, lvds_a_inv_b_non=1, cmos_ab_non=0, cmos_ab_inv=1, cmos_a_non_b_inv=2, cmos_a_inv_b_non=3
+out$(i)_lvds_diff_voltage $(addr)[2:1] 1 1_75ma, 3_5ma, 5_25ma, 7_0ma
+out$(i)_lvds_power_down $(addr)[0] 0
+#end for
+########################################################################
+#for $i in reversed(range(8))
+csdld_en_out_$i 0x0FC[$i] 0 ignore, async
+#end for
+########################################################################
+#for $i in reversed(range(4))
+csdld_en_out_$(8 + $i) 0x0FD[$i] 0 ignore, async
+#end for
+########################################################################
+#set $default_val = 0x7
+#for $i in range(4)
+#set $addr0 = hex($i*3 + 0x190)
+#set $addr1 = hex($i*3 + 0x191)
+#set $addr2 = hex($i*3 + 0x192)
+divider$(i)_low_cycles $(addr0)[7:4] $default_val
+divider$(i)_high_cycles $(addr0)[3:0] $default_val
+divider$(i)_bypass $(addr1)[7] 0
+divider$(i)_ignore_sync $(addr1)[6] 0
+divider$(i)_force_high $(addr1)[5] 0
+divider$(i)_start_high $(addr1)[4] 0
+divider$(i)_phase_offset $(addr1)[3:0] 0
+channel$(i)_power_down $(addr2)[2] 0
+disable_divider$(i)_ddc $(addr2)[0] 0
+#set $default_val /= 2
+#end for
+########################################################################
+vco_divider 0x1E0[2:0] 2 div2, div3, div4, div5, div6, static, div1
+power_down_clock_input_sel 0x1E1[4] 0
+power_down_vco_clock_ifc 0x1E1[3] 0
+power_down_vco_and_clock 0x1E1[2] 0
+select_vco_or_clock 0x1E1[1] 0 external, vco
+bypass_vco_divider 0x1E1[0] 0
+disable_power_on_sync 0x230[3] 0
+power_down_sync 0x230[2] 0
+power_down_dist_ref 0x230[1] 0
+soft_sync 0x230[0] 0
+io_update 0x232[0] 0
+soft_eeprom 0xB02[1] 0
+enable_eeprom_write 0xB02[0] 0
+reg2eeprom 0xB03[0] 0
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint32_t get_reg(boost::uint16_t addr){
+ boost::uint32_t reg = 0;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ if (addr == 0){ //mirror 4 bits in register 0
+ reg |= ((reg >> 7) & 0x1) << 0;
+ reg |= ((reg >> 6) & 0x1) << 1;
+ reg |= ((reg >> 5) & 0x1) << 2;
+ reg |= ((reg >> 4) & 0x1) << 3;
+ }
+ return reg;
+}
+
+void set_reg(boost::uint16_t addr, boost::uint32_t reg){
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask());
+ #end for
+ break;
+ #end for
+ }
+}
+
+boost::uint32_t get_write_reg(boost::uint16_t addr){
+ return (boost::uint32_t(addr) << 8) | get_reg(addr);
+}
+
+boost::uint32_t get_read_reg(boost::uint16_t addr){
+ return (boost::uint32_t(addr) << 8) | (1 << 23);
+}
+
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='ad9522_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_ad9777_regs.py b/host/lib/ic_reg_maps/gen_ad9777_regs.py
new file mode 100755
index 000000000..47b61cf44
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_ad9777_regs.py
@@ -0,0 +1,120 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+########################################################################
+## address 0
+########################################################################
+sdio_bidirectional 0[7] 0 input, io
+lsb_msb_first 0[6] 0 msb, lsb
+soft_reset 0[5] 0
+sleep_mode 0[4] 0
+power_down_mode 0[3] 0
+x_1r_2r_mode 0[2] 0 2r, 1r
+pll_lock_indicator 0[1] 0
+########################################################################
+## address 1
+########################################################################
+filter_interp_rate 1[6:7] 0 1x, 2x, 4x, 8x
+modulation_mode 1[4:5] 0 none, fs_2, fs_4, fs_8
+zero_stuff_mode 1[3] 0
+mix_mode 1[2] 1 complex, real
+modulation_form 1[1] 0 e_minus_jwt, e_plus_jwt
+data_clk_pll_lock_sel 1[0] 0 pll_lock, data_clk
+########################################################################
+## address 2
+########################################################################
+signed_input_data 2[7] 0 signed, unsigned
+two_port_mode 2[6] 0 two_port, one_port
+dataclk_driver_strength 2[5] 0 weak, strong
+dataclk_invert 2[4] 0
+oneportclk_invert 2[2] 0
+iqsel_invert 2[1] 0
+iq_first 2[0] 0 i_first, q_first
+########################################################################
+## address 3
+########################################################################
+data_rate_clock_output 3[7] 0 pll_lock, spi_sdo
+pll_divide_ratio 3[0:1] 0 div1, div2, div4, div8
+########################################################################
+## address 4
+########################################################################
+pll_state 4[7] 0 off, on
+auto_cp_control 4[6] 0 auto, manual
+pll_cp_control 4[0:2] 0 50ua=0, 100ua=1, 200ua=2, 400ua=3, 800ua=7
+########################################################################
+## address 5 and 9
+########################################################################
+idac_fine_gain_adjust 5[0:7] 0
+qdac_fine_gain_adjust 9[0:7] 0
+########################################################################
+## address 6 and A
+########################################################################
+idac_coarse_gain_adjust 6[0:3] 0
+qdac_coarse_gain_adjust 0xA[0:3] 0
+########################################################################
+## address 7, 8 and B, C
+########################################################################
+idac_offset_adjust_msb 7[0:7] 0
+idac_offset_adjust_lsb 8[0:1] 0
+~idac_offset_adjust idac_offset_adjust_lsb, idac_offset_adjust_msb
+idac_ioffset_direction 8[7] 0 out_a, out_b
+qdac_offset_adjust_msb 0xB[0:7] 0
+qdac_offset_adjust_lsb 0xC[0:1] 0
+~qdac_offset_adjust qdac_offset_adjust_lsb, qdac_offset_adjust_msb
+qdac_ioffset_direction 0xC[7] 0 out_a, out_b
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint8_t get_reg(boost::uint8_t addr){
+ boost::uint8_t reg = 0;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return reg;
+}
+
+boost::uint16_t get_write_reg(boost::uint8_t addr){
+ return (boost::uint16_t(addr) << 8) | get_reg(addr);
+}
+
+boost::uint16_t get_read_reg(boost::uint8_t addr){
+ return (boost::uint16_t(addr) << 8) | (1 << 7);
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='ad9777_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_ad9862_regs.py b/host/lib/ic_reg_maps/gen_ad9862_regs.py
new file mode 100755
index 000000000..00340224c
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_ad9862_regs.py
@@ -0,0 +1,246 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+########################################################################
+## General
+########################################################################
+sdio_bidir 0[7] 0 sdio_sdo, sdio
+lsb_first 0[6] 0 msb, lsb
+soft_reset 0[5] 0
+########################################################################
+## Rx Power Down
+########################################################################
+vref_diff_pd 1[7] 0
+vref_pd 1[6] 0
+rx_digital_pd 1[5] 0
+rx_channel_b_pd 1[4] 0
+rx_channel_a_pd 1[3] 0
+buffer_b_pd 1[2] 0
+buffer_a_pd 1[1] 0
+all_rx_pd 1[0] 0
+########################################################################
+## Rx A and B
+########################################################################
+#for $x, $i in (('a', 2), ('b', 3))
+byp_buffer_$x $(i)[7] 0
+rx_pga_$x $(i)[0:4] 0
+#end for
+########################################################################
+## Rx Misc
+########################################################################
+hs_duty_cycle 4[2] 0
+shared_ref 4[1] 0
+clk_duty 4[0] 0
+########################################################################
+## RX I/F (INTERFACE)
+########################################################################
+three_state 5[4] 0
+rx_retime 5[3] 0 clkout1, clkout2
+rx_twos_comp 5[2] 0
+inv_rxsync 5[1] 0
+mux_out 5[0] 0 rx_mux_mode=1, dual_port_mode=0
+########################################################################
+## RX Digital
+########################################################################
+two_channel 6[3] 1 rx_b_dis, both_enb
+rx_keep_ve 6[2] 0 pass_pos, pass_neg
+rx_hilbert 6[1] 0 dis, enb
+decimate 6[0] 0 dis, enb
+########################################################################
+## TX Power Down
+########################################################################
+alt_timing_mode 8[5] 0
+txoff_enable 8[4] 0
+tx_digital_pd 8[3] 0
+tx_analog_pd 8[0:2] 0 none=0, txb=4, txa=2, both=7
+########################################################################
+## Tx Offset and Gain
+########################################################################
+#for $x, $i, $j, $k in (('a', 10, 11, 14), ('b', 12, 13, 15))
+dac_$(x)_offset_1_0 $(i)[6:7] 0
+dac_$(x)_offset_dir $(i)[0] 0 neg_diff, pos_dif
+dac_$(x)_offset_9_2 $(j)[0:7] 0
+dac_$(x)_coarse_gain $(k)[6:7] 0
+dac_$(x)_fine_gain $(k)[0:5] 0
+#end for
+tx_pga_gain 16[0:7] 0
+########################################################################
+## Tx Misc
+########################################################################
+tx_slave_enable 17[1] 0
+tx_pga_mode 17[0] 0 normal, fast
+########################################################################
+## Tx IF (INTERFACE)
+########################################################################
+tx_retime 18[6] 1 clkout1=1, clkout2=0
+qi_order 18[5] 0 iq, qi
+inv_txsync 18[4] 0
+tx_twos_comp 18[3] 0
+inverse_samp 18[2] 0 rise, fall
+edges 18[1] 0 normal, both
+interleaved 18[0] 0 single, interleaved
+########################################################################
+## TX Digital
+########################################################################
+two_data_paths 19[4] 0 single, both
+tx_keep_ve 19[3] 0 pass_pos, pass_neg
+tx_hilbert 19[2] 0 dis, enb
+interp 19[0:1] 0 1, 2, 4
+########################################################################
+## TX Modulator
+########################################################################
+neg_fine_tune 20[5] 0 pos_shift, neg_shift
+fine_mode 20[4] 0 bypass, nco
+real_mix_mode 20[3] 0 complex, real
+neg_coarse_tune 20[2] 0 pos_shift, neg_shift
+coarse_mod 20[0:1] 0 bypass, fdac_4, fdac_8
+########################################################################
+## NCO Tuning Word
+########################################################################
+ftw_7_0 21[0:7] 0
+ftw_15_8 22[0:7] 0
+ftw_23_16 23[0:7] 0
+########################################################################
+## DLL
+########################################################################
+input_clk_ctrl 24[6] 0 internal, external
+adc_div2 24[5] 0 normal, div2
+dll_mult 24[3:4] 0 1, 2, 4
+dll_pd 24[2] 0
+dll_mode 24[0] 0 slow, fast
+########################################################################
+## Clock Out
+########################################################################
+clkout2_div_factor 25[6:7] 0 1, 2, 4, 8
+inv2 25[5] 0 normal, inverted
+inv1 25[1] 0 normal, inverted
+dis2 25[4] 0 enb, dis
+dis1 25[0] 0 enb, dis
+########################################################################
+## Aux ADC
+########################################################################
+#for $x, $i in (('a2', 26), ('a1', 28), ('b2', 30), ('b1', 32))
+aux_adc_$(x)_1_0 $(i)[6:7] 0
+aux_adc_$(x)_9_2 $int(1+$i)[0:7] 0
+#end for
+########################################################################
+## Aux ADC Control
+########################################################################
+aux_spi 34[7] 0 dis, enb
+sel_bnota 34[6] 0 adc_a, adc_b
+#for $x, $i in (('b', 5), ('a', 2))
+refsel_$(x) 34[$i] 0 external, internal
+select_$(x) 34[$int($i-1)] 0 aux_adc2, aux_adc1
+start_$(x) 34[$int($i-2)] 0
+#end for
+########################################################################
+## Aux ADC Clock
+########################################################################
+clk_4 35[0] 0 1_2, 1_4
+########################################################################
+## Aux DAC
+########################################################################
+#for $x, $i in (('a', 36), ('b', 37), ('c', 38))
+aux_dac_$x $(i)[0:7] 0
+#end for
+########################################################################
+## Aux DAC Update
+########################################################################
+aux_dac_slave_enable 39[7] 0
+aux_dacupdate_c 39[2] 0
+aux_dacupdate_b 39[1] 0
+aux_dacupdate_a 39[0] 0
+########################################################################
+## AUX DAC Power Down
+########################################################################
+aux_dac_pd_a 40[2] 0
+aux_dac_pd_b 40[1] 0
+aux_dac_pd_c 40[0] 0
+########################################################################
+## AUX DAC Control
+########################################################################
+aux_dac_invert_a 41[2] 0
+aux_dac_invert_b 41[1] 0
+aux_dac_invert_c 41[0] 0
+########################################################################
+## Sig Delt
+########################################################################
+sig_delt_3_0 42[4:7] 0
+sig_delt_11_4 43[0:7] 0
+########################################################################
+## ADC Low Power
+########################################################################
+rx_low_power_mode_r49 49[0:7] 0
+rx_low_power_mode_r50 50[0:7] 0
+########################################################################
+## Chip ID
+########################################################################
+chip_id 63[0:7] 0
+"""
+
+########################################################################
+# Header and Source templates below
+########################################################################
+BODY_TMPL="""
+boost::uint8_t get_reg(boost::uint8_t addr){
+ boost::uint8_t reg = 0;
+ switch(addr){
+ #for $addr in range(0, 63+1)
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint16_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return reg;
+}
+
+void set_reg(boost::uint8_t addr, boost::uint16_t reg){
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask());
+ #end for
+ break;
+ #end for
+ }
+}
+
+boost::uint16_t get_write_reg(boost::uint8_t addr){
+ return (boost::uint16_t(addr) << 8) | get_reg(addr);
+}
+
+boost::uint16_t get_read_reg(boost::uint8_t addr){
+ return (boost::uint16_t(addr) << 8) | (1 << 15);
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='ad9862_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_adf4350_regs.py b/host/lib/ic_reg_maps/gen_adf4350_regs.py
new file mode 100755
index 000000000..e97772843
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_adf4350_regs.py
@@ -0,0 +1,121 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+########################################################################
+## address 0
+########################################################################
+frac_12_bit 0[3:14] 0
+int_16_bit 0[15:30] 0x23
+##reserved 0[31] 0
+########################################################################
+## address 1
+########################################################################
+mod_12_bit 1[3:14] 0xfff
+phase_12_bit 1[15:26] 0
+prescaler 1[27] 0 4_5, 8_9
+##reserved 1[28:31] 0
+########################################################################
+## address 2
+########################################################################
+counter_reset 2[3] 0 disabled, enabled
+cp_three_state 2[4] 0 disabled, enabled
+power_down 2[5] 0 disabled, enabled
+pd_polarity 2[6] 1 negative, positive
+ldp 2[7] 0 10ns, 6ns
+ldf 2[8] 0 frac_n, int_n
+#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16)))
+charge_pump_current 2[9:12] 5 $current_setting_enums
+double_buffer 2[13] 0 disabled, enabled
+r_counter_10_bit 2[14:23] 0
+reference_divide_by_2 2[24] 1 disabled, enabled
+reference_doubler 2[25] 0 disabled, enabled
+muxout 2[26:28] 1 3state, dvdd, dgnd, rdiv, ndiv, analog_ld, dld, reserved
+low_noise_and_spur 2[29:30] 3 low_noise, reserved0, reserved1, low_spur
+########################################################################
+## address 3
+########################################################################
+clock_divider_12_bit 3[3:14] 0
+clock_div_mode 3[15:16] 0 clock_divider_off, fast_lock, resync_enable, reserved
+##reserved 3[17] 0
+cycle_slip_reduction 3[18] 0 disabled, enabled
+##reserved 3[19:20] 0
+##reserved 3[21:31] 0
+########################################################################
+## address 4
+########################################################################
+output_power 4[3:4] 3 m4dbm, m1dbm, 2dbm, 5dbm
+rf_output_enable 4[5] 1 disabled, enabled
+aux_output_power 4[6:7] 0 m4dbm, m1dbm, 2dbm, 5dbm
+aux_output_enable 4[8] 0 disabled, enabled
+aux_output_select 4[9] 1 divided, fundamental
+mute_till_lock_detect 4[10] 0 mute_disabled, mute_enabled
+vco_power_down 4[11] 0 vco_powered_up, vco_powered_down
+band_select_clock_div 4[12:19] 0
+rf_divider_select 4[20:22] 0 div1, div2, div4, div8, div16
+feedback_select 4[23] 1 divided, fundamental
+##reserved 4[24:31] 0
+########################################################################
+## address 5
+########################################################################
+##reserved 5[3:18] 0
+##reserved 5[19:20] 0
+##reserved 5[21] 0
+ld_pin_mode 5[22:23] 1 low0, dld, low, high
+##reserved 5[24:31] 0
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+enum addr_t{
+ ADDR_R0 = 0,
+ ADDR_R1 = 1,
+ ADDR_R2 = 2,
+ ADDR_R3 = 3,
+ ADDR_R4 = 4,
+ ADDR_R5 = 5
+};
+
+boost::uint32_t get_reg(boost::uint8_t addr){
+ boost::uint32_t reg = addr & 0x7;
+ switch(addr){
+ #for $addr in range(5+1)
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return reg;
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='adf4350_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_adf4360_regs.py b/host/lib/ic_reg_maps/gen_adf4360_regs.py
new file mode 100755
index 000000000..3fd8707a7
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_adf4360_regs.py
@@ -0,0 +1,89 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+########################################################################
+## address 0
+########################################################################
+core_power_level 0[2:3] 0 5ma, 10ma, 15ma, 20ma
+counter_operation 0[4] 0 normal, reset
+muxout_control 0[5:7] 0 3state, dld, ndiv, dvdd, rdiv, nchan_od_ld, sdo, dgnd
+phase_detector_polarity 0[8] 0 neg, pos
+charge_pump_output 0[9] 0 normal, 3state
+cp_gain_0 0[10] 0 set1, set2
+mute_till_ld 0[11] 0 dis, enb
+output_power_level 0[12:13] 0 3_5ma, 5_0ma, 7_5ma, 11_0ma
+#set $current_setting_enums = ', '.join(map(lambda x: x+"ma", "0_31 0_62 0_93 1_25 1_56 1_87 2_18 2_50".split()))
+current_setting1 0[14:16] 0 $current_setting_enums
+current_setting2 0[17:19] 0 $current_setting_enums
+power_down 0[20:21] 0 normal_op=0, async_pd=1, sync_pd=3
+prescaler_value 0[22:23] 0 8_9, 16_17, 32_33
+########################################################################
+## address 2
+########################################################################
+a_counter 2[2:6] 0
+b_counter 2[8:20] 0
+cp_gain_1 2[21] 0 set1, set2
+divide_by_2_output 2[22] 0 fund, div2
+divide_by_2_prescaler 2[23] 0 fund, div2
+########################################################################
+## address 1
+########################################################################
+r_counter 1[2:15] 0
+ablpw 1[16:17] 0 3_0ns, 1_3ns, 6_0ns
+lock_detect_precision 1[18] 0 3cycles, 5cycles
+test_mode_bit 1[19] 0
+band_select_clock_div 1[20:21] 0 1, 2, 4, 8
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+enum addr_t{
+ ADDR_CONTROL = 0,
+ ADDR_NCOUNTER = 2,
+ ADDR_RCOUNTER = 1
+};
+
+boost::uint32_t get_reg(addr_t addr){
+ boost::uint32_t reg = addr & 0x3;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return reg;
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='adf4360_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_ads62p44_regs.py b/host/lib/ic_reg_maps/gen_ads62p44_regs.py
new file mode 100755
index 000000000..f0a84d940
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_ads62p44_regs.py
@@ -0,0 +1,124 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+########################################################################
+## address 0
+########################################################################
+reset 0[1] 0
+serial_readout 0[0] 0
+########################################################################
+## address 16
+########################################################################
+clkout_strength 16[6:7] 0 weaker=1, default=0, stronger=3
+########################################################################
+## address 17
+########################################################################
+dataout_strength 17[0:1] 0 weaker=1, default=0, stronger=3, maximum=2
+lvds_current 17[2:3] 0 3_5ma, 2_5ma, 4_5ma, 1_75ma
+lvds_current_double 17[4:5] 0 default, dblclk, dbldataclock
+########################################################################
+## address 18
+########################################################################
+lvds_clk_term 18[0:2] 0 none, 300, 180, 110, 150, 100, 81, 60
+lvds_data_term 18[3:5] 0 none, 300, 180, 110, 150, 100, 81, 60
+########################################################################
+## address 19
+########################################################################
+offset_freeze 19[4] 0
+########################################################################
+## address 20
+########################################################################
+power_down 20[0:2] 0 normal, a_dis, b_dis, ab_dis, global_pd, a_sby, b_sby, mux
+ref_select 20[3] 0 internal, external
+coarse_gain 20[4] 0 0db, 3_5db
+output_interface 20[5] 0 cmos, lvds
+override 20[7] 0
+########################################################################
+## address 22
+########################################################################
+test_patterns 22[0:2] 0 normal, zeros, ones, toggle, ramp, custom
+lvds_bytewise 22[3] 0
+data_format 22[4] 0 twos_complement, binary
+########################################################################
+## address 23
+########################################################################
+fine_gain 23[0:3] 0
+########################################################################
+## address 24 and 25
+########################################################################
+custom_low 24[0:7] 0
+custom_high 25[0:5] 0
+########################################################################
+## address 26
+########################################################################
+gain_correction 26[0:3] 0
+offset_tc 26[4:6] 0 1_1s, 0_55s, 0_27s, 0_13s, 2_15s, 4_3s
+low_latency 26[7] 0
+########################################################################
+## address 27
+########################################################################
+decimation 27[0:2] 0 decimate_2, decimate_4, decimate_1, decimate_8
+odd_tap_enable 27[3] 0
+filter_enable 27[4] 0
+filter_coeff_sel 27[5] 0 predefined, userdefined
+offset_enable 27[7] 0
+########################################################################
+## address 29
+########################################################################
+decimation_filter_bands 29[0:1] 0
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint8_t get_reg(boost::uint8_t addr){
+ boost::uint8_t reg = 0;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return reg;
+}
+
+boost::uint16_t get_write_reg(boost::uint8_t addr){
+ return (boost::uint16_t(addr) << 8) | get_reg(addr);
+}
+
+boost::uint16_t get_read_reg(boost::uint8_t addr){
+ return (boost::uint16_t(addr) << 8) | (1 << 7);
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='ads62p44_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_max2112_regs.py b/host/lib/ic_reg_maps/gen_max2112_regs.py
new file mode 100755
index 000000000..c2fc4e3e2
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_max2112_regs.py
@@ -0,0 +1,181 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing write registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+WRITE_REGS_TMPL="""\
+########################################################################
+## Note: offsets given from perspective of data bits (excludes address)
+########################################################################
+##
+########################################################################
+## N-Divider MSB (0) Write
+########################################################################
+frac 0[7] 1 invalid, frac
+n_divider_msb 0[0:6] 0
+########################################################################
+## N-Divider LSB (1) Write
+########################################################################
+n_divider_lsb 1[0:7] 0x23
+~n_divider n_divider_lsb, n_divider_msb
+########################################################################
+## Charge Pump (2) Write
+########################################################################
+cpmp 2[6:7] 0
+cplin 2[4:5] 1
+f_divider_mmsb 2[0:3] 0x2
+########################################################################
+## F-Divider MSB (3) Write
+########################################################################
+f_divider_msb 3[0:7] 0xF6
+########################################################################
+## F-Divider LSB (4) Write
+########################################################################
+f_divider_lsb 4[0:7] 0x84
+~f_divider f_divider_lsb, f_divider_msb, f_divider_mmsb
+########################################################################
+## XTAL-Divider R-Divider (5) Write
+########################################################################
+#set $xtal_divider_names = ', '.join(map(lambda x: 'div' + str(x), range(1,9)))
+xtal_divider 5[5:7] 0 $xtal_divider_names
+r_divider 5[0:4] 1
+########################################################################
+## PLL (6) Write
+########################################################################
+d24 6[7] 1 div2, div4 ## div2 for LO <= 1125M, div4 > 1125M
+cps 6[6] 1 i_cp_from_icp, i_cp_from_vas
+icp 6[5] 0 i_cp_600ua, i_cp_1200ua
+##reserved 6[0:4] 0
+########################################################################
+## VCO (7) Write
+########################################################################
+vco 7[3:7] 0x19
+vas 7[2] 1 disabled, enabled
+adl 7[1] 1 disabled, enabled
+ade 7[0] 1 disabled, enabled
+########################################################################
+## LPF (8) Write
+########################################################################
+lp 8[0:7] 0x4B ## map(lambda x: "%0.2f"%((4e6 + (x - 12) * 290e3)/1e6), range(255)) in MHz
+########################################################################
+## Control (9) Write
+########################################################################
+stby 9[7] 0 normal, disable_sig_and_synth
+##reserved 9[6] 0
+pwdn 9[5] 0 normal, invalid
+##reserved 9[4] 0
+bbg 9[0:3] 0 ## Baseband Gain in dB
+########################################################################
+## Shutdown (0xA) Write
+########################################################################
+##reserved 0xA[7] 0
+pll_shutdown 0xA[6] 0 normal, shutdown
+div_shutdown 0xA[5] 0 normal, shutdown
+vco_shutdown 0xA[4] 0 normal, shutdown
+bb_shutdown 0xA[3] 0 normal, shutdown
+rfmix_shutdown 0xA[2] 0 normal, shutdown
+rfvga_shutdown 0xA[1] 0 normal, shutdown
+fe_shutdown 0xA[0] 0 normal, shutdown
+########################################################################
+## Test (0xB) Write
+########################################################################
+cptst 0xB[5:7] 0
+##reserved 0xB[4] 0
+turbo 0xB[3] 1
+ld_mux 0xB[0:2] 0 refout=0, invalid
+"""
+
+########################################################################
+# Template for raw text data describing read registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+READ_REGS_TMPL="""\
+########################################################################
+## Status Byte-1 (0xC) Read
+########################################################################
+por 0xC[7] 0 read, reset
+vasa 0xC[6] 0 vas_fail, vas_win
+vase 0xC[5] 0 active, inactive
+ld 0xC[4] 0 unlocked, locked
+##reserved 0xC[0:3] 0
+########################################################################
+## Status Byte-2 (0xD) Read
+########################################################################
+vcosbr 0xD[3:7] 0 ## vco band readback
+adc 0xD[0:2] 0 ool0, lock0, vaslock0, vaslock1, vaslock2, vaslock3, lock1, ool1
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint8_t get_reg(boost::uint8_t addr){
+ boost::uint8_t reg = 0;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return boost::uint8_t(reg);
+}
+
+void set_reg(boost::uint8_t addr, boost::uint8_t reg){
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask());
+ #end for
+ break;
+ #end for
+ }
+}
+"""
+
+SPLIT_REGS_HELPER_TMPL="""\
+#for $divname in ['n','f']
+void set_$(divname)_divider(boost::uint32_t $divname){
+ #for $regname in sorted(map(lambda r: r.get_name(), filter(lambda r: r.get_name().find(divname + '_divider') == 0, $regs)))
+ #end for
+}
+#end for
+"""
+ #$regname = boost::uint8_t($divname & $regs[regname].get_mask());
+ #$divname = boost::uint32_t($divname >> $regs[regname].get_shift());
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='max2112_write_regs',
+ regs_tmpl=WRITE_REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
+
+ import common; common.generate(
+ name='max2112_read_regs',
+ regs_tmpl=READ_REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ append=True,
+ )
diff --git a/host/lib/ic_reg_maps/gen_max2118_regs.py b/host/lib/ic_reg_maps/gen_max2118_regs.py
new file mode 100755
index 000000000..506fbaec8
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_max2118_regs.py
@@ -0,0 +1,126 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing write registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+WRITE_REGS_TMPL="""\
+########################################################################
+## Note: offsets given from perspective of data bits (excludes address)
+########################################################################
+##
+########################################################################
+## N-Divider MSB (0) Write
+########################################################################
+div2 0[7] 0 div4, div2
+n_divider_msb 0[0:6] 3
+########################################################################
+## N-Divider LSB (1) Write
+########################################################################
+n_divider_lsb 1[0:7] 0xB6
+~n_divider n_divider_lsb, n_divider_msb
+########################################################################
+## R, Charge Pump, and VCO (2) Write
+########################################################################
+#set $r_divider_names = ', '.join(map(lambda x: 'div' + str(2**(x+1)), range(0,8)))
+r_divider 2[5:7] 1 $r_divider_names
+#set $cp_current_bias = ', '.join(map(lambda x: 'i_cp_%dua'%(50*2**x), range(0,4)))
+cp_current 2[3:4] 3 $cp_current_bias
+osc_band 2[0:2] 5
+########################################################################
+## I/Q Filter DAC (3) Write
+########################################################################
+##unused 3[7] 0
+f_dac 3[0:6] 0x7F ## filter tuning dac, depends on m
+########################################################################
+## LPF Divider DAC (4) Write
+########################################################################
+adl_vco_adc_latch 4[7] 0 disabled, enabled
+ade_vco_ade_read 4[6] 0 disabled, enabled
+dl_output_drive 4[5] 0 iq_590m_vpp, iq_1_vpp
+m_divider 4[0:4] 2 ## filter tuning counter
+########################################################################
+## GC2 and Diag (5) Write
+########################################################################
+diag 5[5:7] 0 normal, cp_i_source, cp_i_sink, cp_high_z, unused, n_and_filt, r_and_gc2, m_div
+gc2 5[0:4] 0x1F ## Step Size: 0-1: 0dB, 2-22: 1dB, 23-31: 0.5dB
+"""
+
+########################################################################
+# Template for raw text data describing read registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+READ_REGS_TMPL="""\
+########################################################################
+## Status (0) Read
+########################################################################
+pwr 0[6] 0 not_reset, reset
+adc 0[2:4] 0 ## VCO tuning voltage, Lock Status
+########################################################################
+## I/Q Filter DAC (1) Read
+########################################################################
+filter_dac 1[0:6] 0 ## I/Q Filter tuning DAC, current
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint8_t get_reg(boost::uint8_t addr){
+ boost::uint8_t reg = 0;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return boost::uint8_t(reg);
+}
+
+void set_reg(boost::uint8_t addr, boost::uint8_t reg){
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask());
+ #end for
+ break;
+ #end for
+ }
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='max2118_write_regs',
+ regs_tmpl=WRITE_REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
+
+ import common; common.generate(
+ name='max2118_read_regs',
+ regs_tmpl=READ_REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ append=True,
+ )
diff --git a/host/lib/ic_reg_maps/gen_max2829_regs.py b/host/lib/ic_reg_maps/gen_max2829_regs.py
new file mode 100755
index 000000000..383131c18
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_max2829_regs.py
@@ -0,0 +1,133 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+########################################################################
+## Note: offsets given from perspective of data bits (excludes address)
+########################################################################
+##
+########################################################################
+## Standby (2)
+########################################################################
+_set_to_1_2_0 2[0] 1
+_set_to_1_2_1 2[1] 1
+_set_to_1_2_2 2[2] 1
+pa_bias_dac 2[10] 0
+voltage_ref 2[11] 0
+_set_to_1_2_12 2[12] 1
+mimo_select 2[13] 0 normal, mimo
+########################################################################
+## Integer Divider Ratio (3)
+########################################################################
+int_div_ratio_word 3[0:7] 0xa2
+frac_div_ratio_lsb 3[12:13] 0
+########################################################################
+## Fractional Divider Ratio (4)
+########################################################################
+frac_div_ratio_msb 4[0:13] 0
+########################################################################
+## Band Select and PLL (5)
+########################################################################
+band_select 5[0] 0 2_4ghz, 5ghz
+ref_divider 5[1:3] 1
+pll_cp_select 5[5] 1 2ma, 4ma
+band_select_802_11a 5[6] 0 4_9ghz_to_5_35ghz, 5_47ghz_to_5_875ghz
+vco_bandswitch 5[7] 0 disable, automatic
+vco_spi_bandswitch 5[8] 0 fsm, spi
+vco_sub_band 5[9:10] 0
+_set_to_1_5_11 5[11] 1
+_set_to_1_5_12 5[12] 1
+band_sel_mimo 5[13] 0 normal, mimo
+########################################################################
+## Calibration (6)
+########################################################################
+rx_cal_mode 6[0] 0 dis, enb
+tx_cal_mode 6[1] 0 dis, enb
+_set_to_1_6_10 6[10] 1
+iq_cal_gain 6[11:12] 3 8db, 18db, 24db, 34db
+########################################################################
+## Lowpass Filter (7)
+########################################################################
+rx_lpf_fine_adj 7[0:2] 2 90, 95, 100, 105, 110
+rx_lpf_coarse_adj 7[3:4] 1 7_5mhz, 9_5mhz, 14mhz, 18mhz
+tx_lpf_coarse_adj 7[5:6] 1 12mhz=1, 18mhz=2, 24mhz=3
+rssi_high_bw 7[11] 0 2mhz, 6mhz
+########################################################################
+## Rx Control/RSSI (8)
+########################################################################
+_set_to_1_8_0 8[0] 1
+rx_highpass 8[2] 1 100hz, 30khz
+_set_to_1_8_5 8[5] 1
+rssi_pin_fcn 8[8] 0 rssi, temp
+rssi_op_mode 8[10] 0 rssi_rxhp, enabled
+rssi_output_range 8[11] 0 low, high
+rx_vga_gain_spi 8[12] 0 io, spi
+########################################################################
+## Tx Linearity/Baseband Gain (9)
+########################################################################
+tx_baseband_gain 9[0:1] 0 0db, 2db, 3_5db, 5db
+tx_upconv_linearity 9[2:3] 0 50, 63, 78, 100
+tx_vga_linearity 9[6:7] 0 50, 63, 78, 100
+pa_driver_linearity 9[8:9] 2 50, 63, 78, 100
+tx_vga_gain_spi 9[10] 0 io, spi
+########################################################################
+## PA Bias DAC (10)
+########################################################################
+pa_bias_dac_out_curr 10[0:5] 0
+pa_bias_dac_delay 10[6:9] 0xf
+########################################################################
+## Rx Gain (11)
+########################################################################
+rx_vga_gain 11[0:4] 0x1f
+rx_lna_gain 11[5:6] 3
+########################################################################
+## Tx VGA Gain (12)
+########################################################################
+tx_vga_gain 12[0:5] 0
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint32_t get_reg(boost::uint8_t addr){
+ boost::uint16_t reg = 0;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint16_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return (boost::uint32_t(reg) << 4) | (addr & 0xf);
+}
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='max2829_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
diff --git a/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py b/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py
new file mode 100644
index 000000000..73f7aa3db
--- /dev/null
+++ b/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py
@@ -0,0 +1,75 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# Template for raw text data describing registers
+# name addr[bit range inclusive] default optional enums
+########################################################################
+REGS_TMPL="""\
+########################################################################
+## Note: offsets given from perspective of data bits (excludes address)
+########################################################################
+## Divider byte 1
+########################################################################
+db1 0[0:6] 0x00
+########################################################################
+## Divider byte 2
+########################################################################
+db2 1[0:7] 0x00
+########################################################################
+## Control byte 1
+########################################################################
+cb7 2[7] 0x01
+cp 2[6] 0x00 low,high
+os 2[0] 0x00 on,off
+rs 2[1:2] 0x00 d512=3,d640=0,d1024=1
+test 2[3:5] 0x01 normal=0x01,cpoff=0x02,cpsink=0x06,cpsrc=0x07,cptest1=0x04,cptest2=0x05
+########################################################################
+## Control byte 2
+########################################################################
+bandsel 3[4:7] 0x03 uhf=0x03,vhfhi=0x09,vhflo=0x0a
+power 3[3] 0x00 on,off
+"""
+
+########################################################################
+# Template for methods in the body of the struct
+########################################################################
+BODY_TMPL="""\
+boost::uint8_t get_reg(boost::uint8_t addr){
+ boost::uint8_t reg = 0;
+ switch(addr){
+ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
+ case $addr:
+ #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
+ reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
+ #end for
+ break;
+ #end for
+ }
+ return boost::uint8_t(reg);
+}
+
+"""
+
+if __name__ == '__main__':
+ import common; common.generate(
+ name='tuner_4937di5_regs',
+ regs_tmpl=REGS_TMPL,
+ body_tmpl=BODY_TMPL,
+ file=__file__,
+ )
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 19:26:12 +0000