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Diffstat (limited to 'host/docs')
| -rw-r--r-- | host/docs/usrp_e3x0.dox | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/host/docs/usrp_e3x0.dox b/host/docs/usrp_e3x0.dox index 3a56f70fb..f93326bee 100644 --- a/host/docs/usrp_e3x0.dox +++ b/host/docs/usrp_e3x0.dox @@ -274,8 +274,18 @@ You may need to change the USRP's IP address for several reasons: - **USB**: USB 2.0 Port - **SERIAL**: Micro USB connection for serial uart console +\subsection e3x0_hw_sync Clock and Time Synchronization +Unlike most USRP devices, the E310 does not have independent reference clock and time source inputs. +It is possible, however, to discipline the internal reference clock using an external time (PPS) source +connected to the SYNC input pin. The E310 FPGA has a subsystem that can use the PPS signal from the +SYNC pin or the internal GPS to align edges of the reference clock to edges of a shared PPS signal. +This alignment happens automatically when the time source in UHD is set to "gpsdo" or "external". +Please note that because the SYNC input can only accept a PPS signal, the only supported value for +the reference clock source is "internal". + + \subsection e3x0_hw_pps PPS - Pulse Per Second -Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude. +Using a PPS signal for timestamp synchronization requires a LVCMOS or a 5V logic input signal. An external PPS can be used to discipline the internal reference clock. This feature is automatically enabled with the time source is set to "external". |