4 files changed, 93 insertions, 4 deletions
diff --git a/host/docs/CMakeLists.txt b/host/docs/CMakeLists.txt
index cba97218a..17744db7d 100644
--- a/host/docs/CMakeLists.txt
+++ b/host/docs/CMakeLists.txt
@@ -34,6 +34,7 @@ SET(manual_sources
     usrp1.rst
     usrp2.rst
     usrp_b100.rst
+    usrp_b200.rst
     usrp_e1x0.rst
 )
 
diff --git a/host/docs/index.rst b/host/docs/index.rst
index 5e3d08fb4..27523c139 100644
--- a/host/docs/index.rst
+++ b/host/docs/index.rst
@@ -27,6 +27,7 @@ Application Notes
 * `USRP2 Application Notes <./usrp2.html>`_
 * `USRP-N2X0 Series Application Notes <./usrp2.html>`_
 * `USRP-B100 Series Application Notes <./usrp_b100.html>`_
+* `USRP-B2X0 Series Application Notes <./usrp_b200.html>`_
 * `USRP-E1X0 Series Application Notes <./usrp_e1x0.html>`_
 * `Daughterboard Application Notes <./dboards.html>`_
 * `Transport Application Notes <./transport.html>`_
diff --git a/host/docs/usrp_b100.rst b/host/docs/usrp_b100.rst
index b5dc79b50..ac0942f5c 100644
--- a/host/docs/usrp_b100.rst
+++ b/host/docs/usrp_b100.rst
@@ -21,23 +21,23 @@ Comparative features list
 ------------------------------------------------------------------------
 Specify a Non-standard Image
 ------------------------------------------------------------------------
-UHD software will automatically select the USRP B-Series images from the installed images package.
+UHD software will automatically select the USRP B100 images from the installed images package.
 The image selection can be overridden with the **--fpga=** and **--fw=** device address parameters.
 
 Example device address string representations to specify non-standard images:
 
 ::
 
-    fpga=usrp_b100_fpga_firmware.bin
+    fpga=usrp_b100_fpga_2rx.bin
 
     -- OR --
 
-    fw=usrp_b100_fw_firmware.ihx
+    fw=usrp_b100_fw.ihx
 
 ------------------------------------------------------------------------
 Changing the Master Clock Rate
 ------------------------------------------------------------------------
-The master clock rate of the USRP embedded feeds both the FPGA DSP and the codec chip.
+The master clock rate of the B100 feeds both the FPGA DSP and the codec chip.
 Hundreds of rates between 32MHz and 64MHz are available.
 A few notable rates are:
 
diff --git a/host/docs/usrp_b200.rst b/host/docs/usrp_b200.rst
new file mode 100644
index 000000000..96bf9b5bc
--- /dev/null
+++ b/host/docs/usrp_b200.rst
@@ -0,0 +1,87 @@
+========================================================================
+UHD - USRP-B2X0 Series Application Notes
+========================================================================
+
+.. contents:: Table of Contents
+
+------------------------------------------------------------------------
+Comparative features list - B200
+------------------------------------------------------------------------
+
+* integrated RF frontend
+* 1 RX DDC chain in FPGA
+* 1 TX DUC chain in FPGA
+* Timed commands in FPGA
+* Timed sampling in FPGA
+* External PPS reference
+* External 10MHz reference
+* Configurable clock rate
+* Internal GPSDO option
+
+------------------------------------------------------------------------
+Comparative features list - B210
+------------------------------------------------------------------------
+
+* integrated MIMO frontend
+* 2 RX DDC chains in FPGA
+* 2 TX DUC chains in FPGA
+* Timed commands in FPGA
+* Timed sampling in FPGA
+* External PPS reference
+* External 10MHz reference
+* Configurable clock rate
+* Internal GPSDO option
+
+------------------------------------------------------------------------
+Specify a Non-standard Image
+------------------------------------------------------------------------
+UHD software will automatically select the USRP B2X0 images from the installed images package.
+The image selection can be overridden with the **--fpga=** and **--fw=** device address parameters.
+
+Example device address string representations to specify non-standard images:
+
+::
+
+    fpga=usrp_b200_fpga.bin
+
+    -- OR --
+
+    fw=usrp_b200_fw.hex
+
+------------------------------------------------------------------------
+Changing the Master Clock Rate
+------------------------------------------------------------------------
+The master clock rate feeds the RF frontends and the DSP chains.
+Users may select non-default clock rates to acheive integer decimations or interpolations in the DSP chains.
+The default master clock rate defaults to 32 MHz, but can be set to any rate between 220 kHz and 61.44 MHz.
+
+The user can set the master clock rate through the usrp API call set_master_clock_rate(),
+or the clock rate can be set through the device arguments, which many applications take:
+::
+
+    uhd_usrp_probe --args="master_clock_rate=52e6"
+
+------------------------------------------------------------------------
+RF Frontend Notes
+------------------------------------------------------------------------
+The B200 features and integrated RF frontend.
+
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Frontend tuning
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The RF frontend has individually tunable receive and transmit chains.
+On the B200, there is one transmit and one receive RF frontend.
+On the B210, both transmit and receive can be used in a MIMO configuration.
+For the MIMO case, both receive frontends share the RX LO,
+and both transmit frontends share the TX LO.
+Each LO is tunable between 50 MHz and 6 GHz.
+
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Frontend gain
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+All frontends have individual analog gain controls.
+The receive frontends have 73 dB of available gain;
+and the transmit frontends have 89 dB of available gain.
+Gain settings are application specific,
+but its recommended that users consider using at least
+half of the available gain to get reasonable dynamic range.