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-rw-r--r--host/docs/octoclock.dox34
-rw-r--r--host/docs/sync.dox6
-rw-r--r--host/docs/uhd_find_devices.12
-rw-r--r--host/docs/uhd_usrp_probe.13
-rw-r--r--host/docs/usrp_b200.dox36
5 files changed, 58 insertions, 23 deletions
diff --git a/host/docs/octoclock.dox b/host/docs/octoclock.dox
index 9c1ca7b47..45a12e93a 100644
--- a/host/docs/octoclock.dox
+++ b/host/docs/octoclock.dox
@@ -29,14 +29,15 @@ schematics</a>. Once you verify that the programmer is properly connected, run t
cd <install path>/share/uhd/images
avrdude -p atmega128 -c <programmer name> -P usb -U efuse:w:0xFF:m -U hfuse:w:0x80:m -U lfuse:w:0xFF:m -U flash:w:octoclock_bootloader.hex:i
-**Note:** On Linux, **sudo** must be used with the **avrdude** command.
+\b Note:
+On Linux, `sudo avrdude ...` might be necessary to gain access to the programmer.
Once the bootloader has been burned, power-cycle your OctoClock device and refer to the below instructions on burning the OctoClock's
primary firmware.
\subsection application Primary Octoclock firmware
-To load firmware onto the OctoClock, you must use the *octoclock_firmware_burner* utility, specifying the IP
+To load firmware onto the OctoClock, you must use the `octoclock_firmware_burner` utility, specifying the IP
address of the OctoClock device, as follows:
octoclock_firmware_burner --addr=192.168.10.3
@@ -45,12 +46,13 @@ address of the OctoClock device, as follows:
\subsection host_interface Setting up the host interface
-The OctoClock communicates with the host machine at the UDP layer over Gigabit Ethernet. The default device
-of the OctoClock is **192.168.10.3**. You will need to configure the host machine's Ethernet interface with
-a static IP address to enable communication. An address of **192.168.10.1** and a subnet mask of
-**255.255.255.0** is recommended.
+The OctoClock communicates with the host machine at the UDP layer over Ethernet. The default device
+of the OctoClock is `192.168.10.3`. You will need to configure the host machine's Ethernet interface with
+a static IP address to enable communication. An address of `192.168.10.1` and a subnet mask of
+`255.255.255.0` is recommended.
-**Note:** When using UHD software, if an IP address for the OctoClock is not specified, the software will
+\b Note:
+When using UHD software, if an IP address for the OctoClock is not specified, the software will
use UDP broadcast packets to locate the OctoClock. On some systems, the firewall will block UDP broadcast
packets. It is recommended that you change your firewall settings.
@@ -110,17 +112,17 @@ The same applies for an external signal.
The following sensors are available on both the OctoClock and Octoclock-G; these can be queried through the
<a href="classuhd_1_1octoclock.html">API</a>.
-- **ext_ref_detected:** whether or not the device detects an external reference
-- **gps_detected:** whether or not the device detects an internal GPSDO
-- **using_ref:** which reference the device is using (internal or external)
-- **switch_pos:** the position of the front switch (internal or external)
+- `ext_ref_detected:` whether or not the device detects an external reference
+- `gps_detected:` whether or not the device detects an internal GPSDO
+- `using_ref:` which reference the device is using (internal or external)
+- `switch_pos:` the position of the front switch (internal or external)
On the OctoClock-G, the following sensors are added:
-- **gps_gpgga:** the latest GPGGA string sent by the GPSDO
-- **gps_gprmc:** the latest GPRMC string sent by the GPSDO
-- **gps_time:** the time reported by the GPSDO
-- **gps_locked:** whether or not the GPSDO is locked (true/false)
-- **gps_servo:** the latest debug trace information sent by the GPSDO
+- `gps_gpgga:` the latest GPGGA string sent by the GPSDO
+- `gps_gprmc:` the latest GPRMC string sent by the GPSDO
+- `gps_time:` the time reported by the GPSDO
+- `gps_locked:` whether or not the GPSDO is locked (true/false)
+- `gps_servo:` the latest debug trace information sent by the GPSDO
*/
diff --git a/host/docs/sync.dox b/host/docs/sync.dox
index 8c16eb046..aaae88702 100644
--- a/host/docs/sync.dox
+++ b/host/docs/sync.dox
@@ -152,7 +152,7 @@ metadata should have a time spec set: :
size_t num_tx_samps = tx_streamer->send(buffs, samps_to_send, md);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-\subsection sync_phase_lo Align LOs in the front-end (SBX, WBX, CBX)
+\subsection sync_phase_lo Align LOs in the front-end (SBX, WBX, UBX)
Using timed commands, multiple frontends can be tuned at a specific
time. This timed-tuning ensures that the phase offsets between VCO/PLL
@@ -161,7 +161,9 @@ chains will remain constant after each re-tune. See notes below:
- There is a random phase offset between any two frontends
- This phase offset is different for different LO frequencies
- This phase offset remains constant after retuning
- - Due to a divider, WBX phase offset will be randomly +/- 180 deg after re-tune
+ - Due to a divider, WBX phase offset will be randomly +/- 180 deg after re-tune on all USRPs.
+ - Due to a divider, UBX phase offset will be randomly +/- 180 deg after re-tune on N200/N210.
+ On X300/X310, phase sync with UBX fully works.
- This phase offset will drift over time due to thermal and other characteristics
- Periodic calibration will be necessary for phase-coherent applications
diff --git a/host/docs/uhd_find_devices.1 b/host/docs/uhd_find_devices.1
index dfd5c0751..a29793872 100644
--- a/host/docs/uhd_find_devices.1
+++ b/host/docs/uhd_find_devices.1
@@ -43,6 +43,8 @@ type=b200 | USRP B200, USRP B210
type=e100 | USRP E100, USRP E110
+type=e3x0 | USRP E310
+
type=x300 | USRP X300, USRP X310
type=octoclock | OctoClock
diff --git a/host/docs/uhd_usrp_probe.1 b/host/docs/uhd_usrp_probe.1
index 178027aea..b5a48fc15 100644
--- a/host/docs/uhd_usrp_probe.1
+++ b/host/docs/uhd_usrp_probe.1
@@ -51,8 +51,11 @@ type=b200 | USRP B200, USRP B210
type=e100 | USRP E100, USRP E110
+type=e3x0 | USRP E310
+
type=x300 | USRP X300, USRP X310
+
.SS Identifying by serial number
All USRP devices are given a unique serial number, which can be used to identify a device as follows:
diff --git a/host/docs/usrp_b200.dox b/host/docs/usrp_b200.dox
index 9d3550b98..1da7f2aee 100644
--- a/host/docs/usrp_b200.dox
+++ b/host/docs/usrp_b200.dox
@@ -9,10 +9,12 @@
- External PPS reference input
- External 10 MHz reference input
- Configurable clock rate
+ - Variable analog bandwidth (200 kHz - 56 MHz)
- Internal GPSDO option (see \subpage page_gpsdo_b2x0 for details)
- B210 Only:
- MICTOR Debug Connector
- JTAG Connector
+ - Revision 6 with GPIO header
- FPGA Capabilities:
- Timed commands in FPGA
- Timed sampling in FPGA
@@ -90,6 +92,24 @@ frontends have 73 dB of available gain; and the transmit frontends have
it is recommended that users consider using at least half of the
available gain to get reasonable dynamic range.
+\subsection b200_fe_bw Frontend bandwidth
+
+The analog frontend has a seamlessly adjustable bandwidth of 200 kHz to 56 MHz.
+
+Generally, when requesting any possible master clock rate, UHD will
+automatically configure the analog filters to avoid any aliasing (RX) or
+out-of-band emissions whilst letting through the cleanest possible signal.
+
+If you, however, happen to have a very strong interferer within half the master
+clock rate of your RX LO frequency, you might want to reduce this analog
+bandwidth. You can do so by calling
+uhd::usrp::multi_usrp::set_rx_bandwidth(bw).
+
+The property to control the analog RX bandwidth is `bandwidth/value`.
+
+UHD will not allow you to set bandwidths larger than your current master clock
+rate.
+
\section Hardware Reference
\subsection LED Indicators
@@ -181,11 +201,17 @@ Below is a table showing the external connections and respective power informati
Below is a table showing the on-board connectors and switches:
-Component ID | Description | Details
---------------|----------------------------|----------------------------------------------------------
- J502* | Mictor Connector | Interface to FPGA for I/O and inspection.
- J503* | JTAG Header | Interface to FPGA for programming and debugging.
- S700 | FX3 Hard Reset Switch | -
+Component ID | Description | Details
+------------------------|----------------------------|---------------------------------------------------
+ J502<sup>1</sup> | Mictor Connector | Interface to FPGA for I/O and inspection.
+ J503<sup>1</sup> | JTAG Header | Interface to FPGA for programming and debugging.
+ J504<sup>2</sup> | GPIO Header | Header running to the FPGA for GPIO purposes.
+ S700 | FX3 Hard Reset Switch | Resets the USB controller / System reset
+ U100 | GPSDO socket | Interface to GPS disciplined reference oscillator
+
+<sup>1</sup> Only on the B210
+
+<sup>2</sup> Only since rev. 6 (green board)
*/
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-06 05:09:28 +0000