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Diffstat (limited to 'host/docs/usrp_b100.rst')
| -rw-r--r-- | host/docs/usrp_b100.rst | 44 |
1 files changed, 25 insertions, 19 deletions
diff --git a/host/docs/usrp_b100.rst b/host/docs/usrp_b100.rst index ac0942f5c..223ad5a90 100644 --- a/host/docs/usrp_b100.rst +++ b/host/docs/usrp_b100.rst @@ -1,5 +1,5 @@ ======================================================================== -UHD - USRP-B100 Series Application Notes +UHD - USRP-B100 Series Device Manual ======================================================================== .. contents:: Table of Contents @@ -8,15 +8,21 @@ UHD - USRP-B100 Series Application Notes Comparative features list ------------------------------------------------------------------------ -* 1 transceiver card slot -* 1 RX DDC chain in FPGA -* 1 TX DUC chain in FPGA -* Timed commands in FPGA -* Timed sampling in FPGA -* External PPS reference -* External 10MHz reference -* Configurable clock rate (defaults 64 MHz) -* sc8 and sc16 sample modes +**Hardware Capabilities:** + * 1 transceiver card slot + * External PPS reference input + * External 10 MHz reference input + * Configurable clock rate (defaults 64 MHz) + +**FPGA Capabilities:** + * 1 RX DDC chain in FPGA + * 1 TX DUC chain in FPGA + * Timed commands in FPGA + * Timed sampling in FPGA + * sc8 and sc16 sample modes + + * Up to 8 MHz of RF BW with 16-bit samples + * Up to 16 MHz of RF BW with 8-bit samples ------------------------------------------------------------------------ Specify a Non-standard Image @@ -38,17 +44,17 @@ Example device address string representations to specify non-standard images: Changing the Master Clock Rate ------------------------------------------------------------------------ The master clock rate of the B100 feeds both the FPGA DSP and the codec chip. -Hundreds of rates between 32MHz and 64MHz are available. +Hundreds of rates between 32 MHz and 64 MHz are available. A few notable rates are: -* **64MHz:** maximum rate of the codec chip -* **61.44MHz:** good for UMTS/WCDMA applications -* **52Mhz:** good for GSM applications +* **64 MHz:** maximum rate of the codec chip +* **61.44 MHz:** good for UMTS/WCDMA applications +* **52 MHz:** good for GSM applications ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set 61.44MHz - uses external VCXO +Set 61.44 MHz - uses external VCXO ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use the 61.44MHz clock rate, the USRP embedded will require one jumper to be moved, +To use the 61.44 MHz clock rate, the USRP embedded will require one jumper to be moved, and X4 must be populated with a 61.44 MHz oscillator. * **J15** is a three pin header, move the jumper to (pin1, pin2) @@ -64,7 +70,7 @@ To use other clock rates, the jumper will need to be in the default position. * **J15** is a three pin header, move the jumper to (pin2, pin3) To communicate the desired clock rate into UHD software, -specify the a special device address argument, +specify the special device address argument, where the key is **master_clock_rate** and the value is a rate in Hz. Example: :: @@ -82,9 +88,9 @@ The LEDs on the front panel can be useful in debugging hardware and software iss The LEDs reveal the following about the state of the device: * **LED A:** transmitting -* **LED B:** fpga loaded +* **LED B:** FPGA loaded * **LED C:** receiving -* **LED D:** fpga loaded +* **LED D:** FPGA loaded * **LED E:** reference lock * **LED F:** board power |