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-rw-r--r--fpga/usrp2/top/E1x0/Makefile.E1101
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110
index c2d3e39e6..e5be8d2fa 100644
--- a/fpga/usrp2/top/E1x0/Makefile.E110
+++ b/fpga/usrp2/top/E1x0/Makefile.E110
@@ -50,6 +50,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \
TOP_SRCS = \
../B100/u1plus_core.v \
E1x0.v \
+E1x0.ucf \
timing.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \