diff options
Diffstat (limited to 'fpga')
31 files changed, 1162 insertions, 688 deletions
diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v index fed2791f9..a161b5e00 100644 --- a/fpga/usrp2/control_lib/atr_controller.v +++ b/fpga/usrp2/control_lib/atr_controller.v @@ -7,7 +7,7 @@ module atr_controller (input clk_i, input rst_i, input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o, input we_i, input stb_i, input cyc_i, output reg ack_o, - input run_rx, input run_tx, input [31:0] master_time, + input run_rx, input run_tx, output [31:0] ctrl_lines); reg [3:0] state; diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v index 3d8b5b1e9..74ce30a54 100644 --- a/fpga/usrp2/control_lib/atr_controller16.v +++ b/fpga/usrp2/control_lib/atr_controller16.v @@ -7,7 +7,7 @@ module atr_controller16 (input clk_i, input rst_i, input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o, input we_i, input stb_i, input cyc_i, output reg ack_o, - input run_rx, input run_tx, input [31:0] master_time, + input run_rx, input run_tx, output [31:0] ctrl_lines); reg [3:0] state; diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v index 668012504..29d21ab5a 100644 --- a/fpga/usrp2/control_lib/bootram.v +++ b/fpga/usrp2/control_lib/bootram.v @@ -6,10 +6,10 @@ module bootram (input clk, input reset, - input [12:0] if_adr, + input [13:0] if_adr, output [31:0] if_data, - input [12:0] dwb_adr_i, + input [13:0] dwb_adr_i, input [31:0] dwb_dat_i, output [31:0] dwb_dat_o, input dwb_we_i, @@ -17,17 +17,23 @@ module bootram input dwb_stb_i, input [3:0] dwb_sel_i); - wire [31:0] DOA0, DOA1, DOA2, DOA3; - wire [31:0] DOB0, DOB1, DOB2, DOB3; - wire ENB0, ENB1, ENB2, ENB3; + wire [31:0] DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7; + wire [31:0] DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7; + wire ENB0, ENB1, ENB2, ENB3, ENB4, ENB5, ENB6, ENB7; wire [3:0] WEB; - reg [1:0] delayed_if_bank; + reg [2:0] delayed_if_bank; always @(posedge clk) - delayed_if_bank <= if_adr[12:11]; + delayed_if_bank <= if_adr[13:11]; - assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0); - assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0); + assign if_data = delayed_if_bank[2] ? + (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA7 : DOA6) : (delayed_if_bank[0] ? DOA5 : DOA4)) + : (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0)); + + + assign dwb_dat_o = dwb_adr_i[13] ? + (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB7 : DOB6) : (dwb_adr_i[11] ? DOB5 : DOB4)) + : (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0)); always @(posedge clk) if(reset) @@ -35,10 +41,14 @@ module bootram else dwb_ack_o <= dwb_stb_i & ~dwb_ack_o; - assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00); - assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01); - assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10); - assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11); + assign ENB0 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b000); + assign ENB1 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b001); + assign ENB2 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b010); + assign ENB3 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b011); + assign ENB4 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b100); + assign ENB5 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b101); + assign ENB6 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b110); + assign ENB7 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b111); assign WEB = {4{dwb_we_i}} & dwb_sel_i; @@ -161,90 +171,125 @@ module bootram .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM4 + (.DOA(DOA4), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input -endmodule // bootram + .DOB(DOB4), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB4), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM5 + (.DOA(DOA5), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input -/* - // The following INIT_xx declarations specify the initial contents of the RAM - // Address 0 to 127 - .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - // Address 128 to 255 - .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - // Address 256 to 383 - .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - // Address 384 to 511 - .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - // The next set of INITP_xx are for the parity bits - // Address 0 to 127 - .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000), - // Address 128 to 255 - .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000), - // Address 256 to 383 - .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000), - // Address 384 to 511 - .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000) -*/ + .DOB(DOB5), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB5), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM6 + (.DOA(DOA6), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB6), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB6), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM7 + (.DOA(DOA7), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB7), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB7), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + +endmodule // bootram diff --git a/fpga/usrp2/control_lib/ram_harvard.v b/fpga/usrp2/control_lib/ram_harvard.v index 948f9b36f..a190e20fd 100644 --- a/fpga/usrp2/control_lib/ram_harvard.v +++ b/fpga/usrp2/control_lib/ram_harvard.v @@ -27,9 +27,7 @@ module ram_harvard input dwb_we_i, output dwb_ack_o, input dwb_stb_i, - input [3:0] dwb_sel_i, - - input flush_icache ); + input [3:0] dwb_sel_i ); reg ack_d1; reg stb_d1; diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v index c2ae8f96c..58455cee1 100644 --- a/fpga/usrp2/fifo/dsp_framer36.v +++ b/fpga/usrp2/fifo/dsp_framer36.v @@ -1,9 +1,13 @@ -// Frame DSP packets with a header line to be handled by the protocol machine +// This has 3 functions: +// Correct the VITA packet length +// [optional] Frame DSP packets with an header line to be handled by the protocol machine +// Hold on to the packet until there is a complete one before allowing to leave module dsp_framer36 #(parameter BUF_SIZE = 9, - parameter PORT_SEL = 0) + parameter PORT_SEL = 0, + parameter PROT_ENG_FLAGS = 1) (input clk, input reset, input clear, input [35:0] data_i, input src_rdy_i, output dst_rdy_o, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); @@ -48,10 +52,10 @@ module dsp_framer36 always @(posedge clk) if(reset | clear) - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else if(do_xfer_out) if(dfifo_out_data[33]) // eof - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else pkt_len_out <= pkt_len_out + 1; @@ -59,8 +63,8 @@ module dsp_framer36 wire [1:0] port_sel_bits = PORT_SEL; - assign data_o = (pkt_len_out == 0) ? {4'b0001, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : - (pkt_len_out == 1) ? {4'b0000, dfifo_out_data[31:16],tfifo_data} : + assign data_o = (pkt_len_out == 0) ? {3'b000, 1'b1, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : + (pkt_len_out == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), dfifo_out_data[31:16],tfifo_data} : {dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] }; assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy; diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v index 7774ff076..04c17b647 100644 --- a/fpga/usrp2/fifo/packet_router.v +++ b/fpga/usrp2/fifo/packet_router.v @@ -251,28 +251,14 @@ module packet_router //////////////////////////////////////////////////////////////////// //dummy signals to connect the components below - wire [18:0] _udp_r2s_data, _udp_s2r_data; - wire _udp_r2s_valid, _udp_s2r_valid; - wire _udp_r2s_ready, _udp_s2r_ready; - wire [35:0] _com_out_data; wire _com_out_valid, _com_out_ready; - fifo36_to_fifo19 udp_fifo36_to_fifo19 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), - .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) ); - prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .datain(_udp_r2s_data), .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready), - .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready) ); - - fifo19_to_fifo36 udp_fifo19_to_fifo36 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), - .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) ); + .datain(udp_out_data), .src_rdy_i(udp_out_valid), .dst_rdy_o(udp_out_ready), + .dataout(_com_out_data), .src_rdy_o(_com_out_valid), .dst_rdy_i(_com_out_ready) ); fifo36_mux com_out_mux( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), diff --git a/fpga/usrp2/models/IOBUF.v b/fpga/usrp2/models/IOBUF.v new file mode 100644 index 000000000..1195dfb17 --- /dev/null +++ b/fpga/usrp2/models/IOBUF.v @@ -0,0 +1,83 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.9 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer +// /___/ /\ Filename : IOBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF (O, IO, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IBUF_DELAY_VALUE = "0"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + output O; + inout IO; + input I, T; + + wire ts; + + //tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + $finish; + end + + endcase + + end // initial begin + +endmodule + diff --git a/fpga/usrp2/opencores/zpu/core/zpu_config.vhd b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd index b7e894232..f7743d602 100644 --- a/fpga/usrp2/opencores/zpu/core/zpu_config.vhd +++ b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd @@ -12,4 +12,9 @@ package zpu_config is constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 15;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"3ff8";
+
end zpu_config;
diff --git a/fpga/usrp2/opencores/zpu/core/zpu_core.vhd b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd index 24586b2f6..2450f14d3 100644 --- a/fpga/usrp2/opencores/zpu/core/zpu_core.vhd +++ b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd @@ -26,7 +26,6 @@ entity zpu_core is mem_write : out std_logic_vector(wordSize-1 downto 0); out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); interrupt : in std_logic; break : out std_logic; zpu_status : out std_logic_vector(63 downto 0)); @@ -203,7 +202,7 @@ begin if areset = '1' then state <= State_Idle; break <= '0'; - sp <= stack_start(maxAddrBitIncIO downto minAddrBit); + sp <= spStart(maxAddrBitIncIO downto minAddrBit); pc <= (others => '0'); idim_flag <= '0'; diff --git a/fpga/usrp2/opencores/zpu/core/zpupkg.vhd b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd index eee967a09..1a01563b8 100644 --- a/fpga/usrp2/opencores/zpu/core/zpupkg.vhd +++ b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd @@ -73,7 +73,6 @@ package zpupkg is mem_write : out std_logic_vector(wordSize-1 downto 0);
out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
- stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
interrupt : in std_logic;
break : out std_logic;
zpu_status : out std_logic_vector(63 downto 0));
diff --git a/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd index 8af678b6a..294651fe2 100644 --- a/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd +++ b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd @@ -51,7 +51,7 @@ entity zpu_system is -- ZPU Control signals
enable : in std_logic;
interrupt : in std_logic;
- stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
+
zpu_status : out std_logic_vector(63 downto 0);
-- wishbone interfaces
@@ -84,7 +84,6 @@ begin mem_write => mem_write,
out_mem_addr => out_mem_addr,
mem_writeMask => mem_writeMask,
- stack_start => stack_start,
interrupt => interrupt,
zpu_status => zpu_status,
break => open);
diff --git a/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd index a158ab9c0..23ff48c39 100644 --- a/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd +++ b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd @@ -35,7 +35,7 @@ package zpu_top_pkg is -- ZPU Control signals enable : in std_logic; interrupt : in std_logic; - stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); + zpu_status : out std_logic_vector(63 downto 0); -- wishbone interfaces diff --git a/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd index 9735c4b54..48e5ee31d 100644 --- a/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd +++ b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd @@ -36,7 +36,6 @@ entity zpu_wb_top is -- misc zpu signals interrupt: in std_logic; - stack_start: in std_logic_vector(adr_w-1 downto 0); zpu_status: out std_logic_vector(63 downto 0) ); @@ -67,7 +66,6 @@ zpu_system0: zpu_system port map( areset => rst, enable => enb, interrupt => interrupt, - stack_start => stack_start, zpu_status => zpu_status, zpu_wb_i => zpu_wb_i, zpu_wb_o => zpu_wb_o diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx.v b/fpga/usrp2/sdr_lib/dsp_core_rx.v index 1318809d6..a315234cf 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_rx.v +++ b/fpga/usrp2/sdr_lib/dsp_core_rx.v @@ -7,8 +7,6 @@ module dsp_core_rx input [13:0] adc_a, input adc_ovf_a, input [13:0] adc_b, input adc_ovf_b, - input [15:0] io_rx, - output [31:0] sample, input run, output strobe, @@ -33,10 +31,6 @@ module dsp_core_rx wire enable_hb1, enable_hb2; wire [7:0] cic_decim_rate; - wire [31:10] UNUSED_1; - wire [31:4] UNUSED_2; - wire [31:2] UNUSED_3; - setting_reg #(.my_addr(BASE+0)) sr_0 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_inc),.changed()); @@ -45,9 +39,9 @@ module dsp_core_rx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({scale_i,scale_q}),.changed()); - setting_reg #(.my_addr(BASE+2)) sr_2 + setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed()); + .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed()); rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -60,12 +54,12 @@ module dsp_core_rx wire [7:0] muxctrl; setting_reg #(.my_addr(BASE+5), .width(8)) sr_8 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({UNUSED_2,muxctrl}),.changed()); + .in(set_data),.out(muxctrl),.changed()); wire [1:0] gpio_ena; setting_reg #(.my_addr(BASE+6), .width(2)) sr_9 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({UNUSED_3,gpio_ena}),.changed()); + .in(set_data),.out(gpio_ena),.changed()); always @(posedge clk) case(muxctrl[3:0]) // The I mapping @@ -153,19 +147,9 @@ module dsp_core_rx round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); - // Streaming GPIO - // - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - reg [31:0] sample_reg; always @(posedge clk) - begin - sample_reg[31:17] <= i_out[15:1]; - sample_reg[15:1] <= q_out[15:1]; - sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; - sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; - end + sample_reg <= {i_out,q_out}; assign sample = sample_reg; assign strobe = strobe_hb2; diff --git a/fpga/usrp2/simple_gemac/Makefile.srcs b/fpga/usrp2/simple_gemac/Makefile.srcs index b82e64208..7bcc58c91 100644 --- a/fpga/usrp2/simple_gemac/Makefile.srcs +++ b/fpga/usrp2/simple_gemac/Makefile.srcs @@ -24,4 +24,6 @@ miim/eth_miim.v \ miim/eth_clockgen.v \ miim/eth_outputcontrol.v \ miim/eth_shiftreg.v \ +ethtx_realign.v \ +ethrx_realign.v \ )) diff --git a/fpga/usrp2/simple_gemac/ethrx_realign.v b/fpga/usrp2/simple_gemac/ethrx_realign.v new file mode 100644 index 000000000..0a369c914 --- /dev/null +++ b/fpga/usrp2/simple_gemac/ethrx_realign.v @@ -0,0 +1,72 @@ + +// NOTE: Will not work with single-line frames + +module ethrx_realign + (input clk, input reset, input clear, + input [35:0] datain, input src_rdy_i, output dst_rdy_o, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i); + + reg [1:0] state; + reg [15:0] held; + reg [1:0] held_occ; + + wire xfer_in = src_rdy_i & dst_rdy_o; + wire xfer_out = src_rdy_o & dst_rdy_i; + + wire sof_in = datain[32]; + wire eof_in = datain[33]; + wire [1:0] occ_in = datain[35:34]; + wire sof_out, eof_out; + wire [1:0] occ_out; + + always @(posedge clk) + if(reset | clear) + begin + held <= 0; + held_occ <= 0; + end + else if(xfer_in) + begin + held <= datain[15:0]; + held_occ <= datain[35:34]; + end + + localparam RE_IDLE = 0; + localparam RE_HELD = 1; + localparam RE_DONE = 2; + + always @(posedge clk) + if(reset | clear) + state <= RE_IDLE; + else + case(state) + RE_IDLE : + if(src_rdy_i & dst_rdy_i) + if(eof_in) + state <= RE_DONE; + else + state <= RE_HELD; + + RE_HELD : + if(src_rdy_i & dst_rdy_i & eof_in) + if((occ_in==0)|(occ_in==3)) + state <= RE_DONE; + else + state <= RE_IDLE; + + RE_DONE : + if(dst_rdy_i) + state <= RE_IDLE; + + endcase // case (state) + + + assign sof_out = (state == RE_IDLE); + assign eof_out = (state == RE_DONE) | (occ_in == 1) | (occ_in == 2); + assign occ_out = (state == RE_DONE) ? ((held_occ == 3) ? 1 : 2) : + (occ_in == 1) ? 3 : 0; + + assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]}; + assign src_rdy_o = (state == RE_DONE) | src_rdy_i; + assign dst_rdy_o = dst_rdy_i & ((state == RE_IDLE)|(state == RE_HELD)); +endmodule // ethrx_realign diff --git a/fpga/usrp2/simple_gemac/ethtx_realign.v b/fpga/usrp2/simple_gemac/ethtx_realign.v new file mode 100644 index 000000000..be53abf4c --- /dev/null +++ b/fpga/usrp2/simple_gemac/ethtx_realign.v @@ -0,0 +1,77 @@ + +//////////////////////////////////////////////////////////////////////// +// Ethernet TX - Realign +// +// - removes a 2-byte pad from the front a fifo36 stream +// - occupancy is preserved +// + +module ethtx_realign + (input clk, input reset, input clear, + input [35:0] datain, input src_rdy_i, output dst_rdy_o, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i); + + reg [1:0] state; + reg [15:0] held; + reg [1:0] held_occ; + reg held_sof; + + wire xfer_in = src_rdy_i & dst_rdy_o; + wire xfer_out = src_rdy_o & dst_rdy_i; + + wire sof_in = datain[32]; + wire eof_in = datain[33]; + wire [1:0] occ_in = datain[35:34]; + wire occ_low = occ_in[1] ^ occ_in[0]; //occ is 1 or 2 + + always @(posedge clk) + if(reset | clear) + begin + held <= 0; + held_occ <= 0; + held_sof <= 0; + end + else if(xfer_in) + begin + held <= datain[15:0]; + held_occ <= occ_in; + held_sof <= sof_in; + end + + localparam RE_IDLE = 0; + localparam RE_HELD = 1; + localparam RE_DONE = 2; + + always @(posedge clk) + if(reset | clear) + state <= RE_IDLE; + else + case(state) + RE_IDLE : + if(xfer_in & eof_in) + state <= RE_DONE; + else if(xfer_in & sof_in) + state <= RE_HELD; + + RE_HELD : + if(xfer_in & xfer_out & eof_in) + if(occ_low) + state <= RE_IDLE; + else + state <= RE_DONE; + + RE_DONE : + if(xfer_out) + state <= RE_IDLE; + + endcase // case (state) + + wire sof_out = held_sof; + wire eof_out = (state == RE_HELD)? (eof_in & occ_low) : (state == RE_DONE); + wire [1:0] occ_out = ((state == RE_DONE)? held_occ : occ_in) ^ 2'b10; //(occ + 2)%4 + + assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]}; + assign src_rdy_o = (state == RE_HELD)? src_rdy_i : (state == RE_DONE); + assign dst_rdy_o = (state == RE_HELD)? dst_rdy_i : (state == RE_IDLE); + +endmodule // ethtx_realign diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v index b783729d5..8390eb2c6 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -106,17 +106,22 @@ module simple_gemac_wrapper // TX FIFO Chain wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; wire [7:0] tx_ll_data; - wire [35:0] tx_f36_data_int1; - wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; + wire [35:0] tx_f36_data_int1, tx_f36_data_int2; + wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_src_rdy_int2, tx_f36_dst_rdy_int2; fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset)); - + + ethtx_realign ethtx_realign + (.clk(tx_clk), .reset(tx_reset), .clear(clear), + .datain(tx_f36_data_int1), .src_rdy_i(tx_f36_src_rdy_int1), .dst_rdy_o(tx_f36_dst_rdy_int1), + .dataout(tx_f36_data_int2), .src_rdy_o(tx_f36_src_rdy_int2), .dst_rdy_i(tx_f36_dst_rdy_int2) ); + fifo36_to_ll8 fifo36_to_ll8 (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), + .f36_data(tx_f36_data_int2), .f36_src_rdy_i(tx_f36_src_rdy_int2), .f36_dst_rdy_o(tx_f36_dst_rdy_int2), .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy)); diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v index c155b7d41..2ac8b9be1 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v @@ -90,7 +90,6 @@ module simple_gemac_wrapper19 .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) ); - //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo (.wclk(rx_clk), .datain(rx_f19_data_int2), .src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space), diff --git a/fpga/usrp2/top/u1e/core_compile b/fpga/usrp2/top/u1e/core_compile new file mode 100755 index 000000000..dc0cd081e --- /dev/null +++ b/fpga/usrp2/top/u1e/core_compile @@ -0,0 +1,3 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models + + diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v index b3d71b4ab..d10a3ab30 100644 --- a/fpga/usrp2/top/u1e/u1e_core.v +++ b/fpga/usrp2/top/u1e/u1e_core.v @@ -11,7 +11,7 @@ module u1e_core input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, - output sclk, output [7:0] sen, output mosi, input miso, + output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, @@ -36,7 +36,7 @@ module u1e_core localparam SR_GLOBAL_RESET = 50; // 1 reg localparam SR_REG_TEST32 = 52; // 1 reg - wire [7:0] COMPAT_NUM = 8'd3; + wire [7:0] COMPAT_NUM = 8'd4; wire wb_clk = clk_fpga; wire wb_rst, global_reset; @@ -120,18 +120,15 @@ module u1e_core wire rx_eof = rx_data[33]; wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; - wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug, vr_debug; // ///////////////////////////////////////////////////////////////////////// // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx1_data; - wire run_rx; + wire [31:0] sample_rx; + wire strobe_rx, run_rx; wire [35:0] vita_rx_data; wire vita_rx_src_rdy, vita_rx_dst_rdy; - + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -139,20 +136,13 @@ module u1e_core .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .debug(debug_rx_dsp) ); - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), - .debug_rx(vrc_debug)); - - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), - .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), - .debug_rx(vrf_debug) ); + .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy), + .debug(vr_debug) ); fifo36_mux #(.prio(0)) mux_err_stream (.clk(wb_clk), .reset(wb_rst), .clear(0), @@ -368,7 +358,7 @@ module u1e_core atr_controller16 atr_controller16 (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); @@ -383,7 +373,7 @@ module u1e_core wb_readback_mux_16LE readback_mux_32 (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), - .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), .word00(vita_time[63:32]), .word01(vita_time[31:0]), .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), @@ -400,7 +390,8 @@ module u1e_core time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry @@ -415,7 +406,7 @@ module u1e_core */ assign debug = debug_gpmc; - assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, + assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; assign debug_gpio_1 = debug_vt; diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v index 79470de9e..0e6120ec6 100644 --- a/fpga/usrp2/top/u2_rev3/u2_core.v +++ b/fpga/usrp2/top/u2_rev3/u2_core.v @@ -136,18 +136,22 @@ module u2_core input [3:0] clock_divider ); - localparam SR_MISC = 0; // Uses 9 regs - localparam SR_BUF_POOL = 64; // Uses 4 regs - localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP0 = 160; // 16 - localparam SR_RX_CTRL0 = 176; // 16 - localparam SR_TIME64 = 192; // 3 - localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 208; // 16 - localparam SR_TX_CTRL = 224; // 16 - localparam SR_RX_DSP1 = 240; - localparam SR_RX_CTRL1 = 32; - + localparam SR_MISC = 0; // 7 regs + localparam SR_SIMTIMER = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_UDP_SM = 192; // 64 // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs @@ -208,23 +212,23 @@ module u2_core wire m0_err, m0_rty; wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // SD Card access + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // Unused + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // Unused .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), @@ -319,13 +323,12 @@ module u2_core .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone // I-port connects directly to processor and ram loader - wire flush_icache; ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), @@ -337,12 +340,8 @@ module u2_core .if_adr(16'b0), .if_data(), .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - setting_reg #(.my_addr(SR_MISC+7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - // ///////////////////////////////////////////////////////////////////////// // Buffer Pool, slave #1 wire rd0_ready_i, rd0_ready_o; @@ -417,7 +416,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd5; + localparam compat_num = 32'd6; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -434,7 +433,7 @@ module u2_core // Ethernet MAC Slave #6 simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19 + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), @@ -491,7 +490,7 @@ module u2_core setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(SR_MISC+8),.width(8), .at_reset(8'b0001_1110)) + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi index a7d051630..e5be670fb 100644 --- a/fpga/usrp2/top/u2plus/bootloader.rmi +++ b/fpga/usrp2/top/u2plus/bootloader.rmi @@ -1,5 +1,5 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4a20400_3a0b0b0b_0bae840c_82700b0b_0b0b0b0b; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4df2d_88080b0b_80088408; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_d6cd0400_3a0b0b80_80e29c0c_82700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80d7972d_88080b0b_80088408; defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; @@ -7,9 +7,9 @@ defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_ defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c3040000_0b0b0b88; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c4040000_0b0b0b88; defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; -defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a6_0981050b_72729f06; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a7_0981050b_72729f06; defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; @@ -18,239 +18,495 @@ defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_ defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; -defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_f0738306_0b0b0bad_71fc0608; -defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_992d5050_0b0b0b9e_88087575_80088408; -defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_cb2d5050_0b0b0b9f_88087575_80088408; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_88738306_0b0b80e2_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ee2d5050_0b0b80cd_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_a02d5050_0b0b80cf_88087575_80088408; defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; -defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae800c_810b0b0b; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e2980c_810b0b0b; defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; -defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_ff3f0410_81f33f9d; -defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; -defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; -defparam bootram.RAM0.INIT_23=256'hc00c8290_a0800bb5_b5bc0c82_0b0b0b0b_38838080_08822eb9_a138ae84_8008802e; -defparam bootram.RAM0.INIT_24=256'h80808480_b5c00cf8_8082800b_bc0cf880_0b0b0bb5_8080a40b_0c04f880_800bb5c4; -defparam bootram.RAM0.INIT_25=256'h0ba6b00b_c00c0b0b_80940bb5_0c80c0a8_0b0bb5bc_808c0b0b_0480c0a8_0bb5c40c; -defparam bootram.RAM0.INIT_26=256'hae8c0c70_92388412_5270802e_08700852_a338ae8c_c8335170_ff3d0db5_b5c40c04; -defparam bootram.RAM0.INIT_27=256'hb808802e_0b0b0bb5_04803d0d_833d0d04_0bb5c834_70f03881_70085252_2dae8c08; -defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5b8_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; -defparam bootram.RAM0.INIT_29=256'h518bb43f_d0055273_3fb23dfe_5254868c_59923d70_3dfee005_d03d0db2_3d0d0404; -defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_b43fa6b4_52735198_38765378_ff74278f_775481ff_8008b238; -defparam bootram.RAM0.INIT_2B=256'hb039fc3d_858a3fff_39a6ec51_a6b85184_3f91c23f_b4518598_068f38a6_812e0981; -defparam bootram.RAM0.INIT_2C=256'h3fa6f051_e03f86d6_85e13f8e_81a08c0c_fc3f800b_80e45189_81a08c0c_0d81ff0b; -defparam bootram.RAM0.INIT_2D=256'h51547380_70810651_08708d2a_3f81c6b4_805182ed_81ff0655_ee3f8008_84e23f83; -defparam bootram.RAM0.INIT_2E=256'h80805380_82c33f82_a6388151_8008802e_5190b53f_81fc8080_5184bd3f_c338a79c; -defparam bootram.RAM0.INIT_2F=256'hf8518484_3f8a39a7_73519191_5184913f_c43fa7bc_8eaa3f90_fc808051_ffff5281; -defparam bootram.RAM0.INIT_30=256'h5183e53f_9938a8fc_8008802e_518fa03f_3fb0800a_d05183f8_74b238a8_3ffea13f; -defparam bootram.RAM0.INIT_31=256'h8fc63f80_98800a51_5183cd3f_d83fa9b4_800a5190_88df3fb0_3f82ac51_815181f9; -defparam bootram.RAM0.INIT_32=256'h5183a53f_bb3faab0_800a518d_ffff5298_80805380_83ba3f82_38aa8451_08802eaa; -defparam bootram.RAM0.INIT_33=256'h80085480_518f893f_81fc8080_5183913f_ba39ab90_3faad451_a43f8fc9_82ac5188; -defparam bootram.RAM0.INIT_34=256'hac5187e9_82ea3f82_3faab051_80518d80_5281fc80_5380ffff_38828080_08802eb5; -defparam bootram.RAM0.INIT_35=256'h82c63ffc_39a7f851_3f81548a_80518fd5_5187da3f_db3f82ac_a7bc5182_3f8f8e3f; -defparam bootram.RAM0.INIT_36=256'hb7387581_54807425_74ff1656_5a575758_7a7c7f7f_04f83d0d_0c863d0d_e33f7380; -defparam bootram.RAM0.INIT_37=256'hff065185_05527781_538a3dfc_a1053482_33028405_70810558_8a3d3476_17575473; -defparam bootram.RAM0.INIT_38=256'h04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e_8a5186fd_81ff0654_cf3f8008; -defparam bootram.RAM0.INIT_39=256'hd051ff89_81f75280_3dfc0553_34815488_5675883d_748338dc_5580de56_02a30533; -defparam bootram.RAM0.INIT_3A=256'h70525684_02a70533_3dfc0552_34815389_0533893d_7c5702ab_04f93d0d_3f883d0d; -defparam bootram.RAM0.INIT_3B=256'h3f800881_755183b2_76537b52_77259738_2e9e3880_56547380_81ff0670_ef3f8008; -defparam bootram.RAM0.INIT_3C=256'h5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89_83388155_5473802e_ff067056; -defparam bootram.RAM0.INIT_3D=256'h3d0d04fb_75800c88_83388156_2e098106_567480de_883d3356_a03f800b_80d051ff; -defparam bootram.RAM0.INIT_3E=256'h5581bb3f_06537652_157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779; -defparam bootram.RAM0.INIT_3F=256'h800b800c_51819f3f_3f8a5272_705253cb_0d747653_0d04fe3d_800c873d_e539800b; -defparam bootram.RAM1.INIT_00=256'h81135374_55558439_76787055_04fc3d0d_3f833d0d_528051de_ff3d0d73_843d0d04; -defparam bootram.RAM1.INIT_01=256'h863d0d04_3473800c_e7388073_2e098106_0652718a_800881ff_80087334_5181b23f; -defparam bootram.RAM1.INIT_02=256'h0d04ff3d_1234823d_0533ae90_7251028f_04803d0d_3f833d0d_528051c9_ff3d0d73; -defparam bootram.RAM1.INIT_03=256'hae901333_3d0d8053_3d0d04fe_0c535183_05702272_7510abcc_81ce8005_0d73a029; -defparam bootram.RAM1.INIT_04=256'h0d767856_0d04fc3d_e738843d_53827325_d13f8113_33527251_3fae9413_527251c9; -defparam bootram.RAM1.INIT_05=256'h73a02981_7351df3f_87388d52_2e098106_33537281_38ae9014_09810694_54748a2e; -defparam bootram.RAM1.INIT_06=256'hce800552_73a02981_04ff3d0d_0c863d0d_38748c15_72802ef8_84140853_ce800554; -defparam bootram.RAM1.INIT_07=256'hc6a40870_c2880c81_0d800b81_0d04ff3d_800c833d_38901208_70802ef8_88120851; -defparam bootram.RAM1.INIT_08=256'h2a81c284_800c7088_ff0681c2_70227081_10ae9805_38845170_84712583_8f065151; -defparam bootram.RAM1.INIT_09=256'h81517180_33555354_88059705_0d767802_0d04fd3d_880c833d_800b81c2_0c515181; -defparam bootram.RAM1.INIT_0A=256'h81900b81_81c28c0c_72108107_5170f138_81065151_70862a70_81c29008_2e818638; -defparam bootram.RAM1.INIT_0B=256'h06708132_872a7081_c2900870_70f13881_06515151_812a7081_c2900870_c2900c81; -defparam bootram.RAM1.INIT_0C=256'h0c81c290_7081c290_8338a051_5171812e_b13880e8_3871802e_70802eba_51515151; -defparam bootram.RAM1.INIT_0D=256'hcc398151_34ff1252_70810556_08517074_3881c28c_515170f1_70810651_0870812a; -defparam bootram.RAM1.INIT_0E=256'h535481c2_97053355_78028805_fd3d0d76_853d0d04_0c70800c_0b81c290_883980c0; -defparam bootram.RAM1.INIT_0F=256'h81905170_802e8438_81d05171_81c28c0c_f1387210_51515170_2a708106_90087086; -defparam bootram.RAM1.INIT_10=256'h81067081_70872a70_81c29008_5170f138_81065151_70812a70_81c29008_81c2900c; -defparam bootram.RAM1.INIT_11=256'h2e833890_d0517181_c28c0c80_38733381_802e80c5_80cf3871_5170802e_32515151; -defparam bootram.RAM1.INIT_12=256'h2a708106_90087087_f13881c2_51515170_2a708106_90087081_900c81c2_517081c2; -defparam bootram.RAM1.INIT_13=256'h81c2900c_3980c00b_3981518a_5354ffb7_8114ff13_802e8e38_51515170_70813251; -defparam bootram.RAM1.INIT_14=256'h52717425_70a23870_06515254_0870810a_7581c6a4_04fd3d0d_0c853d0d_80517080; -defparam bootram.RAM1.INIT_15=256'h853d0d04_1252e239_27f13881_868d9f71_74315151_c6ac0870_ac085381_9b3881c6; -defparam bootram.RAM1.INIT_16=256'h06515171_127081ff_269638c9_527180da_ff065152_a9117081_8f0533ff_ff3d0d02; -defparam bootram.RAM1.INIT_17=256'h335358ff_58568076_3d0d797b_3d0d04f9_70800c83_ff065151_d0127081_b9268938; -defparam bootram.RAM1.INIT_18=256'h06721970_147081ff_aa387281_5371782e_81173353_ef38810b_09810682_5371ba2e; -defparam bootram.RAM1.INIT_19=256'h71d83881_70335152_bd387216_71802e82_53515452_06515151_337080c4_33abdd11; -defparam bootram.RAM1.INIT_1A=256'h7084190c_ff067205_3f800881_5252feec_06821733_842b9ff0_fb3f8008_163351fe; -defparam bootram.RAM1.INIT_1B=256'h80068417_8c2bbfe0_cb3f8008_163351fe_828a3883_54fd5374_11335753_7010178b; -defparam bootram.RAM1.INIT_1C=256'h9ff00673_8008842b_53fea93f_85173352_80067305_882b83fe_bb3f8008_335253fe; -defparam bootram.RAM1.INIT_1D=256'h842b9ff0_873f8008_163351fe_88180c87_ff067305_3f800881_5253fe98_05861733; -defparam bootram.RAM1.INIT_1E=256'hff068c19_89057081_d2387410_74742780_52717734_3f800812_5252fdf8_06881733; -defparam bootram.RAM1.INIT_1F=256'h53fdc13f_06723352_842b9ff0_cf3f8008_565152fd_52335552_70708105_08177119; -defparam bootram.RAM1.INIT_20=256'h51515284_065a525b_197081ff_81ff0681_33701a70_17081570_7274348c_80081353; -defparam bootram.RAM1.INIT_21=256'h81ff0673_19703070_05547305_0571882a_08783372_17088818_ffb03884_17087526; -defparam bootram.RAM1.INIT_22=256'h3f800812_5252fce4_068a1533_842b9ff0_f33f8008_515354fc_3356545b_101a8911; -defparam bootram.RAM1.INIT_23=256'h3d0d0480_72800c89_83398053_8539fe53_81068938_77722e09_5152fb53_7081ff06; -defparam bootram.RAM1.INIT_24=256'h337880ff_0d029305_0d04fe3d_f138823d_51515170_2a708106_90087088_3d0d81d6; -defparam bootram.RAM1.INIT_25=256'h7681d680_5170f138_81065151_70882a70_81d69008_80075353_060780c0_067a8c80; -defparam bootram.RAM1.INIT_26=256'h3881d690_72802e96_900c7251_800781d6_980c7182_ff0681d6_900c7581_0c7181d6; -defparam bootram.RAM1.INIT_27=256'h810b81d6_04fc3d0d_0c843d0d_08517080_3881d680_515170f1_70810651_0870882a; -defparam bootram.RAM1.INIT_28=256'h800b81d6_56fee43f_f63d0d7d_863d0d04_51ff873f_53805280_55885480_940c8880; -defparam bootram.RAM1.INIT_29=256'h88a80b81_81d6980c_800c810b_882b81d6_d6840c7c_0c8b0b81_0b81d690_980c8880; -defparam bootram.RAM1.INIT_2A=256'h900c8a80_800b81d6_80d33888_54737627_3f7e5580_900cfeb3_a80b81d6_d6900c8a; -defparam bootram.RAM1.INIT_2B=256'h883d7675_d680085b_84085a81_085981d6_5881d688_81d68c08_0cfe983f_0b81d690; -defparam bootram.RAM1.INIT_2C=256'h57348112_75708105_17517033_27913871_80527173_83387053_53707327_31525790; -defparam bootram.RAM1.INIT_2D=256'hc0526851_70545780_3d0d883d_3d0d04ea_d6980c8c_39800b81_1454ffa9_52ec3972; -defparam bootram.RAM1.INIT_2E=256'h81069438_81aa2e09_2e9d3873_547381ff_17703351_05575574_0284059d_fed23f80; -defparam bootram.RAM1.INIT_2F=256'h5473800c_27d13880_1555be75_548b3981_06853881_992e0981_51547381_74167033; -defparam bootram.RAM1.INIT_30=256'h85f73f80_d8527351_558453ab_fe823f80_84527951_3d705454_f93d0d86_983d0d04; -defparam bootram.RAM1.INIT_31=256'h97053370_fd3d0d02_a0940c04_04810b81_0c893d0d_81557480_81068338_08752e09; -defparam bootram.RAM1.INIT_32=256'h2ba00671_90067483_07077310_88067173_0672812a_71832a84_71872a07_852a8206; -defparam bootram.RAM1.INIT_33=256'h51525351_81d4800c_7081ff06_78872b07_06707207_852b80c0_81ff0676_73070770; -defparam bootram.RAM1.INIT_34=256'hff51ff98_ff9e3f81_5381ff51_81d00a07_74d00a06_04fe3d0d_52853d0d_55525555; -defparam bootram.RAM1.INIT_35=256'h81ff0652_72882a70_51ff813f_873f80e1_3fb251ff_9951ff8c_ff923f81_3f81aa51; -defparam bootram.RAM1.INIT_36=256'hdb3f7290_982a51fe_fee23f72_3f818151_b251fee8_51feed3f_7281ff06_52fef53f; -defparam bootram.RAM1.INIT_37=256'hfeba3fa0_bf3f8e51_3f8051fe_a151fec4_feca3f81_cf3fb051_065253fe_2a7081ff; -defparam bootram.RAM1.INIT_38=256'h8c0cf93d_398c0802_3d0d04ff_fea63f84_ab3f8051_3fa051fe_8051feb0_51feb53f; -defparam bootram.RAM1.INIT_39=256'h800b8c08_0888050c_0508308c_388c0888_088025ab_8c088805_08fc050c_0d800b8c; -defparam bootram.RAM1.INIT_3A=256'h088c0508_fc050c8c_05088c08_0c8c08f4_8c08f405_8838810b_08fc0508_f4050c8c; -defparam bootram.RAM1.INIT_3B=256'h38810b8c_fc050888_050c8c08_0b8c08f0_8c050c80_08308c08_8c088c05_8025ab38; -defparam bootram.RAM1.INIT_3C=256'h81a73f80_88050851_08528c08_8c088c05_050c8053_088c08fc_8c08f005_08f0050c; -defparam bootram.RAM1.INIT_3D=256'h8c08f805_08f8050c_0508308c_388c08f8_08802e8c_8c08fc05_f8050c54_08708c08; -defparam bootram.RAM1.INIT_3E=256'h88050880_050c8c08_0b8c08fc_fb3d0d80_08028c0c_8c0c048c_54893d0d_0870800c; -defparam bootram.RAM1.INIT_3F=256'h8c388c08_05088025_0c8c088c_8c08fc05_050c810b_308c0888_08880508_2593388c; -defparam bootram.RAM2.INIT_00=256'h8c08f805_3f800870_050851ad_528c0888_088c0508_0c81538c_8c088c05_8c050830; -defparam bootram.RAM2.INIT_01=256'h800c5487_f8050870_050c8c08_308c08f8_08f80508_2e8c388c_fc050880_0c548c08; -defparam bootram.RAM2.INIT_02=256'h088c0508_f8050c8c_800b8c08_08fc050c_0d810b8c_8c0cfd3d_048c0802_3d0d8c0c; -defparam bootram.RAM2.INIT_03=256'h088c0508_2499388c_088c0508_38800b8c_08802ea3_8c08fc05_0827ac38_8c088805; -defparam bootram.RAM2.INIT_04=256'h388c088c_802e80c9_08fc0508_0cc9398c_8c08fc05_fc050810_050c8c08_108c088c; -defparam bootram.RAM2.INIT_05=256'hf805088c_050c8c08_318c0888_088c0508_8805088c_a1388c08_88050826_05088c08; -defparam bootram.RAM2.INIT_06=256'h2a8c088c_8c050881_050c8c08_2a8c08fc_fc050881_050c8c08_078c08f8_08fc0508; -defparam bootram.RAM2.INIT_07=256'h8c08f805_0c518d39_8c08f405_88050870_8f388c08_0508802e_398c0890_050cffaf; -defparam bootram.RAM2.INIT_08=256'h56528372_78777956_04fc3d0d_3d0d8c0c_08800c85_8c08f405_f4050c51_08708c08; -defparam bootram.RAM2.INIT_09=256'h72712e09_74335253_a0387433_5271ff2e_b038ff12_5170802e_74078306_278c3874; -defparam bootram.RAM2.INIT_0A=256'h04747454_0c863d0d_38800b80_098106e2_5571ff2e_ff145455_81158115_8106bd38; -defparam bootram.RAM2.INIT_0B=256'h55ffaf39_38707355_718326e9_14545451_118414fc_068f3884_082e0981_51700873; -defparam bootram.RAM2.INIT_0C=256'h83065170_38727507_8f72278c_55555555_7670797b_04fc3d0d_0c863d0d_72713180; -defparam bootram.RAM2.INIT_0D=256'hff2e0981_ff125271_81055634_54337470_72708105_ff2e9838_ff125271_802ea738; -defparam bootram.RAM2.INIT_0E=256'h54087170_72708405_8405530c_54087170_72708405_0d047451_800c863d_06ea3874; -defparam bootram.RAM2.INIT_0F=256'hf0125271_8405530c_54087170_72708405_8405530c_54087170_72708405_8405530c; -defparam bootram.RAM2.INIT_10=256'h387054ff_718326ed_0cfc1252_70840553_05540871_38727084_83722795_8f26c938; -defparam bootram.RAM2.INIT_11=256'ha4528151_e3c63fae_0ce4a83f_3873b5cc_72812e98_84085454_0d800bae_8339fd3d; -defparam bootram.RAM2.INIT_12=256'h51843f00_a53f8008_528151e6_af3faea4_e4913fe3_72b5cc0c_08519b3f_e6bc3f80; -defparam bootram.RAM2.INIT_13=256'hff058171_18841908_d9388188_77802e80_085a545a_0882c811_0d7baea8_ff39f73d; -defparam bootram.RAM2.INIT_14=256'h77065372_81801908_88055656_822b7811_24b53873_e9388074_80742480_2b595559; -defparam bootram.RAM2.INIT_15=256'h57547380_812c5a57_17fc1779_2dff14fc_74085372_53537951_78167008_802eb538; -defparam bootram.RAM2.INIT_16=256'h2dff14fc_74085372_51f8c03f_08a53879_0853bc13_ad38aea8_085877ff_25d63877; -defparam bootram.RAM2.INIT_17=256'h53722d79_51bc1308_ff943972_d2398057_25ffa938_57547380_812c5a57_17fc1779; -defparam bootram.RAM2.INIT_18=256'h5270ff2e_12700852_38702dfc_70ff2e91_70085252_ac0bfc05_ff3d0db5_51f8943f; -defparam bootram.RAM2.INIT_19=256'h523a206d_4552524f_4f4b0000_00000040_3f040000_0404e398_38833d0d_098106f1; -defparam bootram.RAM2.INIT_1A=256'h49484558_20696e20_4261636b_65642120_7475726e_65207265_696d6167_61696e20; -defparam bootram.RAM2.INIT_1B=256'h6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00_64206d6f_206c6f61; -defparam bootram.RAM2.INIT_1C=256'h53746172_6e0a0000_6974696f_55206564_61205a50_756c7472_70657220_72207375; -defparam bootram.RAM2.INIT_1D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; -defparam bootram.RAM2.INIT_1E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072; -defparam bootram.RAM2.INIT_1F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368; -defparam bootram.RAM2.INIT_20=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361; -defparam bootram.RAM2.INIT_21=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061; -defparam bootram.RAM2.INIT_22=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845; -defparam bootram.RAM2.INIT_23=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070; -defparam bootram.RAM2.INIT_24=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072; -defparam bootram.RAM2.INIT_25=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d; -defparam bootram.RAM2.INIT_26=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374; -defparam bootram.RAM2.INIT_27=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67; -defparam bootram.RAM2.INIT_28=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00; -defparam bootram.RAM2.INIT_29=256'h64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67_204c6f61_756e642e; -defparam bootram.RAM2.INIT_2A=256'h65747572_523a2052_4552524f_2e000000_6d616765_6e672069_61727469_2e205374; -defparam bootram.RAM2.INIT_2B=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; -defparam bootram.RAM2.INIT_2C=256'h64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068_206e6576; -defparam bootram.RAM2.INIT_2D=256'h61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d_696f6e20; -defparam bootram.RAM2.INIT_2E=256'h00202020_0b0b0b0b_01b200d9_05160364_14580a2c_2e2e2e00_77617265_6669726d; -defparam bootram.RAM2.INIT_2F=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; -defparam bootram.RAM2.INIT_30=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; -defparam bootram.RAM2.INIT_31=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; -defparam bootram.RAM2.INIT_32=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; -defparam bootram.RAM2.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_37=256'hffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000_792e6578_64756d6d; -defparam bootram.RAM2.INIT_38=256'h0018000f_ffff0031_05050400_01010100_00001ab4_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_39=256'h00000000_00001a4c_000019f0_00001994_00000000_0000172c_000016e0_000b0000; -defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_000016ec; -defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3E=256'h1234e66d_330eabcd_00000001_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_000b0000_deec0005; -defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_15=256'h00000000_00000000_00000000_ffffffff_00000000_ffffffff_00000000_00000000; -defparam bootram.RAM3.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_cf943f04_82813f80; +defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010; +defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04; +defparam bootram.RAM0.INIT_23=256'h800b80e2_f40c82a0_0b0b80e2_8380800b_822ebd38_80e29c08_802ea438_80e29808; +defparam bootram.RAM0.INIT_24=256'h0b80e2f8_80808280_e2f40cf8_0b0b0b80_808080a4_fc0c04f8_800b80e2_f80c8290; +defparam bootram.RAM0.INIT_25=256'h940b80e2_80c0a880_80e2f40c_8c0b0b0b_80c0a880_e2fc0c04_84800b80_0cf88080; +defparam bootram.RAM0.INIT_26=256'h70085252_80e2a408_5170a738_80e38033_04ff3d0d_80e2fc0c_80d7c80b_f80c0b0b; +defparam bootram.RAM0.INIT_27=256'h8034833d_810b80e3_5270ee38_08700852_2d80e2a4_e2a40c70_38841280_70802e94; +defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e2f008_3d0d0b0b_0d040480; +defparam bootram.RAM0.INIT_29=256'h852eb238_5a798380_0d973d22_0404ee3d_3f823d0d_0b0bf5d4_e2f0510b_040b0b80; +defparam bootram.RAM0.INIT_2A=256'h5a953d22_819d3980_862e8f38_39798380_8e3881a7_8380842e_248b3879_79838085; +defparam bootram.RAM0.INIT_2B=256'h7053963d_f423923d_3d2280e4_39815a95_e4f8238a_953d2280_9539825a_80e4fc23; +defparam bootram.RAM0.INIT_2C=256'h7b1d7f1d_3d415e5c_0b883d99_5b5f4080_0284057b_ae3f8008_abdc3f8b_84055241; +defparam bootram.RAM0.INIT_2D=256'h79337b34_7d055b5b_7b1d963d_901f5e5c_ef38800b_5c887c26_7b34811c_5b5b7933; +defparam bootram.RAM0.INIT_2E=256'h7c26ef38_811c5c86_79337b34_601d5b5b_5e5c7b1d_800b881f_7c26ed38_811c5c88; +defparam bootram.RAM0.INIT_2F=256'h3d0d686a_3d0d04ee_9d903f94_7c26ef38_811c5c86_79337b34_611d5b5b_805c7b1e; +defparam bootram.RAM0.INIT_30=256'ha23f80e1_d7cc5198_538a5280_2e8f3875_0856758a_27973876_5a578379_8412085a; +defparam bootram.RAM0.INIT_31=256'h9f185675_17085dff_5ba05c88_3fa0588a_9c51988f_a45280d8_8e387853_5878a326; +defparam bootram.RAM0.INIT_32=256'h39951733_085e82f2_cc3f8008_80c15c8a_56750804_80da8c05_38758429_95268388; +defparam bootram.RAM0.INIT_33=256'h55961733_5a515677_2a848006_70307096_3380f232_92389417_7580f22e_56888058; +defparam bootram.RAM0.INIT_34=256'h80085f80_5199b83f_38815877_75782e83_18335758_52800b97_538c1708_54901708; +defparam bootram.RAM0.INIT_35=256'h398d1733_c95c81dd_8fdb3f80_18335256_ea05538c_7054953d_398d1733_d35c82aa; +defparam bootram.RAM0.INIT_36=256'h75822488_822ea038_17335675_81c7399c_3f80c85c_525690e7_538c1833_70548e18; +defparam bootram.RAM0.INIT_37=256'h17085692_5695398c_1808710c_8c170890_8106a038_75842e09_a138a839_3875812e; +defparam bootram.RAM0.INIT_38=256'h9e387582_5675822e_399c1733_d05c81ba_33763480_08569317_8a398c17_17227623; +defparam bootram.RAM0.INIT_39=256'h17087022_5691398c_08700840_9a388c17_2e098106_a2397584_812e9d38_24883875; +defparam bootram.RAM0.INIT_3A=256'h7553943d_83389456_56947625_398d1733_d25c80fe_33405680_8c170870_40568839; +defparam bootram.RAM0.INIT_3B=256'h94762583_8d173356_3480d739_8405b505_5c800802_bc3f80d6_1733518b_ea05528c; +defparam bootram.RAM0.INIT_3C=256'h05b50534_5c750284_9d3f80d5_1733518a_8e17528c_993f7553_1733518d_3894568c; +defparam bootram.RAM0.INIT_3D=256'h57577533_963d7905_5a587719_800b833d_3ddc0554_17085594_80cc5c8c_ad39785e; +defparam bootram.RAM0.INIT_3E=256'h19963d79_3d5a5877_54800b83_943ddc05_a05ca455_ed38a439_58887826_77348118; +defparam bootram.RAM0.INIT_3F=256'h0d747053_0d04fe3d_a63f943d_8080519d_26ed3883_18588878_33773481_05575775; +defparam bootram.RAM1.INIT_00=256'h8d39a052_3f9db93f_815191ea_5188953f_38a052a0_72802e92_5394b83f_80d8e852; +defparam bootram.RAM1.INIT_01=256'h5280d9a4_89b53f86_80d98851_0d82b53f_0d04fa3d_d93f843d_3f725191_72518884; +defparam bootram.RAM1.INIT_02=256'h92b43f88_3f800851_bd3f85df_85cb3f86_3fa7f13f_c45193f3_8a5280d9_5193fc3f; +defparam bootram.RAM1.INIT_03=256'h96db3f86_52800851_85c13f73_3f800854_8c3f86b1_92ce3f88_3f800851_983f86bd; +defparam bootram.RAM1.INIT_04=256'h83808451_3f8ab252_805197a1_fb528380_96e53f8b_5190bf3f_84528008_a03f8380; +defparam bootram.RAM1.INIT_05=256'h825196f9_dd528380_97833fbe_83808651_3f8ab252_8551978d_b2528380_97973f8a; +defparam bootram.RAM1.INIT_06=256'h802e80c9_08568008_90b43f80_3dfc0551_aabb3f88_51a8a93f_bd3f8ffa_3f805190; +defparam bootram.RAM1.INIT_07=256'h055180c3_52800890_5380d9e8_06ad3884_ee2e0981_557382fd_8e052255_38768008; +defparam bootram.RAM1.INIT_08=256'h3f883974_735185dd_3f86e23f_525491a4_3f941670_f05192b3_9a3880d9_853f8008; +defparam bootram.RAM1.INIT_09=256'h8d38a00b_5573802e_81065155_70852a70_82808c08_3f8eae3f_b43f8fb9_5275519c; +defparam bootram.RAM1.INIT_0A=256'h808c0c80_80c00b82_2efef838_51547380_2a708106_9d3f7486_80d55186_82808c0c; +defparam bootram.RAM1.INIT_0B=256'h3f9f5280_aa3f89d8_889f3f8d_3f82b73f_f53f93c5_fe3d0d85_3ffee839_cf518682; +defparam bootram.RAM1.INIT_0C=256'hcf3f8852_82ac518c_5185913f_3f845284_ac518cdc_859e3f82_9f528051_5185c23f; +defparam bootram.RAM1.INIT_0D=256'h805184e8_82539f52_518cb53f_f73f82ac_52905184_8cc23f90_3f82ac51_88518584; +defparam bootram.RAM1.INIT_0E=256'h9f529e51_8025df38_ff135372_518c993f_db3f80e4_529c5184_8ca63f9f_3f80e451; +defparam bootram.RAM1.INIT_0F=256'h808c0870_803d0d82_843d0d04_810b800c_81e0840c_bf3f890b_52815184_84e33f9f; +defparam bootram.RAM1.INIT_10=256'h82055a57_30708025_a7053370_7f028c05_3d0d7a7d_3d0d04f9_800c5182_8b2a8106; +defparam bootram.RAM1.INIT_11=256'h30709f2a_388a5573_88557383_832e8838_88055575_38728025_75822e93_57585957; +defparam bootram.RAM1.INIT_12=256'h842b0751_fe057072_05777131_76812cff_802e9738_38725472_8177259e_51538054; +defparam bootram.RAM1.INIT_13=256'h73528118_51ac9a3f_ff065277_a43f7281_527b51ac_81805474_86397353_54548054; +defparam bootram.RAM1.INIT_14=256'h54bd5378_815580ca_9f053356_fb3d0d02_893d0d04_51ac8a3f_815280da_51ac923f; +defparam bootram.RAM1.INIT_15=256'hff3ffeb8_51d63f90_3f815281_c551abe1_0d815280_0d04fe3d_e63f873d_527551fe; +defparam bootram.RAM1.INIT_16=256'hfa3d0d78_843d0d04_e0800c53_70900781_81e08008_802ef338_ff065372_3f800881; +defparam bootram.RAM1.INIT_17=256'h33527181_38805471_70802e83_70335252_9e387217_53727627_70565480_7a575781; +defparam bootram.RAM1.INIT_18=256'h04fe3d0d_0c883d0d_81517080_802e8338_74075170_53df3974_80558113_ff2e8338; +defparam bootram.RAM1.INIT_19=256'h88335574_3d0d80e3_3d0d04f9_bcac3f84_80e2ac51_80dae852_88348653_810b80e3; +defparam bootram.RAM1.INIT_1A=256'h80d051ab_54568252_54873d70_24b63886_08558075_3481b8a4_0b80e388_80c63881; +defparam bootram.RAM1.INIT_1B=256'h38865375_0655748c_800881ff_51fee93f_38865275_74802e9c_81ff0655_d53f8008; +defparam bootram.RAM1.INIT_1C=256'h80e2a80c_80dae408_80e38434_0d04810b_800c893d_80e2ac0b_51bbd73f_5280e2ac; +defparam bootram.RAM1.INIT_1D=256'h38845487_807524b3_b8a40855_e3843481_38810b80_557480c3_80e38433_04fb3d0d; +defparam bootram.RAM1.INIT_1E=256'h0551fdfc_52873dfc_2e993884_06557480_800881ff_51aaeb3f_8c5280d0_3dfc0553; +defparam bootram.RAM1.INIT_1F=256'h77568454_04fb3d0d_0c873d0d_e2a80b80_e2a80c80_86387580_ff065574_3f800881; +defparam bootram.RAM1.INIT_20=256'h0b80e384_e2a80c81_38750880_74802e8d_81ff0655_b13f8008_80d051a9_75538c52; +defparam bootram.RAM1.INIT_21=256'h81e08c0c_80e38c0c_08060770_7180e38c_09737506_803d0d73_873d0d04_3474800c; +defparam bootram.RAM1.INIT_22=256'h0c51823d_0c81e098_7080e390_90080607_067180e3_73097375_04803d0d_51823d0d; +defparam bootram.RAM1.INIT_23=256'h8a528051_04ff3d0d_0c843d0d_c93f7280_53805182_0d747053_3f04fe3d_0d0482b1; +defparam bootram.RAM1.INIT_24=256'h157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779_3d0d04fb_82b83f83; +defparam bootram.RAM1.INIT_25=256'h75335556_59565880_0d797b7d_0d04f93d_800c873d_e539800b_5582933f_06537652; +defparam bootram.RAM1.INIT_26=256'h8b387581_5473802e_e53f7433_78525581_81157453_77259d38_38815680_73762ea4; +defparam bootram.RAM1.INIT_27=256'h04fe3d0d_3f833d0d_8051ff8f_3d0d7352_3d0d04ff_75800c89_7324e538_17575376; +defparam bootram.RAM1.INIT_28=256'h528051dd_ff3d0d73_843d0d04_800b800c_5181ab3f_3f8a5272_5253feff_74765370; +defparam bootram.RAM1.INIT_29=256'h73348008_c23f8008_53755181_84398113_56575556_77797b71_04fb3d0d_3f833d0d; +defparam bootram.RAM1.INIT_2A=256'h7431800c_80733472_7224db38_74315274_2e8a3872_387181ff_718a2e90_81ff0652; +defparam bootram.RAM1.INIT_2B=256'h14708429_0d738429_0d04ff3d_1234823d_3380e2b4_51028f05_803d0d72_873d0d04; +defparam bootram.RAM1.INIT_2C=256'hb4133352_805380e2_04fe3d0d_51833d0d_720c5451_f0057022_761080da_82908005; +defparam bootram.RAM1.INIT_2D=256'h0d767856_0d04fc3d_e538843d_53827325_c93f8113_33527251_80e2b813_7251c13f; +defparam bootram.RAM1.INIT_2E=256'h3f738429_527351de_0687388d_812e0981_14335372_3880e2b4_09810695_54748a2e; +defparam bootram.RAM1.INIT_2F=256'h3d0d7484_3d0d04fe_8c150c86_2ef83874_08537280_55538414_82908005_14708429; +defparam bootram.RAM1.INIT_30=256'h800c843d_12085372_2e853890_ff537080_52535181_05881108_29829080_29157084; +defparam bootram.RAM1.INIT_31=256'h38901208_70732e91_52545253_05881108_29829080_29167084_0d807584_0d04fe3d; +defparam bootram.RAM1.INIT_32=256'h0c81b8a4_0b81a888_ff3d0d80_843d0d04_3872800c_545170f1_88140852_7081ff06; +defparam bootram.RAM1.INIT_33=256'h0c70882a_0681a880_227081ff_e2bc0570_51701080_25833884_51518471_08708f06; +defparam bootram.RAM1.INIT_34=256'h55535481_05970533_76780288_04fd3d0d_0c833d0d_0b81a888_51518180_81a8840c; +defparam bootram.RAM1.INIT_35=256'ha88c0c81_10810781_70f13872_06515151_862a7081_a8900870_81863881_5171802e; +defparam bootram.RAM1.INIT_36=256'h2a708106_90087087_f13881a8_51515170_2a708106_90087081_900c81a8_900b81a8; +defparam bootram.RAM1.INIT_37=256'h81a8900c_38a05170_71812e83_3880e851_71802eb1_802eba38_51515170_70813251; +defparam bootram.RAM1.INIT_38=256'hff1252cc_81055634_51707470_81a88c08_5170f138_81065151_70812a70_81a89008; +defparam bootram.RAM1.INIT_39=256'h05335553_02880597_3d0d7678_3d0d04fd_70800c85_81a8900c_3980c00b_39815188; +defparam bootram.RAM1.INIT_3A=256'h2e843881_d0517180_a88c0c81_38721081_515170f1_70810651_0870862a_5481a890; +defparam bootram.RAM1.INIT_3B=256'h872a7081_a8900870_70f13881_06515151_812a7081_a8900870_a8900c81_90517081; +defparam bootram.RAM1.INIT_3C=256'h5171812e_8c0c80d0_733381a8_2e80c538_cf387180_70802e80_51515151_06708132; +defparam bootram.RAM1.INIT_3D=256'h0870872a_3881a890_515170f1_70810651_0870812a_0c81a890_7081a890_83389051; +defparam bootram.RAM1.INIT_3E=256'h80c00b81_81518a39_54ffb739_14ff1353_2e8e3881_51517080_81325151_70810670; +defparam bootram.RAM1.INIT_3F=256'ha2387052_51525470_70810a06_81b8a408_fd3d0d75_853d0d04_5170800c_a8900c80; +defparam bootram.RAM2.INIT_00=256'h52e23985_f1388112_8d9f7127_31515186_ac087074_085381b8_3881b8ac_7174259b; +defparam bootram.RAM2.INIT_01=256'h808c0c80_0cff0b82_0b828084_80800cef_81e20b82_8280880c_3d0dff0b_3d0d04ff; +defparam bootram.RAM2.INIT_02=256'h82808808_04fb3d0d_38833d0d_708025f1_0cff1151_70840554_51a1c972_e4d45287; +defparam bootram.RAM2.INIT_03=256'h38725173_71802e8f_74760652_e4d45555_53810b80_58515280_8c087106_70098280; +defparam bootram.RAM2.INIT_04=256'h04ff3d0d_38873d0d_877325dc_10575553_13841576_0c8f3981_7482808c_0852712d; +defparam bootram.RAM2.INIT_05=256'h72068280_80880870_2b700982_0c518172_d4057571_842980e4_269f3871_73527187; +defparam bootram.RAM2.INIT_06=256'h0c833d0d_5281e0c8_81e0c40c_22747008_0d029205_0404ff3d_52833d0d_880c5351; +defparam bootram.RAM2.INIT_07=256'hcc0c823d_820b81e0_802ef338_06515170_a0087084_cc0c81b8_810b81e0_04803d0d; +defparam bootram.RAM2.INIT_08=256'hb8a00875_2e933881_54527280_08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f; +defparam bootram.RAM2.INIT_09=256'hfc51f7af_8b3880da_5271802e_70810651_3971812a_8080529a_0c535381_71902a71; +defparam bootram.RAM2.INIT_0A=256'h2ef23881_51517080_7080c006_81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f; +defparam bootram.RAM2.INIT_0B=256'ha0087090_0c5281b8_0781e0cc_70902b88_028e0522_04ff3d0d_0c823d0d_80800b80; +defparam bootram.RAM2.INIT_0C=256'h8638ba51_5372802e_0d755480_0d04fd3d_cc0c833d_840b81e0_802ef338_06515170; +defparam bootram.RAM2.INIT_0D=256'h83113356_fb3d0d77_853d0d04_7327e638_81135385_52a1ca3f_14703352_f5c43f72; +defparam bootram.RAM2.INIT_0E=256'h61630290_3d0d7c7e_3d0d04f6_80ed3f87_80db8051_70335356_81113354_82113355; +defparam bootram.RAM2.INIT_0F=256'had51782d_8a387952_3875802e_7680258f_5d5b5957_2a515b5f_7030709f_05bb0533; +defparam bootram.RAM2.INIT_10=256'h527651a9_ffbd3f77_3f800851_7651a990_80537752_79557854_77269438_76305777; +defparam bootram.RAM2.INIT_11=256'h3d0d04f7_f4ac3f82_8b053351_803d0d02_8c3d0d04_3351782d_80db8c05_a83f8008; +defparam bootram.RAM2.INIT_12=256'h387681ff_802e81d1_06575775_337081ff_5c5a5878_5208a4b0_70708405_3d0d8c3d; +defparam bootram.RAM2.INIT_13=256'ha0387580_7580f024_2e80fb38_597580f0_19703357_80db3881_2e098106_065675a5; +defparam bootram.RAM2.INIT_14=256'h397580f5_c638818b_80e42e80_81953975_2e819e38_8a387580_7580e324_e32eb938; +defparam bootram.RAM2.INIT_15=256'h77841983_3880ec39_80f82eba_80f53975_2e80db38_387580f3_80f5248b_2eac3875; +defparam bootram.RAM2.INIT_16=256'h53903977_a4b05480_59568055_19710852_da397784_51792d80_56805275_12335259; +defparam bootram.RAM2.INIT_17=256'ha4b05480_59568055_19710852_92397784_81538a52_55a4b054_52595680_84197108; +defparam bootram.RAM2.INIT_18=256'h76708105_8e388052_5675802e_59567633_19710859_9e397784_51fdd03f_53905275; +defparam bootram.RAM2.INIT_19=256'h803d0d81_a0940c04_04810b81_0c8b3d0d_39800b80_1959fea3_2dec3981_58335179; +defparam bootram.RAM2.INIT_1A=256'hff067b8c_05337980_3d0d0297_3d0d04fd_70f13882_06515151_882a7081_a0900870; +defparam bootram.RAM2.INIT_1B=256'h81a0900c_a0800c72_980c7781_ff0681a0_3f7683ff_555354d0_80c08007_80060770; +defparam bootram.RAM2.INIT_1C=256'h3d0d04fc_70800c85_a0800851_ffaa3f81_802e8938_0c735173_0781a090_7180c280; +defparam bootram.RAM2.INIT_1D=256'h3971902a_555351ee_73058115_10157022_278f3872_80537274_7a545555_3d0d7678; +defparam bootram.RAM2.INIT_1E=256'h86537552_04fd3d0d_0c863d0d_ec397180_902a0552_ffff0672_8d387183_5170802e; +defparam bootram.RAM2.INIT_1F=256'h80720c88_a8528551_3d0d80e3_3d0d04ff_a00c5485_700880e3_aaf83f76_80e39851; +defparam bootram.RAM2.INIT_20=256'h52702254_80e3a452_2253800b_0d029605_0d04fd3d_f338833d_52708025_12ff1252; +defparam bootram.RAM2.INIT_21=256'h787a7183_04fa3d0d_0c853d0d_80517080_7225ee38_12525285_38811288_72742e8e; +defparam bootram.RAM2.INIT_22=256'h80e3a455_80e3a80b_ad398008_0884050c_89387680_8008802e_5856c73f_ffff0653; +defparam bootram.RAM2.INIT_23=256'h73237684_988c3f75_7525eb38_14545585_38811588_71802e8f_88155552_55557308; +defparam bootram.RAM2.INIT_24=256'h88055291_7353923d_54a9c73f_3dd60552_933d5392_0d867054_0d04f13d_140c883d; +defparam bootram.RAM2.INIT_25=256'h23800b8c_8405a605_3d238002_8a800b8b_a2052381_80028405_a9b83f90_3ddc0551; +defparam bootram.RAM2.INIT_26=256'h5e80538a_23685d66_8405ae05_3d238002_c0910b8d_aa052380_80028405_3d238180; +defparam bootram.RAM2.INIT_27=256'h05ba0523_3d220284_903d2396_23983d22_8405ae05_3f800802_0551fdb7_52913de4; +defparam bootram.RAM2.INIT_28=256'h9a903f91_e6840551_80c02981_d4055269_ac53913d_05be0523_23800284_800b913d; +defparam bootram.RAM2.INIT_29=256'h80e39852_a53f8653_f20551a8_3d529a3d_2386539b_800b973d_3d0d805b_3d0d04e8; +defparam bootram.RAM2.INIT_2A=256'h5a800b9b_08800858_f7f73f80_80e20523_22028405_0280f205_51a8973f_9a3df805; +defparam bootram.RAM2.INIT_2B=256'ha33d0840_a13d085f_905d6e5e_4659845c_45a33d08_44a13d08_f005436e_3dc41143; +defparam bootram.RAM2.INIT_2C=256'h75085473_3873760c_73752784_51565a55_90807131_1a787c31_58750870_8c3d5684; +defparam bootram.RAM2.INIT_2D=256'h3f750853_a851eedc_883880db_5473802e_16088306_738c3894_73830654_802e9a38; +defparam bootram.RAM2.INIT_2E=256'h26843880_ac3878bf_778025ff_ff195957_05570817_3f757084_765198e6_94160852; +defparam bootram.RAM2.INIT_2F=256'h1f94055a_943d237f_818a800b_6b6e4040_04ea3d0d_3f9a3d0d_2a51f781_c0597882; +defparam bootram.RAM2.INIT_30=256'h5a79963d_80c08007_ce052369_02840580_23818080_800b953d_80ca0523_79028405; +defparam bootram.RAM2.INIT_31=256'h8008095a_5cfae43f_933d7052_80538a52_08466847_2380e3a0_0580d205_23800284; +defparam bootram.RAM2.INIT_32=256'h923880db_ff065a79_3f800881_5c5e8a8e_983d7053_913d7053_80d20523_79028405; +defparam bootram.RAM2.INIT_33=256'h54908053_5d94557b_60586b57_7f5a6d59_3fa93902_cf3fec8d_3f7a51f6_d451f7db; +defparam bootram.RAM2.INIT_34=256'h3d0d7f58_3d0d04f7_fd8d3f98_7c26ef38_811c5c86_79337b34_7c1f5b5b_805c7b1d; +defparam bootram.RAM2.INIT_35=256'h05237756_028405a6_8b3d2380_88185776_05a20523_3d220284_8a3d238d_02ae0522; +defparam bootram.RAM2.INIT_36=256'h90800284_0b8e3d23_ee3d0d81_8b3d0d04_51fe9e3f_5391527d_8b3df805_7e558854; +defparam bootram.RAM2.INIT_37=256'h80085294_be3f8653_b60523e8_81028405_05b50534_34840284_860b8f3d_05b20523; +defparam bootram.RAM2.INIT_38=256'h3df60551_53805294_a4c83f86_3df20551_80085294_983f8453_a4d83fe9_3dec0551; +defparam bootram.RAM2.INIT_39=256'h8653805b_e4055490_9c55943d_80578056_80598058_0843025c_fc3f8008_a5d53fe8; +defparam bootram.RAM2.INIT_3A=256'haa3d088e_04d93d0d_3f943d0d_ef38fbcf_5b867b26_7a34811b_dba01b33_7a1c5a80; +defparam bootram.RAM2.INIT_3B=256'h8d387952_5b799b26_29f2055b_ac3d0884_9d38901d_09810682_7d90862e_11225f5d; +defparam bootram.RAM2.INIT_3C=256'h802e0981_225a7990_a838821b_09810686_5a79812e_b4397a22_f5b93f86_80dc8451; +defparam bootram.RAM2.INIT_3D=256'h85ff389e_2e098106_225a7981_8c38861b_09810686_798c842e_841b225a_06869a38; +defparam bootram.RAM2.INIT_3E=256'h0551a28a_a93dffa8_80e3a052_08438453_87c33f80_1d70525f_87cb3fa8_1d705240; +defparam bootram.RAM2.INIT_3F=256'h821b2202_22a13d23_a2e83f7a_98527951_865380e3_38a73d5a_800885d5_3f80085c; +defparam bootram.RAM3.INIT_00=256'h05238653_84058182_05348202_84058181_851b3302_33a23d34_0523841b_840580fe; +defparam bootram.RAM3.INIT_01=256'h5b865398_02818e05_5aa2a73f_3dea0552_547f53aa_b53f8470_e40551a2_7952a93d; +defparam bootram.RAM3.INIT_02=256'ha2803f02_7a527e51_3d5f8653_a28c3f9e_3df40551_537f52a9_a2983f79_1d527a51; +defparam bootram.RAM3.INIT_03=256'h811c5c86_79337b34_7f1d5b5b_7d537b1d_3ddc0554_5d9c55a9_7c587c57_7c5a7c59; +defparam bootram.RAM3.INIT_04=256'h5b5b6084_708c2a43_901d7022_0684aa38_802e0981_b4397d90_f99d3f84_7c26ef38; +defparam bootram.RAM3.INIT_05=256'hffff065e_861b2280_06848638_852e0981_06515a79_882a708f_84973879_2e098106; +defparam bootram.RAM3.INIT_06=256'h5580e3a0_7d901c62_8338815f_993f8008_821d51a0_80dba052_7d5f8653_7d83fa38; +defparam bootram.RAM3.INIT_07=256'h5183fe3f_1d529c1d_83c73888_387b802e_815c7e87_80088338_5ca0833f_5470535b; +defparam bootram.RAM3.INIT_08=256'h087a08a4_a4388c1b_09810683_387f912e_812e81bb_415d407f_1c22ec11_891b3382; +defparam bootram.RAM3.INIT_09=256'h1de41d82_838339ac_51f2883f_5280dca4_3879537e_7e7a2e8f_5d5d4240_1f841122; +defparam bootram.RAM3.INIT_0A=256'h3d405a88_499a3d99_993d237f_ec387a22_08802e82_80084280_5df5c73f_1d22535d; +defparam bootram.RAM3.INIT_0B=256'h8853a93d_3d236047_821b2297_519feb3f_5379527f_9c3d4088_519ff73f_537e5279; +defparam bootram.RAM3.INIT_0C=256'h1d7f1d5b_3d5e5c7b_7c557d84_cd3f7b56_527e519f_3f885379_79519fd6_ffb40552; +defparam bootram.RAM3.INIT_0D=256'h887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c_5b79337b; +defparam bootram.RAM3.INIT_0E=256'h2e818138_8a387e88_427e832e_7033415b_1b08a41e_81f3398c_085a792d_38618405; +defparam bootram.RAM3.INIT_0F=256'h810681bd_79912e09_1e335b5b_80c01db5_0680e838_832e0981_1a335a79_81db3981; +defparam bootram.RAM3.INIT_10=256'h840c7d81_0c7d81e1_0b81e180_9438810a_2e098106_5c5a797b_80e4fc22_38821b22; +defparam bootram.RAM3.INIT_11=256'hc40c7d81_0c7d81e2_0b81e2c0_9438810a_2e098106_225b797b_3980e4f8_e1880cb3; +defparam bootram.RAM3.INIT_12=256'h3f80de39_e951e48a_e4d00c80_86387d81_2e098106_225b797b_3980e4f4_e2c80c93; +defparam bootram.RAM3.INIT_13=256'h22963d23_0523841a_840580ce_05347d02_840580cd_3d347d02_5d5d7d95_ac1de41d; +defparam bootram.RAM3.INIT_14=256'h527c51f1_537b812a_8a3f8008_70525bf2_6052943d_05237d53_840580d2_861a2202; +defparam bootram.RAM3.INIT_15=256'h3fa93d0d_6151f6b1_7a537f52_7c557e54_05237b56_840580ce_095a7902_fe3f8008; +defparam bootram.RAM3.INIT_16=256'h8c135351_56517108_80e3dc54_38767008_727427a4_d4085553_800b80e3_04fc3d0d; +defparam bootram.RAM3.INIT_17=256'h04fb3d0d_0c863d0d_ff517080_7326e738_81135373_72518b39_81068538_70752e09; +defparam bootram.RAM3.INIT_18=256'he3d40c8e_38811480_73872689_e3d40854_25ba3880_3f800880_5755ffb9_77797153; +defparam bootram.RAM3.INIT_19=256'h54865375_dc120c51_760880e3_1470822b_0c547310_0680e3d8_08811187_3980e3d8; +defparam bootram.RAM3.INIT_1A=256'h813f873d_e005519c_842980e3_53755273_08055486_80081080_14519439_5280e3e0; +defparam bootram.RAM3.INIT_1B=256'h842980e3_54865373_10800805_99388008_73800824_d83f8054_0d7551fe_0d04fd3d; +defparam bootram.RAM3.INIT_1C=256'h2b71902b_12337198_75703381_04fd3d0d_0c853d0d_81547380_519bd73f_e0055276; +defparam bootram.RAM3.INIT_1D=256'h0d883d70_0d04ea3d_5452853d_52535456_7107800c_07831633_70882b72_07821433; +defparam bootram.RAM3.INIT_1E=256'h9d387381_7381ff2e_70335154_57557417_84059d05_b43f8002_52685194_545780c0; +defparam bootram.RAM3.INIT_1F=256'h55be7527_8b398115_85388154_2e098106_54738199_16703351_06943874_aa2e0981; +defparam bootram.RAM3.INIT_20=256'h845380dc_e43f8055_52795193_70545484_3d0d863d_3d0d04f9_73800c98_d1388054; +defparam bootram.RAM3.INIT_21=256'he0940c04_04810b81_0c893d0d_81557480_81068338_08752e09_99c43f80_c8527351; +defparam bootram.RAM3.INIT_22=256'h81065151_708d2a70_81b8b408_5189bb3f_ff065580_3f800881_d13f8abc_fc3d0d8d; +defparam bootram.RAM3.INIT_23=256'h8008802e_51febf3f_3fb0800a_8451e1a4_b53880dd_81833974_80dccc51_54738838; +defparam bootram.RAM3.INIT_24=256'hdde85180_84b53f80_b0800a51_51e6d93f_813f82ac_3f815189_b051e190_9a3880dd; +defparam bootram.RAM3.INIT_25=256'hff529880_805380ff_e33f8380_deb451e0_2ebb3880_3f800880_0a51fee3_cc399880; +defparam bootram.RAM3.INIT_26=256'h82ac51e6_51e0bd3f_3f80df84_9b3ffee5_82ac51e6_51e0cd3f_3f80dee0_0a5192b9; +defparam bootram.RAM3.INIT_27=256'h0d757053_0c04fd3d_7180e4bc_863d0d04_51e0a93f_3980dfc0_83e93f88_8b3f8051; +defparam bootram.RAM3.INIT_28=256'h2d853d0d_38735172_72802e85_e4bc0853_de9a3f80_a052a051_54eab83f_80e08c52; +defparam bootram.RAM3.INIT_29=256'h04fc3d0d_2d843d0d_38805172_72802e85_e4bc0853_ddfe3f80_a0528051_04fe3d0d; +defparam bootram.RAM3.INIT_2A=256'h08868006_38820b80_802e80ec_54815571_81065153_08862a70_3fff0b80_9a518987; +defparam bootram.RAM3.INIT_2B=256'h54718480_8a3987e8_802e8e38_388a5471_8280248a_2e9b3871_54718280_535580e4; +defparam bootram.RAM3.INIT_2C=256'h83067207_088a2c70_2a8c0680_ba3f7188_52855188_c23f8008_54845188_2e8338ff; +defparam bootram.RAM3.INIT_2D=256'hc8110852_8c0680e2_3f71822b_5452debb_c4555351_c80c80e0_337080e4_80e18411; +defparam bootram.RAM3.INIT_2E=256'ha338fec1_2e098106_a6387481_0c74822e_7480e4c0_082e9838_7480e4c0_52ded53f; +defparam bootram.RAM3.INIT_2F=256'h51fdfb3f_fea73f73_80e4c40c_2e8e3873_80e4c408_06963873_822e0981_3f9e3974; +defparam bootram.RAM3.INIT_30=256'h0b80e4c4_e4c00cff_3f800b80_0851879c_daa93f80_04fd3d0d_3f863d0d_995187c7; +defparam bootram.RAM3.INIT_31=256'he03f8451_528451e4_c73fbabd_529c5187_3f81ae80_985187d0_a63f8d52_0c995187; +defparam bootram.RAM3.INIT_32=256'h8d388008_7380082e_5186f43f_87aa3f84_53548451_f49f0670_08908007_87893f80; +defparam bootram.RAM3.INIT_33=256'h0d04fd3d_833f853d_52805187_08848007_86dd3f80_d63f8051_e0dc51e7_53735280; +defparam bootram.RAM3.INIT_34=256'h73109006_71730707_812a8806_2a840672_2a077183_82067187_3370852a_0d029705; +defparam bootram.RAM3.INIT_35=256'hff0682c0_2b077081_72077887_80c00670_0676852b_077081ff_06717307_74832ba0; +defparam bootram.RAM3.INIT_36=256'hff51ff9e_0a075381_0a0681d0_3d0d74d0_3d0d04fe_55555285_53515552_800c5152; +defparam bootram.RAM3.INIT_37=256'h813f7288_80e151ff_51ff873f_ff8c3fb2_3f819951_aa51ff92_ff983f81_3f81ff51; +defparam bootram.RAM3.INIT_38=256'h3f72982a_8151fee2_fee83f81_ed3fb251_ff0651fe_f53f7281_065252fe_2a7081ff; +defparam bootram.RAM3.INIT_39=256'h51febf3f_fec43f80_3f81a151_b051feca_53fecf3f_81ff0652_72902a70_51fedb3f; +defparam bootram.RAM3.INIT_3A=256'h04ffaf3d_3f843d0d_8051fea6_51feab3f_feb03fa0_b53f8051_3fa051fe_8e51feba; +defparam bootram.RAM3.INIT_3B=256'h9451e5bf_945280e1_38775382_82932690_58595777_08841208_0880da3d_0d80d83d; +defparam bootram.RAM3.INIT_3C=256'h80ca3875_7580e426_2e80e938_387580e4_80e62698_80cc3875_7580e62e_3f81d039; +defparam bootram.RAM3.INIT_3D=256'h81953975_2e80f738_387580f2_80f3268b_819b3875_7580f32e_3881ac39_80e12ea5; +defparam bootram.RAM3.INIT_3E=256'h8c943f80_3f800841_80398c90_08084181_d7d33f80_3980c15f_da38818b_80f72e80; +defparam bootram.RAM3.INIT_3F=256'h5f80d639_f93f80c5_e0055189_80d33dfd_8c170852_90170853_5f80ee39_084280c6; +defparam bootram.RAM4.INIT_00=256'h5fb73994_bc3980c2_3880c45f_75802e86_81ff0656_bb3f8008_e005518a_80d33dfd; +defparam bootram.RAM4.INIT_01=256'h528c1708_53901708_3dfe8005_a43980d3_3f80d75f_085188dd_08528c17_17539017; +defparam bootram.RAM4.INIT_02=256'hec055480_80d33dfd_5f829455_3f8339a0_8051fcff_3980d35f_80d25f8d_518bba3f; +defparam bootram.RAM4.INIT_03=256'h8251ec9b_ec388380_58887826_77348118_57577533_d53d7905_58771980_0b833d5a; +defparam bootram.RAM4.INIT_04=256'h028405ab_02a70533_3ff93d0d_ff518398_51d8e03f_0d80e1e0_0d04803d_3f80d33d; +defparam bootram.RAM4.INIT_05=256'h0d7a7c7f_0d04f83d_9e3f893d_528051e5_54755381_88805598_2b075757_05337188; +defparam bootram.RAM4.INIT_06=256'h58330284_76708105_738a3d34_81175754_25b73875_56548074_5874ff16_7f5a5757; +defparam bootram.RAM4.INIT_07=256'hef3f7380_548a51dd_0881ff06_dcc13f80_81ff0651_fc055277_82538a3d_05a10534; +defparam bootram.RAM4.INIT_08=256'hdc567588_56748338_335580de_0d02a305_0d04fa3d_800c8a3d_39815473_2e8538c1; +defparam bootram.RAM4.INIT_09=256'hab053389_0d7c5702_0d04f93d_893f883d_80d051ff_5381f752_883dfc05_3d348154; +defparam bootram.RAM4.INIT_0A=256'h802e9e38_70565473_0881ff06_dbe13f80_33705256_5202a705_893dfc05_3d348153; +defparam bootram.RAM4.INIT_0B=256'h5574800c_2e833881_56547380_81ff0670_a43f8008_527551da_3876537b_80772597; +defparam bootram.RAM4.INIT_0C=256'h56567480_0b883d33_ffa03f80_5280d051_055381f7_54883dfc_fa3d0d81_893d0d04; +defparam bootram.RAM4.INIT_0D=256'h0ca60b81_0b81c080_940c80eb_990b81c0_883d0d04_5675800c_06833881_de2e0981; +defparam bootram.RAM4.INIT_0E=256'h820b81c0_c0980c51_70810781_2bbe8006_3d0d7288_b00c0480_b00b81c0_c0ac0c89; +defparam bootram.RAM4.INIT_0F=256'h803d0d72_823d0d04_a808800c_f13881c0_51515170_2a708106_a4087081_a00c81c0; +defparam bootram.RAM4.INIT_10=256'h70812a70_81c0a408_81c0a00c_9c0c840b_517381c0_81c0980c_06708107_882bbe80; +defparam bootram.RAM4.INIT_11=256'h91387583_55575771_72830655_0d787a7c_ff39fa3d_823d0d04_5170f138_81065151; +defparam bootram.RAM4.INIT_12=256'h94387382_55737527_822a7255_88ca3f72_86388151_5271802e_38728306_0652718a; +defparam bootram.RAM4.INIT_13=256'h708f0680_7470842a_04fe3d0d_39883d0d_811454e9_0c525452_12700872_2b771177; +defparam bootram.RAM4.INIT_14=256'h803d0d82_843d0d04_53d3cf3f_ec113352_8f0680e1_d3dc3f72_54515353_e1ec1133; +defparam bootram.RAM4.INIT_15=256'hff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151_882a7081_e0900870; +defparam bootram.RAM4.INIT_16=256'h800c7182_387682e0_515170f1_70810651_0870882a_5382e090_c0800753_80060780; +defparam bootram.RAM4.INIT_17=256'h90087088_963882e0_5172802e_e0900c72_82800782_e0980c71_81ff0682_e0900c75; +defparam bootram.RAM4.INIT_18=256'he0940c88_0d810b82_0d04fc3d_800c843d_80085170_f13882e0_51515170_2a708106; +defparam bootram.RAM4.INIT_19=256'h81528151_548a8053_88805590_04fc3d0d_3f863d0d_8051ff87_80538052_80558854; +defparam bootram.RAM4.INIT_1A=256'hfed53f86_81528051_88548653_0d888055_0d04fc3d_800c863d_0881ff06_fef13f80; +defparam bootram.RAM4.INIT_1B=256'hff065170_3f800881_803d0deb_823d0d04_8106800c_80088132_3d0dca3f_3d0d0480; +defparam bootram.RAM4.INIT_1C=256'h8055a054_ffb43f88_9b38dd3f_75800826_5684e33f_fb3d0d77_823d0d04_802ef438; +defparam bootram.RAM4.INIT_1D=256'h80cb3d08_80c93d08_ffba3d0d_873d0d04_51fe843f_53815280_069b0a07_75fe9b0a; +defparam bootram.RAM4.INIT_1E=256'h805381ff_81a73882_73800826_54849f3f_b4387517_81ff2681_57805573_ff115657; +defparam bootram.RAM4.INIT_1F=256'h9f3f7482_fed43ffd_3ffefd3f_73518aea_cb3d0852_3f755380_52548c8f_52883d70; +defparam bootram.RAM4.INIT_20=256'h0c88a00b_0b82e098_e0800c81_c00a0782_c00a0680_900c76fe_800b82e0_e0980c88; +defparam bootram.RAM4.INIT_21=256'h0c54fe84_0882e08c_fe801570_3d558f56_ef3f80c8_e0900cfc_8aa00b82_82e0900c; +defparam bootram.RAM4.INIT_22=256'h88800b82_e0800c54_15700882_0c54fe8c_0882e084_fe881570_e0880c54_15700882; +defparam bootram.RAM4.INIT_23=256'he0980c81_38800b82_8025ffbc_16565675_3fff1690_900cfcb0_800b82e0_e0900c8a; +defparam bootram.RAM4.INIT_24=256'h082680cb_80577380_5682db3f_12575a56_797b7d72_04f93d0d_80c83d0d_5574800c; +defparam bootram.RAM4.INIT_25=256'h27833876_55577675_80743175_2ea23882_06547380_387581ff_802e80c3_38815774; +defparam bootram.RAM4.INIT_26=256'h807527e1_38745482_74802e8e_31575956_74197676_eb3f7316_527551fd_54775373; +defparam bootram.RAM4.INIT_27=256'h802e8d38_56545573_0d76787a_0d04fc3d_800c893d_3f815776_dc39fd8c_38828054; +defparam bootram.RAM4.INIT_28=256'hcb3f8008_0ca63981_160c8075_0c800b84_800b8816_74279038_ed3f8008_73135481; +defparam bootram.RAM4.INIT_29=256'h51fcc93f_88160c71_84160c71_760c7406_80083072_5281bd3f_ff165651_30707406; +defparam bootram.RAM4.INIT_2A=256'h14088415_38815388_71802e9f_06705452_800881ff_54fc983f_fd3d0d75_863d0d04; +defparam bootram.RAM4.INIT_2B=256'h0d04fc3d_800c853d_3f805372_0c51fc94_05708816_14088008_81823f88_082e9438; +defparam bootram.RAM4.INIT_2C=256'h04ff3d0d_0c863d0d_800a0680_3f8008fe_8151faa3_0a538152_a05481f9_0d888055; +defparam bootram.RAM4.INIT_2D=256'h81069338_70a02e09_06545151_800881ff_7081ff06_8008882a_a038d73f_80e4cc08; +defparam bootram.RAM4.INIT_2E=256'hc03f8008_833d0d04_3f71800c_8438f5b2_52827127_08ea1152_0c80e4cc_7180e4cc; +defparam bootram.RAM4.INIT_2F=256'h04f63d0d_082b800c_3f810b80_0c04ffa9_80082b80_f33f810b_33800c04_80e2c205; +defparam bootram.RAM4.INIT_30=256'he0800c81_7c882b82_82e0840c_900c8b0b_800b82e0_e0980c88_3f800b82_7d56f998; +defparam bootram.RAM4.INIT_31=256'h2780d338_80547376_e73f7e55_e0900cf8_8aa80b82_82e0900c_0c88a80b_0b82e098; +defparam bootram.RAM4.INIT_32=256'he084085a_88085982_085882e0_3f82e08c_900cf8cc_800b82e0_e0900c8a_88800b82; +defparam bootram.RAM4.INIT_33=256'h71175170_73279138_53805271_27833870_90537073_75315257_5b883d76_82e08008; +defparam bootram.RAM4.INIT_34=256'h803d0d72_8c3d0d04_82e0980c_a939800b_721454ff_1252ec39_05573481_33757081; +defparam bootram.RAM4.INIT_35=256'h3f800870_085182de_8c088805_8c050852_80538c08_0cfd3d0d_8c08028c_51f7893f; +defparam bootram.RAM4.INIT_36=256'h05085182_528c0888_088c0508_0d81538c_8c0cfd3d_048c0802_3d0d8c0c_800c5485; +defparam bootram.RAM4.INIT_37=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_0c048c08_853d0d8c_70800c54_b93f8008; +defparam bootram.RAM4.INIT_38=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025; +defparam bootram.RAM4.INIT_39=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4; +defparam bootram.RAM4.INIT_3A=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c; +defparam bootram.RAM4.INIT_3B=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80; +defparam bootram.RAM4.INIT_3C=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e; +defparam bootram.RAM4.INIT_3D=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c; +defparam bootram.RAM4.INIT_3E=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81; +defparam bootram.RAM4.INIT_3F=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05; +defparam bootram.RAM5.INIT_00=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; +defparam bootram.RAM5.INIT_01=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b; +defparam bootram.RAM5.INIT_02=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e; +defparam bootram.RAM5.INIT_03=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc; +defparam bootram.RAM5.INIT_04=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508; +defparam bootram.RAM5.INIT_05=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508; +defparam bootram.RAM5.INIT_06=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c; +defparam bootram.RAM5.INIT_07=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c; +defparam bootram.RAM5.INIT_08=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff; +defparam bootram.RAM5.INIT_09=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff; +defparam bootram.RAM5.INIT_0A=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414; +defparam bootram.RAM5.INIT_0B=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079; +defparam bootram.RAM5.INIT_0C=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081; +defparam bootram.RAM5.INIT_0D=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084; +defparam bootram.RAM5.INIT_0E=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553; +defparam bootram.RAM5.INIT_0F=256'h71028c05_3d0d7679_ff8339fc_ed387054_52718326_530cfc12_71708405_84055408; +defparam bootram.RAM5.INIT_10=256'h38737370_71ff2e93_38ff1252_70802ea2_74830651_72278a38_55535583_9f053357; +defparam bootram.RAM5.INIT_11=256'h7071902b_882b7507_0d047474_800c863d_06ef3874_ff2e0981_ff125271_81055534; +defparam bootram.RAM5.INIT_12=256'h530c7271_71708405_05530c72_72717084_8405530c_38727170_8f7227a5_07515451; +defparam bootram.RAM5.INIT_13=256'h718326f2_0cfc1252_70840553_90387271_38837227_718f26dd_0cf01252_70840553; +defparam bootram.RAM5.INIT_14=256'h5170802e_74078306_80d93871_5272802e_70545555_0d787a7c_9039fa3d_387053ff; +defparam bootram.RAM5.INIT_15=256'h81873870_3872802e_098106a9_5174712e_33743356_2eb13871_135372ff_80d438ff; +defparam bootram.RAM5.INIT_16=256'h33743356_06d13871_ff2e0981_55555272_8115ff15_fc388112_70802e80_81ff0651; +defparam bootram.RAM5.INIT_17=256'h27883871_57558373_0d047174_800c883d_51525270_06717131_067581ff_517081ff; +defparam bootram.RAM5.INIT_18=256'hff120670_09f7fbfd_38740870_72802eb1_39fc1353_5552ff97_88387476_0874082e; +defparam bootram.RAM5.INIT_19=256'hd0387476_0876082e_27d03874_57558373_84158417_51709a38_80065151_f8848281; +defparam bootram.RAM5.INIT_1A=256'h387380e4_72812e9e_9c085454_800b80e2_04fd3d0d_0c883d0d_39800b80_5552fedf; +defparam bootram.RAM5.INIT_1B=256'he4d00cff_a33f7280_800851f6_ffb9bb3f_dc528151_973f80e2_fb3fffb1_d00cffb1; +defparam bootram.RAM5.INIT_1C=256'h0d80e2e4_ff39ff3d_f6863f00_3f800851_51ffb99e_e2dc5281_b0fa3f80_b1de3fff; +defparam bootram.RAM5.INIT_1D=256'h833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138_08525270_0bfc0570; +defparam bootram.RAM5.INIT_1E=256'h6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_3f040000_04ffb289; +defparam bootram.RAM5.INIT_1F=256'h74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e_636b6574; +defparam bootram.RAM5.INIT_20=256'h21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d_6c697479; +defparam bootram.RAM5.INIT_21=256'h3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f_6f722069; +defparam bootram.RAM5.INIT_22=256'h7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070_70656374; +defparam bootram.RAM5.INIT_23=256'h70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000_74202564; +defparam bootram.RAM5.INIT_24=256'h6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000_203d2025; +defparam bootram.RAM5.INIT_25=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741_720a0000; +defparam bootram.RAM5.INIT_26=256'h756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d_640a0000; +defparam bootram.RAM5.INIT_27=256'h65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000_723a2025; +defparam bootram.RAM5.INIT_28=256'h000007cc_000007cc_000007cc_000007cc_00000650_00000000_65743a20_7061636b; +defparam bootram.RAM5.INIT_29=256'h000007cc_000007a2_000007cc_000007cc_000006a5_000006bd_000007cc_000007cc; +defparam bootram.RAM5.INIT_2A=256'h00000778_000007cc_0000065d_00000715_000007cc_000006d3_000007cc_000007cc; +defparam bootram.RAM5.INIT_2B=256'h45000000_01b200d9_05160364_14580a2c_3fff0000_0050c285_c0a80a02_00000751; +defparam bootram.RAM5.INIT_2C=256'h00000000_43444546_38394142_34353637_30313233_2e256400_642e2564_25642e25; +defparam bootram.RAM5.INIT_2D=256'h656e7420_69676e6d_6420616c_3a206261_5f706b74_73656e64_ffff0000_ffffffff; +defparam bootram.RAM5.INIT_2E=256'h6f6e3a20_636f6d6d_6e65745f_66000000_72206275_6e642f6f_656e2061_6f66206c; +defparam bootram.RAM5.INIT_2F=256'h666f7220_696e6720_6c6f6f6b_63686520_74206361_6f206869_65642074_6661696c; +defparam bootram.RAM5.INIT_30=256'h3d202564_697a6520_72642073_20776569_6172703a_646c655f_0a68616e_00000000; +defparam bootram.RAM5.INIT_31=256'h3a202564_67746873_206c656e_74656e74_6e736973_696e636f_55445020_0a000000; +defparam bootram.RAM5.INIT_32=256'h696e2073_50322b20_20555352_74696e67_53746172_0b0b0b0b_00000000_2025640a; +defparam bootram.RAM5.INIT_33=256'h6172652e_69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465_61666520; +defparam bootram.RAM5.INIT_34=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_00000000; +defparam bootram.RAM5.INIT_35=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; +defparam bootram.RAM5.INIT_36=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; +defparam bootram.RAM5.INIT_37=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; +defparam bootram.RAM5.INIT_38=256'h6820746f_726f7567_67207468_6c6c696e_2e0a4661_6f756e64_67652066_20696d61; +defparam bootram.RAM5.INIT_39=256'h6f647563_64207072_56616c69_72652e00_726d7761_6e206669_6c742d69_20627569; +defparam bootram.RAM5.INIT_3A=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e; +defparam bootram.RAM5.INIT_3B=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69; +defparam bootram.RAM5.INIT_3C=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000; +defparam bootram.RAM5.INIT_3D=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; +defparam bootram.RAM5.INIT_3E=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; +defparam bootram.RAM5.INIT_3F=256'h2d696e20_75696c74_746f2062_75676820_7468726f_696e6720_46616c6c_6e642e20; +defparam bootram.RAM6.INIT_00=256'h00000000_2025640a_7420746f_64207365_53706565_2e000000_77617265_6669726d; +defparam bootram.RAM6.INIT_01=256'h45545249_53594d4d_58000000_57455f52_58000000_57455f54_00000000_4e4f4e45; +defparam bootram.RAM6.INIT_02=256'h5048595f_6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865_43000000; +defparam bootram.RAM6.INIT_03=256'h20307825_20676f74_7825782c_74652030_2077726f_4144563a_4e45475f_4155544f; +defparam bootram.RAM6.INIT_04=256'h6e207570_6f722069_21457272_00030203_00000001_00030003_00000000_780a0000; +defparam bootram.RAM6.INIT_05=256'h64207061_65637465_20457870_6c65723a_68616e64_6b657420_20706163_64617465; +defparam bootram.RAM6.INIT_06=256'h00000000_2025640a_20676f74_20627574_2025642c_6e677468_64206c65_796c6f61; +defparam bootram.RAM6.INIT_07=256'h64756d6d_43444546_38394142_34353637_30313233_00000000_6f72740a_0a0a6162; +defparam bootram.RAM6.INIT_08=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_65000000_792e6578; +defparam bootram.RAM6.INIT_09=256'hffff0031_05050400_01010100_3fff0000_0050c285_c0a80a02_0000316c_00000000; +defparam bootram.RAM6.INIT_0A=256'h000030fc_10101200_00003038_00003030_00003028_00003020_000b0000_0018000f; +defparam bootram.RAM6.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff; +defparam bootram.RAM6.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v index ec54de73e..ee5d7efcd 100644 --- a/fpga/usrp2/top/u2plus/u2plus_core.v +++ b/fpga/usrp2/top/u2plus/u2plus_core.v @@ -131,18 +131,22 @@ module u2plus_core output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi ); - localparam SR_MISC = 0; // Uses 9 regs - localparam SR_BUF_POOL = 64; // Uses 4 regs - localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP0 = 160; // 16 - localparam SR_RX_CTRL0 = 176; // 16 - localparam SR_TIME64 = 192; // 3 - localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 208; // 16 - localparam SR_TX_CTRL = 224; // 16 - localparam SR_RX_DSP1 = 240; - localparam SR_RX_CTRL1 = 32; - + localparam SR_MISC = 0; // 7 regs + localparam SR_SIMTIMER = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_UDP_SM = 192; // 64 // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs @@ -203,22 +207,22 @@ module u2plus_core wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; wb_1master #(.decode_w(8), - .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM - .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // 16K-20K, Buffer Pool - .s2_addr(8'b0110_0000),.s2_mask(8'b1111_1111), // SPI - .s3_addr(8'b0110_0001),.s3_mask(8'b1111_1111), // I2C - .s4_addr(8'b0110_0010),.s4_mask(8'b1111_1111), // GPIO - .s5_addr(8'b0110_0011),.s5_mask(8'b1111_1111), // Readback - .s6_addr(8'b0110_0100),.s6_mask(8'b1111_1111), // Ethernet MAC - .s7_addr(8'b0101_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) - .s8_addr(8'b0110_0101),.s8_mask(8'b1111_1111), // PIC - .s9_addr(8'b0110_0110),.s9_mask(8'b1111_1111), // Unused - .sa_addr(8'b0110_0111),.sa_mask(8'b1111_1111), // UART - .sb_addr(8'b0110_1000),.sb_mask(8'b1111_1111), // ATR - .sc_addr(8'b0110_1001),.sc_mask(8'b1111_1111), // Unused - .sd_addr(8'b0110_1010),.sd_mask(8'b1111_1111), // ICAP - .se_addr(8'b0110_1011),.se_mask(8'b1111_1111), // SPI Flash - .sf_addr(8'b1000_0000),.sf_mask(8'b1100_0000), // 32-48K, Main RAM + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // ICAP + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // SPI Flash + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // 48K-64K, Boot RAM .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), @@ -256,55 +260,47 @@ module u2plus_core .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - ////////////////////////////////////////////////////////////////////////////////////////// + // //////////////////////////////////////////////////////////////////////////////////////// // Reset Controller - reg cpu_bldr_ctrl_state; - localparam CPU_BLDR_CTRL_WAIT = 0; - localparam CPU_BLDR_CTRL_DONE = 1; - - wire bldr_done; - wire por_rst; - wire [aw-1:0] cpu_adr; - wire [aw-1:0] cpu_sp_init = (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)? - 16'hfff8 : //top of 8K boot ram re-purposed at 56K - 16'h1ff8 ; //top of 8K boot ram - - //When the main program runs, it will try to access system ram at 0. - //This logic re-maps the cpu address to force select the system ram. - assign m0_adr = - (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_WAIT)? cpu_adr : ( //in bootloader - (cpu_adr[15:14] == 2'b00)? {2'b10, cpu_adr[13:0]} : ( //map 0-16 to 32-48 (main ram) - (cpu_adr[15:13] == 3'b111)? {3'b000, cpu_adr[12:0]} : ( //map 56-64 to 0-8 (boot ram) - cpu_adr))); //otherwise - - system_control sysctrl ( - .wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) - ); - - always @(posedge wb_clk) - if(por_rst) begin + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + wire por_rst; + wire [aw-1:0] cpu_adr; + + // Swap boot ram and main ram when in bootloader mode + assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr : + cpu_adr ^ 16'hC000; + + system_control sysctrl + (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) ); + + always @(posedge wb_clk) + if(por_rst) begin cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; wb_rst <= 1'b1; - end - else begin + end + else begin case(cpu_bldr_ctrl_state) - - CPU_BLDR_CTRL_WAIT: begin - wb_rst <= 1'b0; - if (bldr_done == 1'b1) begin //set by the bootloader + + CPU_BLDR_CTRL_WAIT: begin + wb_rst <= 1'b0; + if (bldr_done == 1'b1) begin //set by the bootloader cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; wb_rst <= 1'b1; - end - end - - CPU_BLDR_CTRL_DONE: begin //stay here forever - wb_rst <= 1'b0; - end - + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + wb_rst <= 1'b0; + end + endcase //cpu_bldr_ctrl_state - end - + end + // ///////////////////////////////////////////////////////////////////////// // Processor @@ -317,18 +313,17 @@ module u2plus_core .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .stack_start(cpu_sp_init), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); - - + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + // ///////////////////////////////////////////////////////////////////////// // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone // I-port connects directly to processor bootram bootram(.clk(wb_clk), .reset(wb_rst), - .if_adr(13'b0), .if_data(), - .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + .if_adr(14'b0), .if_data(), + .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); ////blinkenlights v0.1 //defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; @@ -339,8 +334,8 @@ module u2plus_core ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .if_adr(14'b0), .if_data(), - .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), - .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); + .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool, slave #1 @@ -416,7 +411,7 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd5; + localparam compat_num = 32'd6; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -433,7 +428,7 @@ module u2plus_core // Ethernet MAC Slave #6 simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19 + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), @@ -477,7 +472,7 @@ module u2plus_core .in(set_data),.out(adc_outs),.changed()); setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phy_reset),.changed()); - setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(bldr_done),.changed()); // ///////////////////////////////////////////////////////////////////////// @@ -492,7 +487,7 @@ module u2plus_core setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(SR_MISC+8),.width(8), .at_reset(8'b0001_1110)) + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v index c642842f6..b4f6e55b8 100644 --- a/fpga/usrp2/udp/prot_eng_tx.v +++ b/fpga/usrp2/udp/prot_eng_tx.v @@ -1,146 +1,110 @@ -// The input FIFO contents should be 16 bits wide -// The first word is 1 for fast path (accelerated protocol) -// 0 for software implemented protocol -// The second word is the number of bytes in the packet, -// and must be valid even if we are in slow path mode -// Odd means the last word is half full -// Flags[1:0] is {eop, sop} -// Protocol word format is: -// 21 UDP Source Port Here -// 20 UDP Dest Port Here -// 19 Last Header Line -// 18 IP Header Checksum XOR -// 17 IP Length Here -// 16 UDP Length Here -// 15:0 data word to be sent - module prot_eng_tx #(parameter BASE=0) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [18:0] datain, input src_rdy_i, output dst_rdy_o, - output [18:0] dataout, output src_rdy_o, input dst_rdy_i); - - wire [2:0] flags_i = datain[18:16]; - reg [15:0] dataout_int; - reg fast_path, sof_o; - - wire [2:0] flags_o = {flags_i[2], flags_i[1], sof_o}; // OCC, EOF, SOF + input [35:0] datain, input src_rdy_i, output dst_rdy_o, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i); - assign dataout = {flags_o[2:0], dataout_int[15:0]}; + wire src_rdy_int1, dst_rdy_int1; + wire src_rdy_int2, dst_rdy_int2; + wire [35:0] data_int1, data_int2; - reg [4:0] state; - wire do_payload = (state == 31); - - assign dst_rdy_o = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30)); - assign src_rdy_o = src_rdy_i & ~((state==0) | (state==1) | (state==30)); - - localparam HDR_WIDTH = 16 + 6; // 16 bits plus flags - localparam HDR_LEN = 32; // Up to 64 bytes of protocol + // Shortfifo on input to guarantee no deadlock + fifo_short #(.WIDTH(36)) head_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1), + .space(),.occupied() ); // Store header values in a small dual-port (distributed) ram - reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1]; - wire [HDR_WIDTH-1:0] header_word; - - reg [1:0] port_sel; - reg [31:0] per_port_data[0:3]; - reg [15:0] udp_src_port, udp_dst_port, chk_precompute; - - always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16]; - always @(posedge clk) udp_dst_port <= per_port_data[port_sel][15:0]; - + reg [31:0] header_ram[0:63]; + reg [3:0] state; + reg [1:0] port_sel; + always @(posedge clk) - if(set_stb & ((set_addr & 8'hE0) == BASE)) - header_ram[set_addr[4:0]] <= set_data; + if(set_stb & ((set_addr & 8'hC0) == BASE)) + header_ram[set_addr[5:0]] <= set_data; - always @(posedge clk) - if(set_stb & (set_addr == (BASE + 14))) - chk_precompute <= set_data[15:0]; + wire [31:0] header_word = header_ram[{port_sel[1:0],state[3:0]}]; + reg [15:0] pre_checksums [0:3]; always @(posedge clk) - if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) - per_port_data[set_addr[1:0]] <= set_data; - - wire do_udp_src_port = header_word[21]; - wire do_udp_dst_port = header_word[20]; - wire last_hdr_line = header_word[19]; - wire do_ip_chk = header_word[18]; - wire do_ip_len = header_word[17]; - wire do_udp_len = header_word[16]; + if(set_stb & ((set_addr & 8'hCF)== (BASE+7))) + pre_checksums[set_addr[5:4]] <= set_data[15:0]; + + wire [15:0] pre_checksum = pre_checksums[port_sel[1:0]]; - assign header_word = header_ram[state]; - // Protocol State Machine reg [15:0] length; wire [15:0] ip_length = length + 28; // IP HDR + UDP HDR wire [15:0] udp_length = length + 8; // UDP HDR - + reg sof_o; + reg [31:0] prot_data; + always @(posedge clk) if(reset) begin - state <= 0; - fast_path <= 0; + state <= 0; sof_o <= 0; end else - if(src_rdy_i & dst_rdy_i) + if(src_rdy_int1 & dst_rdy_int2) case(state) 0 : begin - fast_path <= datain[0]; - port_sel <= datain[2:1]; - state <= 1; - end - 1 : - begin - length <= datain[15:0]; + port_sel <= data_int1[18:17]; + length <= data_int1[15:0]; sof_o <= 1; - if(fast_path) - state <= 2; + if(data_int1[16]) + state <= 1; else - state <= 30; // Skip 1 word for alignment + state <= 12; end - 30 : - state <= 31; - 31 : + 12 : begin sof_o <= 0; - if(flags_i[1]) // eop + if(data_int1[33]) // eof state <= 0; end default : begin sof_o <= 0; - if(~last_hdr_line) - state <= state + 1; - else - state <= 31; + state <= state + 1; end endcase // case (state) - wire [15:0] checksum; + wire [15:0] ip_checksum; add_onescomp #(.WIDTH(16)) add_onescomp - (.A(chk_precompute),.B(ip_length),.SUM(checksum)); - - reg [15:0] checksum_reg; - always @(posedge clk) - checksum_reg <= checksum; + (.A(pre_checksum),.B(ip_length),.SUM(ip_checksum)); + reg [15:0] ip_checksum_reg; + always @(posedge clk) ip_checksum_reg <= ip_checksum; always @* - if(do_payload) - dataout_int <= datain[15:0]; - else if(do_ip_chk) - dataout_int <= 16'hFFFF ^ checksum_reg; - else if(do_ip_len) - dataout_int <= ip_length; - else if(do_udp_len) - dataout_int <= udp_length; - else if(do_udp_src_port) - dataout_int <= udp_src_port; - else if(do_udp_dst_port) - dataout_int <= udp_dst_port; - else - dataout_int <= header_word[15:0]; + case(state) + 1 : prot_data <= header_word; // ETH, top half ignored + 2 : prot_data <= header_word; // ETH + 3 : prot_data <= header_word; // ETH + 4 : prot_data <= header_word; // ETH + 5 : prot_data <= { header_word[31:16], ip_length }; // IP + 6 : prot_data <= header_word; // IP + 7 : prot_data <= { header_word[31:16], (16'hFFFF ^ ip_checksum_reg) }; // IP + 8 : prot_data <= header_word; // IP + 9 : prot_data <= header_word; // IP + 10: prot_data <= header_word; // UDP + 11: prot_data <= { udp_length, header_word[15:0]}; // UDP + default : prot_data <= data_int1[31:0]; + endcase // case (state) + + assign data_int2 = { data_int1[35:33] & {3{state[3]}}, sof_o, prot_data }; + assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12)); + assign src_rdy_int2 = src_rdy_int1 & (state != 0); + + // Shortfifo on output to guarantee no deadlock + fifo_short #(.WIDTH(36)) tail_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2), + .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), + .space(),.occupied() ); endmodule // prot_eng_tx diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v index c8fffe605..138794e57 100644 --- a/fpga/usrp2/udp/prot_eng_tx_tb.v +++ b/fpga/usrp2/udp/prot_eng_tx_tb.v @@ -8,40 +8,45 @@ module prot_eng_tx_tb(); always #50 clk = ~clk; reg [31:0] f36_data; - reg [1:0] f36_occ; - reg f36_sof, f36_eof; - + reg [1:0] f36_occ; + reg f36_sof, f36_eof; wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; - reg src_rdy_f36i = 0; - reg [15:0] count; + reg src_rdy_f36i = 0; + wire dst_rdy_f36i; + wire [35:0] casc_do; - wire [18:0] final_out, prot_out; + wire src_rdy_f36o, dst_rdy_f36o; - wire src_rdy_final, dst_rdy_final, src_rdy_prot; - reg dst_rdy_prot =0; - - wire dst_rdy_f36o ; - fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), - .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o)); + wire [35:0] prot_out; + wire src_rdy_prot, dst_rdy_prot; - fifo36_to_fifo19 fifo_converter - (.clk(clk),.reset(rst),.clear(clear), - .f36_datain(casc_do),.f36_src_rdy_i(src_rdy_f36o),.f36_dst_rdy_o(dst_rdy_f36o), - .f19_dataout(final_out),.f19_src_rdy_o(src_rdy_final),.f19_dst_rdy_i(dst_rdy_final)); + wire [35:0] realign_out; + wire src_rdy_realign; + reg dst_rdy_realign = 1; + + reg [15:0] count; reg set_stb; reg [7:0] set_addr; reg [31:0] set_data; + fifo_short #(.WIDTH(36)) fifo_cascade36 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), + .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o)); + prot_eng_tx #(.BASE(BASE)) prot_eng_tx - (.clk(clk), .reset(rst), + (.clk(clk), .reset(rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .datain(final_out[18:0]),.src_rdy_i(src_rdy_final),.dst_rdy_o(dst_rdy_final), - .dataout(prot_out[18:0]),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot)); - + .datain(casc_do),.src_rdy_i(src_rdy_f36o),.dst_rdy_o(dst_rdy_f36o), + .dataout(prot_out),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot)); + + ethtx_realign ethtx_realign + (.clk(clk), .reset(rst), .clear(0), + .datain(prot_out),.src_rdy_i(src_rdy_prot),.dst_rdy_o(dst_rdy_prot), + .dataout(realign_out),.src_rdy_o(src_rdy_realign),.dst_rdy_i(dst_rdy_realign)); + reg [35:0] printer; task WriteSREG; @@ -58,17 +63,22 @@ module prot_eng_tx_tb(); end endtask // WriteSREG + always @(posedge clk) + if(src_rdy_realign) + $display("Read: %h",realign_out); + + task ReadFromFIFO36; begin $display("Read from FIFO36"); - #1 dst_rdy_prot <= 1; + #1 dst_rdy_realign <= 1; while(~src_rdy_prot) @(posedge clk); while(1) begin while(~src_rdy_prot) @(posedge clk); - $display("Read: %h",prot_out); + $display("Read: %h",realign_out); @(posedge clk); end end @@ -80,7 +90,7 @@ module prot_eng_tx_tb(); begin count <= 4; src_rdy_f36i <= 1; - f36_data <= 32'h0003_000c; + f36_data <= 32'h0001_000c; f36_sof <= 1; f36_eof <= 0; f36_occ <= 0; @@ -132,37 +142,34 @@ module prot_eng_tx_tb(); begin #10000; @(posedge clk); - ReadFromFIFO36; + //ReadFromFIFO36; end initial begin @(negedge rst); @(posedge clk); - WriteSREG(BASE, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+1, {11'b0, 5'h00, 16'h0000}); - WriteSREG(BASE+2, {11'b0, 5'h00, 16'hABCD}); - WriteSREG(BASE+3, {11'b0, 5'h00, 16'h1234}); - WriteSREG(BASE+4, {11'b0, 5'h00, 16'h5678}); - WriteSREG(BASE+5, {11'b0, 5'h00, 16'hF00D}); - WriteSREG(BASE+6, {11'b0, 5'h00, 16'hBEEF}); - WriteSREG(BASE+7, {11'b0, 5'h10, 16'hDCBA}); - WriteSREG(BASE+8, {11'b0, 5'h00, 16'h4321}); - WriteSREG(BASE+9, {11'b0, 5'h04, 16'hABCD}); - WriteSREG(BASE+10, {11'b0, 5'h08, 16'hABCD}); + WriteSREG(BASE, 32'h89AB_CDEF); + WriteSREG(BASE+1, 32'h1111_2222); + WriteSREG(BASE+2, 32'h3333_4444); + WriteSREG(BASE+3, 32'h5555_6666); + WriteSREG(BASE+4, 32'h7777_8888); + WriteSREG(BASE+5, 32'h9999_aaaa); + WriteSREG(BASE+6, 32'hbbbb_cccc); + WriteSREG(BASE+7, 32'hdddd_eeee); + WriteSREG(BASE+8, 32'h0f0f_0011); + WriteSREG(BASE+9, 32'h0022_0033); + WriteSREG(BASE+10, 32'h0044_0055); + WriteSREG(BASE+11, 32'h0066_0077); + WriteSREG(BASE+12, 32'h0088_0099); @(posedge clk); - WriteSREG(BASE+24, 16'h6666); - WriteSREG(BASE+25, 16'h7777); - WriteSREG(BASE+26, 16'h8888); - WriteSREG(BASE+27, 16'h9999); - PutPacketInFIFO36(32'hA0B0C0D0,16); @(posedge clk); @(posedge clk); #10000; @(posedge clk); - PutPacketInFIFO36(32'hE0F0A0B0,36); + //PutPacketInFIFO36(32'hE0F0A0B0,36); @(posedge clk); @(posedge clk); @(posedge clk); diff --git a/fpga/usrp2/vrt/trigger_context_pkt.v b/fpga/usrp2/vrt/trigger_context_pkt.v index 226ec45f2..1d456814b 100644 --- a/fpga/usrp2/vrt/trigger_context_pkt.v +++ b/fpga/usrp2/vrt/trigger_context_pkt.v @@ -10,7 +10,7 @@ module trigger_context_pkt wire [15:0] packets; wire [6:0] dummy1; wire [14:0] dummy2; - wire enable_timed, enable_consumed; + wire enable_cycle, enable_consumed; reg [30:0] cycle_count, packet_count; diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index d7498286d..28955d108 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -2,7 +2,8 @@ module vita_rx_chain #(parameter BASE=0, parameter UNIT=0, - parameter FIFOSIZE=10) + parameter FIFOSIZE=10, + parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, output overrun, @@ -15,7 +16,7 @@ module vita_rx_chain wire [31:0] vrc_debug, vrf_debug; wire [35:0] rx_data_int; - wire rx_src_rdy_int, rx_dst_rdy_in; + wire rx_src_rdy_int, rx_dst_rdy_int; vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), @@ -32,7 +33,9 @@ module vita_rx_chain .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .debug_rx(vrf_debug) ); - dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT)) dsp0_framer36 + dsp_framer36 #(.BUF_SIZE(FIFOSIZE), + .PORT_SEL(UNIT), + .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp0_framer36 (.clk(clk), .reset(reset), .clear(clear), .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v index 6f567668d..fa84d7a2f 100644 --- a/fpga/usrp2/vrt/vita_tx_chain.v +++ b/fpga/usrp2/vrt/vita_tx_chain.v @@ -27,16 +27,17 @@ module vita_tx_chain wire trigger, sent; wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire error, packet_consumed; + wire error, packet_consumed, ack; wire [31:0] error_code; wire clear_seqnum; wire [31:0] current_seqnum; + wire strobe_tx; assign underrun = error; assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+1)) sr - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_vita)); setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v index e966d987c..14b97a215 100644 --- a/fpga/usrp2/vrt/vita_tx_control.v +++ b/fpga/usrp2/vrt/vita_tx_control.v @@ -71,7 +71,7 @@ module vita_tx_control wire [31:0] error_policy; setting_reg #(.my_addr(BASE+3)) sr_error_policy - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(error_policy),.changed()); wire policy_wait = error_policy[0]; diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v index eb39feaec..163c2af20 100644 --- a/fpga/usrp2/vrt/vita_tx_deframer.v +++ b/fpga/usrp2/vrt/vita_tx_deframer.v @@ -38,8 +38,8 @@ module vita_tx_deframer assign has_secs = ~(data_i[23:22]==2'b00); assign has_tics = ~(data_i[21:20]==2'b00); assign has_trailer = data_i[26]; - assign is_sob = data_i[25]; - assign is_eob = data_i[24]; + wire is_sob = data_i[25]; + wire is_eob = data_i[24]; wire eof = data_i[33]; reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg; reg has_trailer_reg, is_sob_reg, is_eob_reg; |