diff options
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/top/x400/Makefile | 101 |
1 files changed, 61 insertions, 40 deletions
diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile index 5098e58b1..ce5134932 100644 --- a/fpga/usrp3/top/x400/Makefile +++ b/fpga/usrp3/top/x400/Makefile @@ -1,20 +1,20 @@ # -# Copyright 2021 Ettus Research, a National Instruments Brand +# Copyright 2022 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # # NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target ##------------------- -##USRP X4XX FPGA Help +##USRP X4xx FPGA Help ##------------------- ##Usage: -## make <Targets> <Options> +## make <Targets> <Options> ## ##Output: -## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header -## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file -## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary) +## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header +## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file +## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary) @@ -47,8 +47,8 @@ X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 DRAM_CH=4*$(D X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=0 -X410_CG_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_CG_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_C1_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_C1_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 @@ -100,67 +100,87 @@ endif vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" ## -##Supported Targets -##----------------- - -all: X410_X4_200 ##(Default target) +##Available Targets +##------------|-----------|-----------------|-----------------|------------ +##Target | Bandwidth | QSFP0 | QSFP1 | DRAM +##------------|-----------|-----------------|-----------------|------------ +##X410_X1_100 | 100 MHz | 10 GbE (Lane 0) | None | 64b x 4 Ch +##X410_XG_100 | 100 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch +##X410_X4_100 | 100 MHz | 4 x 10 GbE | None | 64b x 4 Ch +##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | None | 64b x 4 Ch +##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch +##X410_X4_200 | 200 MHz | 4 x 10 GbE | None | 64b x 4 Ch +##X410_C1_400 | 400 MHz | 100 GbE | None | None +##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | None +##* Note: Not all targets are shipped with UHD -##X410_X1_100: 10GbE on QSFP0 (Lane 0), 100MHz Bandwidth X410_X1_100: build/usrp_x410_fpga_X1_100.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call post_build,X410,X1_100) -##X410_XG_100: 10GbE on QSFP0 (Lane 0) and QSFP1 (Lane 0), 100MHz Bandwidth X410_XG_100: build/usrp_x410_fpga_XG_100.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call post_build,X410,XG_100) -##X410_X4_100: 4x10GbE on QSFP0, 100MHz Bandwidth X410_X4_100: build/usrp_x410_fpga_X4_100.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) $(call post_build,X410,X4_100) -##X410_X4C_100: (EXPERIMENTAL) 4x10GbE on QSFP0, 100GbE on QSFP1, 100MHz Bandwidth -X410_X4C_100: build/usrp_x410_fpga_X4C_100.dts - $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) - $(call post_build,X410,X4C_100) - -##X410_CG_100: (EXPERIMENTAL) 100GbE on QSFP0, 100MHz Bandwidth -X410_CG_100: build/usrp_x410_fpga_CG_100.dts - $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) - $(call post_build,X410,CG_100) +X410_X1_200: build/usrp_x410_fpga_X1_200.dts + $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) + $(call post_build,X410,X1_200) -##X410_XG_200: 10GbE on QSFP0 (Lane 0) and QSFP1 (Lane 0), 200MHz Bandwidth X410_XG_200: build/usrp_x410_fpga_XG_200.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) $(call post_build,X410,XG_200) -##X410_X4_200: 4x10GbE on QSFP0, 200MHz Bandwidth X410_X4_200: build/usrp_x410_fpga_X4_200.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) $(call post_build,X410,X4_200) -##X410_X4C_200: (EXPERIMENTAL) 4x10GbE on QSFP0, 100GbE on QSFP1, 200MHz Bandwidth -X410_X4C_200: build/usrp_x410_fpga_X4C_200.dts - $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) - $(call post_build,X410,X4C_200) - -##X410_CG_200: (EXPERIMENTAL) 100GbE on QSFP0, 200MHz Bandwidth -X410_CG_200: build/usrp_x410_fpga_CG_200.dts - $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) - $(call post_build,X410,CG_200) - -##X410_C1_400: (EXPERIMENTAL) 100GbE on QSFP0, 400MHz Bandwidth X410_C1_400: build/usrp_x410_fpga_C1_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) $(call post_build,X410,C1_400) -##X410_CG_400: (EXPERIMENTAL) 100GbE on QSFP0 and QSFP1, 400MHz Bandwidth X410_CG_400: build/usrp_x410_fpga_CG_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) $(call post_build,X410,CG_400) -X410_IP: ##Build IPs only +## +##Experimental Targets +##-------------|-----------|----------------|----------------|------------ +##Target | Bandwidth | QSFP0 | QSFP1 | DRAM +##-------------|-----------|----------------|----------------|------------ +##X410_X4C_100 | 100 | 4 x 10 GbE | 100GbE | None +##X410_C1_100 | 100 | 100 GbE | None | 64b x 4 Ch +##X410_X4C_200 | 200 | 4 x 10 GbE | 100GbE | None +##X410_C1_200 | 200 | 100 GbE | None | 64b x 4 Ch + +X410_X4C_100: build/usrp_x410_fpga_X4C_100.dts + $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) + $(call post_build,X410,X4C_100) + +X410_C1_100: build/usrp_x410_fpga_CG_100.dts + $(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS)) + $(call post_build,X410,CG_100) + +X410_C1_200: build/usrp_x410_fpga_CG_200.dts + $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) + $(call post_build,X410,CG_200) + +X410_X4C_200: build/usrp_x410_fpga_X4C_200.dts + $(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS)) + $(call post_build,X410,X4C_200) + +## +##Other Make Targets +##------------------ + +.DEFAULT_GOAL := all + +all: X410_X4_200 X410_CG_400 ##(Default targets) + +X410_IP: ##Build IP only. $(call vivado_ip,X410,$(DEFS) X410=1) build/%.dts: dts/*.dts dts/*.dtsi @@ -177,7 +197,7 @@ clean: ##Clean up all target build outputs. @rm -rf build-X4* @rm -rf build -cleanall: ##Clean up all target and ip build outputs. +cleanall: ##Clean up all target and IP build outputs. @echo "Cleaning targets and IP..." @rm -rf build-ip @rm -rf build-X4* @@ -189,6 +209,7 @@ help: ##Show this help message. ## ##Supported Options ##----------------- +##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build. ##GUI=1 Launch the build in the Vivado GUI. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. |