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-rw-r--r--fpga/usrp3/top/n3xx/mb_timing.xdc5
1 files changed, 2 insertions, 3 deletions
diff --git a/fpga/usrp3/top/n3xx/mb_timing.xdc b/fpga/usrp3/top/n3xx/mb_timing.xdc
index 6aa3f8132..95265acee 100644
--- a/fpga/usrp3/top/n3xx/mb_timing.xdc
+++ b/fpga/usrp3/top/n3xx/mb_timing.xdc
@@ -106,6 +106,5 @@ set_max_delay -from $PORT_LIST 50.000
set_min_delay -from $PORT_LIST 0.000
#******************************************************************************
-## Reset Sync False Path
-set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/D]
-set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/C]
+## Synchronizer false paths
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}]