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-rw-r--r--fpga/usrp3/top/x400/Makefile.x4xx.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/top/x400/Makefile.x4xx.inc b/fpga/usrp3/top/x400/Makefile.x4xx.inc
index 3bcbe38cd..d031d7e83 100644
--- a/fpga/usrp3/top/x400/Makefile.x4xx.inc
+++ b/fpga/usrp3/top/x400/Makefile.x4xx.inc
@@ -170,7 +170,7 @@ $(WB_SPI_SRCS) $(RFNOC_XPORT_SV_SRCS) \
# Pass the edge table and image core header files required by RFNoC
# to Vivado as Verilog definitions.
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
-IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)"
+IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
# Dependency Targets