diff options
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs | 15 | ||||
| -rw-r--r-- | fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf | 0 | ||||
| -rw-r--r-- | fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf | 0 |
3 files changed, 15 insertions, 0 deletions
diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs new file mode 100644 index 000000000..032a35f41 --- /dev/null +++ b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated --> +<!-- by the Xilinx ISE software. Any direct editing or --> +<!-- changes made to this file may result in unpredictable --> +<!-- behavior or data corruption. It is strongly advised that --> +<!-- users do not edit the contents of this file. --> +<!-- --> +<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> + +<messages> +<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file "/home/jblum/uhdpriv/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v" into library work</arg> +</msg> + +</messages> + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf |