summaryrefslogtreecommitdiffstats
path: root/fpga
diff options
context:
space:
mode:
Diffstat (limited to 'fpga')
-rw-r--r--fpga/usrp2/control_lib/Makefile.srcs2
-rw-r--r--fpga/usrp2/control_lib/settings_bus_crossclock.v9
-rw-r--r--fpga/usrp2/control_lib/settings_fifo_ctrl.v392
-rw-r--r--fpga/usrp2/control_lib/simple_spi_core.v214
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise4
-rw-r--r--fpga/usrp2/fifo/Makefile.srcs1
-rw-r--r--fpga/usrp2/fifo/packet_dispatcher36_x4.v316
-rw-r--r--fpga/usrp2/fifo/packet_router.v23
-rw-r--r--fpga/usrp2/top/N2x0/bootloader.rmi780
-rw-r--r--fpga/usrp2/top/N2x0/u2plus_core.v86
-rw-r--r--fpga/usrp2/top/USRP2/Makefile2
-rw-r--r--fpga/usrp2/top/USRP2/u2_core.v95
-rw-r--r--fpga/usrp2/vrt/vita_rx_framer.v8
-rw-r--r--fpga/usrp2/vrt/vita_tx_deframer.v3
14 files changed, 1488 insertions, 447 deletions
diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index 6ee7ea262..0bb9a3efe 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -55,4 +55,6 @@ atr_controller16.v \
fifo_to_wb.v \
gpio_atr.v \
user_settings.v \
+settings_fifo_ctrl.v \
+simple_spi_core.v \
))
diff --git a/fpga/usrp2/control_lib/settings_bus_crossclock.v b/fpga/usrp2/control_lib/settings_bus_crossclock.v
index 9c5912042..a61ee8fad 100644
--- a/fpga/usrp2/control_lib/settings_bus_crossclock.v
+++ b/fpga/usrp2/control_lib/settings_bus_crossclock.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -22,16 +22,17 @@
// the system or dsp clock on the output side
module settings_bus_crossclock
+ #(parameter FLOW_CTRL=0)
(input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i,
- input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o);
+ input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o, input blocked);
wire full, empty;
fifo_xlnx_16x40_2clk settings_fifo
(.rst(rst_i),
.wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full),
- .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(~empty), .empty(empty));
+ .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(set_stb_o), .empty(empty));
- assign set_stb_o = ~empty;
+ assign set_stb_o = ~empty & (~blocked | ~FLOW_CTRL);
endmodule // settings_bus_crossclock
diff --git a/fpga/usrp2/control_lib/settings_fifo_ctrl.v b/fpga/usrp2/control_lib/settings_fifo_ctrl.v
new file mode 100644
index 000000000..82651e776
--- /dev/null
+++ b/fpga/usrp2/control_lib/settings_fifo_ctrl.v
@@ -0,0 +1,392 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+// A settings and readback bus controlled via fifo36 interface
+
+module settings_fifo_ctrl
+ #(
+ parameter PROT_DEST = 0, //protocol framer destination
+ parameter PROT_HDR = 1, //needs a protocol header?
+ parameter ACK_SID = 0 //stream ID for packet ACK
+ )
+ (
+ //clock and synchronous reset for all interfaces
+ input clock, input reset, input clear,
+
+ //current system time
+ input [63:0] vita_time,
+
+ //ready signal for multiple peripherals
+ input perfs_ready,
+
+ //input fifo36 interface control
+ input [35:0] in_data, input in_valid, output in_ready,
+
+ //output fifo36 interface status
+ output [35:0] out_data, output out_valid, input out_ready,
+
+ //32-bit settings bus outputs
+ output strobe, output [7:0] addr, output [31:0] data,
+
+ //16X 32-bit inputs for readback
+ input [31:0] word00,
+ input [31:0] word01,
+ input [31:0] word02,
+ input [31:0] word03,
+ input [31:0] word04,
+ input [31:0] word05,
+ input [31:0] word06,
+ input [31:0] word07,
+ input [31:0] word08,
+ input [31:0] word09,
+ input [31:0] word10,
+ input [31:0] word11,
+ input [31:0] word12,
+ input [31:0] word13,
+ input [31:0] word14,
+ input [31:0] word15,
+
+ //debug output
+ output [31:0] debug
+ );
+
+ wire reading = in_valid && in_ready;
+ wire writing = out_valid && out_ready;
+
+ //------------------------------------------------------------------
+ //-- The command fifo:
+ //-- Stores an individual register access command per line.
+ //------------------------------------------------------------------
+ wire [63:0] in_command_ticks, out_command_ticks;
+ wire [31:0] in_command_hdr, out_command_hdr;
+ wire [31:0] in_command_data, out_command_data;
+ wire in_command_has_time, out_command_has_time;
+ wire command_fifo_full, command_fifo_empty;
+ wire command_fifo_read, command_fifo_write;
+
+ shortfifo #(.WIDTH(129)) command_fifo (
+ .clk(clock), .rst(reset), .clear(clear),
+ .datain({in_command_ticks, in_command_hdr, in_command_data, in_command_has_time}),
+ .dataout({out_command_ticks, out_command_hdr, out_command_data, out_command_has_time}),
+ .write(command_fifo_write), .full(command_fifo_full), //input interface
+ .empty(command_fifo_empty), .read(command_fifo_read) //output interface
+ );
+
+ //------------------------------------------------------------------
+ //-- The result fifo:
+ //-- Stores an individual result of a command per line.
+ //------------------------------------------------------------------
+ wire [31:0] in_result_hdr, out_result_hdr;
+ wire [31:0] in_result_data, out_result_data;
+ wire result_fifo_full, result_fifo_empty;
+ wire result_fifo_read, result_fifo_write;
+
+ shortfifo #(.WIDTH(64)) result_fifo (
+ .clk(clock), .rst(reset), .clear(clear),
+ .datain({in_result_hdr, in_result_data}),
+ .dataout({out_result_hdr, out_result_data}),
+ .write(result_fifo_write), .full(result_fifo_full), //input interface
+ .empty(result_fifo_empty), .read(result_fifo_read) //output interface
+ );
+
+ //------------------------------------------------------------------
+ //-- Input state machine:
+ //-- Read input packet and fill a command fifo entry.
+ //------------------------------------------------------------------
+ localparam READ_LINE0 = 0;
+ localparam VITA_HDR = 1;
+ localparam VITA_SID = 2;
+ localparam VITA_CID0 = 3;
+ localparam VITA_CID1 = 4;
+ localparam VITA_TSI = 5;
+ localparam VITA_TSF0 = 6;
+ localparam VITA_TSF1 = 7;
+ localparam READ_HDR = 8;
+ localparam READ_DATA = 9;
+ localparam WAIT_EOF = 10;
+ localparam STORE_CMD = 11;
+
+ reg [4:0] in_state;
+
+ //holdover from current read inputs
+ reg [31:0] in_data_reg, in_hdr_reg;
+ reg [63:0] in_ticks_reg;
+ wire has_sid = in_data[28];
+ wire has_cid = in_data[27];
+ wire has_tsi = in_data[23:22] != 0;
+ wire has_tsf = in_data[21:20] != 0;
+ reg has_sid_reg, has_cid_reg, has_tsi_reg, has_tsf_reg;
+
+ assign in_ready = (in_state < STORE_CMD);
+ assign command_fifo_write = (in_state == STORE_CMD);
+ assign in_command_ticks = in_ticks_reg;
+ assign in_command_data = in_data_reg;
+ assign in_command_hdr = in_hdr_reg;
+ assign in_command_has_time = has_tsf_reg;
+
+ always @(posedge clock) begin
+ if (reset) begin
+ in_state <= READ_LINE0;
+ end
+ else begin
+ case (in_state)
+
+ READ_LINE0: begin
+ if (reading/* && in_data[32]*/) in_state <= VITA_HDR;
+ end
+
+ VITA_HDR: begin
+ if (reading) begin
+ if (has_sid) in_state <= VITA_SID;
+ else if (has_cid) in_state <= VITA_CID0;
+ else if (has_tsi) in_state <= VITA_TSI;
+ else if (has_tsf) in_state <= VITA_TSF0;
+ else in_state <= READ_HDR;
+ end
+ has_sid_reg <= has_sid;
+ has_cid_reg <= has_cid;
+ has_tsi_reg <= has_tsi;
+ has_tsf_reg <= has_tsf;
+ end
+
+ VITA_SID: begin
+ if (reading) begin
+ if (has_cid_reg) in_state <= VITA_CID0;
+ else if (has_tsi_reg) in_state <= VITA_TSI;
+ else if (has_tsf_reg) in_state <= VITA_TSF0;
+ else in_state <= READ_HDR;
+ end
+ end
+
+ VITA_CID0: begin
+ if (reading) in_state <= VITA_CID1;
+ end
+
+ VITA_CID1: begin
+ if (reading) begin
+ if (has_tsi_reg) in_state <= VITA_TSI;
+ else if (has_tsf_reg) in_state <= VITA_TSF0;
+ else in_state <= READ_HDR;
+ end
+ end
+
+ VITA_TSI: begin
+ if (reading) begin
+ if (has_tsf_reg) in_state <= VITA_TSF0;
+ else in_state <= READ_HDR;
+ end
+ end
+
+ VITA_TSF0: begin
+ if (reading) in_state <= VITA_TSF1;
+ in_ticks_reg[63:32] <= in_data;
+ end
+
+ VITA_TSF1: begin
+ if (reading) in_state <= READ_HDR;
+ in_ticks_reg[31:0] <= in_data;
+ end
+
+ READ_HDR: begin
+ if (reading) in_state <= READ_DATA;
+ in_hdr_reg <= in_data[31:0];
+ end
+
+ READ_DATA: begin
+ if (reading) in_state <= (in_data[33])? STORE_CMD : WAIT_EOF;
+ in_data_reg <= in_data[31:0];
+ end
+
+ WAIT_EOF: begin
+ if (reading && in_data[33]) in_state <= STORE_CMD;
+ end
+
+ STORE_CMD: begin
+ if (~command_fifo_full) in_state <= READ_LINE0;
+ end
+
+ endcase //in_state
+ end
+ end
+
+ //------------------------------------------------------------------
+ //-- Command state machine:
+ //-- Read a command fifo entry, act on it, produce result.
+ //------------------------------------------------------------------
+ localparam LOAD_CMD = 0;
+ localparam EVENT_CMD = 1;
+
+ reg cmd_state;
+ reg [31:0] rb_data;
+
+ reg [63:0] command_ticks_reg;
+ reg [31:0] command_hdr_reg;
+ reg [31:0] command_data_reg;
+
+ reg [63:0] vita_time_reg;
+ always @(posedge clock)
+ vita_time_reg <= vita_time;
+
+ wire late;
+ `ifndef FIFO_CTRL_NO_TIME
+ time_compare time_compare(
+ .time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late));
+ `else
+ assign late = 1;
+ `endif
+
+ //action occurs in the event state and when there is fifo space (should always be true)
+ //the third condition is that all peripherals in the perfs signal are ready/active high
+ //the fourth condition is that is an event time has been set, action is delayed until that time
+ wire time_ready = (out_command_has_time)? late : 1;
+ wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready;
+
+ assign command_fifo_read = action;
+ assign result_fifo_write = action;
+ assign in_result_hdr = command_hdr_reg;
+ assign in_result_data = rb_data;
+
+ always @(posedge clock) begin
+ if (reset) begin
+ cmd_state <= LOAD_CMD;
+ end
+ else begin
+ case (cmd_state)
+
+ LOAD_CMD: begin
+ if (~command_fifo_empty) cmd_state <= EVENT_CMD;
+ command_ticks_reg <= out_command_ticks;
+ command_hdr_reg <= out_command_hdr;
+ command_data_reg <= out_command_data;
+ end
+
+ EVENT_CMD: begin // poking and peeking happens here!
+ if (action || clear) cmd_state <= LOAD_CMD;
+ end
+
+ endcase //cmd_state
+ end
+ end
+
+ //------------------------------------------------------------------
+ //-- assign to settings bus interface
+ //------------------------------------------------------------------
+ reg strobe_reg;
+ assign strobe = strobe_reg;
+ assign data = command_data_reg;
+ assign addr = command_hdr_reg[7:0];
+ wire poke = command_hdr_reg[8];
+
+ always @(posedge clock) begin
+ if (reset || clear) strobe_reg <= 0;
+ else strobe_reg <= action && poke;
+ end
+
+ //------------------------------------------------------------------
+ //-- readback mux
+ //------------------------------------------------------------------
+ always @(posedge clock) begin
+ case (out_command_hdr[3:0])
+ 0 : rb_data <= word00;
+ 1 : rb_data <= word01;
+ 2 : rb_data <= word02;
+ 3 : rb_data <= word03;
+ 4 : rb_data <= word04;
+ 5 : rb_data <= word05;
+ 6 : rb_data <= word06;
+ 7 : rb_data <= word07;
+ 8 : rb_data <= word08;
+ 9 : rb_data <= word09;
+ 10: rb_data <= word10;
+ 11: rb_data <= word11;
+ 12: rb_data <= word12;
+ 13: rb_data <= word13;
+ 14: rb_data <= word14;
+ 15: rb_data <= word15;
+ endcase // case(addr_reg[3:0])
+ end
+
+ //------------------------------------------------------------------
+ //-- Output state machine:
+ //-- Read a command fifo entry, act on it, produce ack packet.
+ //------------------------------------------------------------------
+ localparam WRITE_PROT_HDR = 0;
+ localparam WRITE_VRT_HDR = 1;
+ localparam WRITE_VRT_SID = 2;
+ localparam WRITE_RB_HDR = 3;
+ localparam WRITE_RB_DATA = 4;
+
+ //the state for the start of packet condition
+ localparam WRITE_PKT_HDR = (PROT_HDR)? WRITE_PROT_HDR : WRITE_VRT_HDR;
+
+ reg [2:0] out_state;
+
+ assign out_valid = ~result_fifo_empty;
+ assign result_fifo_read = out_data[33] && writing;
+
+ always @(posedge clock) begin
+ if (reset) begin
+ out_state <= WRITE_PKT_HDR;
+ end
+ else if (writing && out_data[33]) begin
+ out_state <= WRITE_PKT_HDR;
+ end
+ else if (writing) begin
+ out_state <= out_state + 1;
+ end
+ end
+
+ //------------------------------------------------------------------
+ //-- assign to output fifo interface
+ //------------------------------------------------------------------
+ wire [31:0] prot_hdr;
+ assign prot_hdr[15:0] = 16; //bytes in proceeding vita packet
+ assign prot_hdr[16] = 1; //yes frame
+ assign prot_hdr[18:17] = PROT_DEST;
+ assign prot_hdr[31:19] = 0; //nothing
+
+ reg [31:0] out_data_int;
+ always @* begin
+ case (out_state)
+ WRITE_PROT_HDR: out_data_int <= prot_hdr;
+ WRITE_VRT_HDR: out_data_int <= {12'b010100000000, out_result_hdr[19:16], 2'b0, prot_hdr[15:2]};
+ WRITE_VRT_SID: out_data_int <= ACK_SID;
+ WRITE_RB_HDR: out_data_int <= out_result_hdr;
+ WRITE_RB_DATA: out_data_int <= out_result_data;
+ default: out_data_int <= 0;
+ endcase //state
+ end
+
+ assign out_data[35:34] = 2'b0;
+ assign out_data[33] = (out_state == WRITE_RB_DATA);
+ assign out_data[32] = (out_state == WRITE_PKT_HDR);
+ assign out_data[31:0] = out_data_int;
+
+ //------------------------------------------------------------------
+ //-- debug outputs
+ //------------------------------------------------------------------
+ assign debug = {
+ in_state, out_state, //8
+ in_valid, in_ready, in_data[33:32], //4
+ out_valid, out_ready, out_data[33:32], //4
+ command_fifo_empty, command_fifo_full, //2
+ command_fifo_read, command_fifo_write, //2
+ addr, //8
+ strobe_reg, strobe, poke, out_command_has_time //4
+ };
+
+endmodule //settings_fifo_ctrl
diff --git a/fpga/usrp2/control_lib/simple_spi_core.v b/fpga/usrp2/control_lib/simple_spi_core.v
new file mode 100644
index 000000000..3c0ed60b9
--- /dev/null
+++ b/fpga/usrp2/control_lib/simple_spi_core.v
@@ -0,0 +1,214 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+// Simple SPI core, the simplest, yet complete spi core I can think of
+
+// Settings register controlled.
+// 2 settings regs, control and data
+// 1 32-bit readback and status signal
+
+// Settings reg map:
+//
+// BASE+0 divider setting
+// bits [15:0] spi clock divider
+//
+// BASE+1 configuration input
+// bits [23:0] slave select, bit0 = slave0 enabled
+// bits [29:24] num bits (1 through 32)
+// bit [30] data input edge = in data bit latched on rising edge of clock
+// bit [31] data output edge = out data bit latched on rising edge of clock
+//
+// BASE+2 input data
+// Writing this register begins a spi transaction.
+// Bits are latched out from bit 0.
+// Therefore, load this register in reverse.
+//
+// Readback
+// Bits are latched into bit 0.
+// Therefore, data will be in-order.
+
+module simple_spi_core
+ #(
+ //settings register base address
+ parameter BASE = 0,
+
+ //width of serial enables (up to 24 is possible)
+ parameter WIDTH = 8,
+
+ //idle state of the spi clock
+ parameter CLK_IDLE = 0,
+
+ //idle state of the serial enables
+ parameter SEN_IDLE = 24'hffffff
+ )
+ (
+ //clock and synchronous reset
+ input clock, input reset,
+
+ //32-bit settings bus inputs
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ //32-bit data readback
+ output [31:0] readback,
+
+ //read is high when spi core can begin another transaction
+ output ready,
+
+ //spi interface, slave selects, clock, data in, data out
+ output [WIDTH-1:0] sen,
+ output sclk,
+ output mosi,
+ input miso,
+
+ //optional debug output
+ output [31:0] debug
+ );
+
+ wire [15:0] sclk_divider;
+ setting_reg #(.my_addr(BASE+0),.width(16)) divider_sr(
+ .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(sclk_divider),.changed());
+
+ wire [23:0] slave_select;
+ wire [5:0] num_bits;
+ wire datain_edge, dataout_edge;
+ setting_reg #(.my_addr(BASE+1),.width(32)) config_sr(
+ .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out({dataout_edge, datain_edge, num_bits, slave_select}),.changed());
+
+ wire [31:0] mosi_data;
+ wire trigger_spi;
+ setting_reg #(.my_addr(BASE+2),.width(32)) data_sr(
+ .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(mosi_data),.changed(trigger_spi));
+
+ localparam WAIT_TRIG = 0;
+ localparam PRE_IDLE = 1;
+ localparam CLK_REG = 2;
+ localparam CLK_INV = 3;
+ localparam POST_IDLE = 4;
+ localparam IDLE_SEN = 5;
+
+ reg [2:0] state;
+
+ reg ready_reg;
+ assign ready = ready_reg && ~trigger_spi;
+
+ //serial clock either idles or is in one of two clock states
+ reg sclk_reg;
+ assign sclk = sclk_reg;
+
+ //serial enables either idle or enabled based on state
+ wire sen_is_idle = (state == WAIT_TRIG) || (state == IDLE_SEN);
+ wire [23:0] sen24 = (sen_is_idle)? SEN_IDLE : (SEN_IDLE ^ slave_select);
+ reg [WIDTH-1:0] sen_reg;
+ always @(posedge clock) sen_reg <= sen24[WIDTH-1:0];
+ assign sen = sen_reg;
+
+ //data output shift register
+ reg [31:0] dataout_reg;
+ wire [31:0] dataout_next = {dataout_reg[30:0], 1'b0};
+ assign mosi = dataout_reg[31];
+
+ //data input shift register
+ reg [31:0] datain_reg;
+ wire [31:0] datain_next = {datain_reg[30:0], miso};
+ assign readback = datain_reg;
+
+ //counter for spi clock
+ reg [15:0] sclk_counter;
+ wire sclk_counter_done = (sclk_counter == sclk_divider);
+ wire [15:0] sclk_counter_next = (sclk_counter_done)? 0 : sclk_counter + 1;
+
+ //counter for latching bits miso/mosi
+ reg [6:0] bit_counter;
+ wire [6:0] bit_counter_next = bit_counter + 1;
+ wire bit_counter_done = (bit_counter_next == num_bits);
+
+ always @(posedge clock) begin
+ if (reset) begin
+ state <= WAIT_TRIG;
+ sclk_reg <= CLK_IDLE;
+ ready_reg <= 0;
+ end
+ else begin
+ case (state)
+
+ WAIT_TRIG: begin
+ if (trigger_spi) state <= PRE_IDLE;
+ ready_reg <= ~trigger_spi;
+ dataout_reg <= mosi_data;
+ sclk_counter <= 0;
+ bit_counter <= 0;
+ sclk_reg <= CLK_IDLE;
+ end
+
+ PRE_IDLE: begin
+ if (sclk_counter_done) state <= CLK_REG;
+ sclk_counter <= sclk_counter_next;
+ sclk_reg <= CLK_IDLE;
+ end
+
+ CLK_REG: begin
+ if (sclk_counter_done) begin
+ state <= CLK_INV;
+ if (datain_edge != CLK_IDLE) datain_reg <= datain_next;
+ if (dataout_edge != CLK_IDLE && bit_counter != 0) dataout_reg <= dataout_next;
+ sclk_reg <= ~CLK_IDLE; //transition to rising when CLK_IDLE == 0
+ end
+ sclk_counter <= sclk_counter_next;
+ end
+
+ CLK_INV: begin
+ if (sclk_counter_done) begin
+ state <= (bit_counter_done)? POST_IDLE : CLK_REG;
+ bit_counter <= bit_counter_next;
+ if (datain_edge == CLK_IDLE) datain_reg <= datain_next;
+ if (dataout_edge == CLK_IDLE && ~bit_counter_done) dataout_reg <= dataout_next;
+ sclk_reg <= CLK_IDLE; //transition to falling when CLK_IDLE == 0
+ end
+ sclk_counter <= sclk_counter_next;
+ end
+
+ POST_IDLE: begin
+ if (sclk_counter_done) state <= IDLE_SEN;
+ sclk_counter <= sclk_counter_next;
+ sclk_reg <= CLK_IDLE;
+ end
+
+ IDLE_SEN: begin
+ if (sclk_counter_done) state <= WAIT_TRIG;
+ sclk_counter <= sclk_counter_next;
+ sclk_reg <= CLK_IDLE;
+ end
+
+ default: state <= WAIT_TRIG;
+
+ endcase //state
+ end
+ end
+
+ assign debug = {
+ trigger_spi, state, //4
+ sclk, mosi, miso, ready, //4
+ sen[7:0], //8
+ 1'b0, bit_counter[6:0], //8
+ sclk_counter_done, bit_counter_done, //2
+ sclk_counter[5:0] //6
+ };
+
+endmodule //simple_spi_core
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
index 9abec8c3e..660fb2f65 100644
--- a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
@@ -21,9 +21,7 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.xise"/>
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.veo" xil_pn:origination="imported"/>
- </files>
+ <files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs
index 28d506571..6cbd5cd3f 100644
--- a/fpga/usrp2/fifo/Makefile.srcs
+++ b/fpga/usrp2/fifo/Makefile.srcs
@@ -32,6 +32,7 @@ splitter36.v \
valve36.v \
fifo_pacer.v \
packet_dispatcher36_x3.v \
+packet_dispatcher36_x4.v \
packet_generator32.v \
packet_generator.v \
packet_verifier32.v \
diff --git a/fpga/usrp2/fifo/packet_dispatcher36_x4.v b/fpga/usrp2/fifo/packet_dispatcher36_x4.v
new file mode 100644
index 000000000..7eedb3e74
--- /dev/null
+++ b/fpga/usrp2/fifo/packet_dispatcher36_x4.v
@@ -0,0 +1,316 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// Packet dispatcher with fifo36 interface and 4 outputs.
+//
+// The packet dispatcher expects 2-byte padded ethernet frames.
+// The frames will be inspected at ethernet, IPv4, UDP, and VRT layers.
+// Packets are dispatched into the following streams:
+// * tx dsp stream
+// * tx control stream
+// * to cpu stream
+// * to external stream
+// * to both cpu and external
+//
+// The following registers are used for dispatcher control:
+// * base + 0 = this ipv4 address (32 bits)
+// * base + 1 = udp control port (upper 16 bits), udp dsp port (lower 16 bits)
+//
+
+module packet_dispatcher36_x4
+ #(
+ parameter BASE = 0
+ )
+ (
+ //clocking and reset interface:
+ input clk, input rst, input clr,
+
+ //setting register interface:
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ //input stream interfaces:
+ input [35:0] com_inp_data, input com_inp_valid, output com_inp_ready,
+
+ //output stream interfaces:
+ output [35:0] ext_out_data, output ext_out_valid, input ext_out_ready,
+ output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready,
+ output [35:0] ctl_out_data, output ctl_out_valid, input ctl_out_ready,
+ output [35:0] cpu_out_data, output cpu_out_valid, input cpu_out_ready
+ );
+
+ //setting register to program the IP address
+ wire [31:0] my_ip_addr;
+ setting_reg #(.my_addr(BASE+0)) sreg_ip_addr(
+ .clk(clk),.rst(rst),
+ .strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(my_ip_addr),.changed()
+ );
+
+ //setting register to program the UDP DSP port
+ wire [15:0] dsp_udp_port, ctl_udp_port;
+ setting_reg #(.my_addr(BASE+1), .width(32)) sreg_data_port(
+ .clk(clk),.rst(rst),
+ .strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out({ctl_udp_port, dsp_udp_port}),.changed()
+ );
+
+ ////////////////////////////////////////////////////////////////////
+ // Communication input inspector
+ // - inspect com input and send it to DSP, EXT, CPU, or BOTH
+ ////////////////////////////////////////////////////////////////////
+ localparam PD_STATE_READ_COM_PRE = 0;
+ localparam PD_STATE_READ_COM = 1;
+ localparam PD_STATE_WRITE_REGS = 2;
+ localparam PD_STATE_WRITE_LIVE = 3;
+
+ localparam PD_DEST_DSP = 0;
+ localparam PD_DEST_EXT = 1;
+ localparam PD_DEST_CPU = 2;
+ localparam PD_DEST_BOF = 3;
+ localparam PD_DEST_CTL = 4;
+
+ localparam PD_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr
+ localparam PD_DREGS_DSP_OFFSET = 11; //offset to start dsp at
+
+ //output inspector interfaces
+ wire [35:0] pd_out_dsp_data;
+ wire pd_out_dsp_valid;
+ wire pd_out_dsp_ready;
+
+ wire [35:0] pd_out_ext_data;
+ wire pd_out_ext_valid;
+ wire pd_out_ext_ready;
+
+ wire [35:0] pd_out_cpu_data;
+ wire pd_out_cpu_valid;
+ wire pd_out_cpu_ready;
+
+ wire [35:0] pd_out_bof_data;
+ wire pd_out_bof_valid;
+ wire pd_out_bof_ready;
+
+ wire [35:0] pd_out_ctl_data;
+ wire pd_out_ctl_valid;
+ wire pd_out_ctl_ready;
+
+ reg [1:0] pd_state;
+ reg [2:0] pd_dest;
+ reg [3:0] pd_dreg_count; //data registers to buffer headers
+ wire [3:0] pd_dreg_count_next = pd_dreg_count + 1'b1;
+ wire pd_dreg_counter_done = (pd_dreg_count_next == PD_MAX_NUM_DREGS)? 1'b1 : 1'b0;
+ reg [35:0] pd_dregs [PD_MAX_NUM_DREGS-1:0];
+
+ reg is_eth_dst_mac_bcast;
+ reg is_eth_type_ipv4;
+ reg is_eth_ipv4_proto_udp;
+ reg is_eth_ipv4_dst_addr_here;
+ reg is_eth_udp_dsp_port_here;
+ reg is_eth_udp_ctl_port_here;
+ wire is_vrt_size_zero = (com_inp_data[15:0] == 16'h0); //needed on the same cycle, so it cant be registered
+
+ //Inspector output flags special case:
+ //Inject SOF into flags at first DSP line.
+ wire [3:0] pd_out_flags = (
+ (pd_dreg_count == PD_DREGS_DSP_OFFSET) &&
+ (pd_dest == PD_DEST_DSP)
+ )? 4'b0001 : pd_dregs[pd_dreg_count][35:32];
+
+ //The communication inspector ouput data and valid signals:
+ //Mux between com input and data registers based on the state.
+ wire [35:0] pd_out_data = (pd_state == PD_STATE_WRITE_REGS)?
+ {pd_out_flags, pd_dregs[pd_dreg_count][31:0]} : com_inp_data
+ ;
+ wire pd_out_valid =
+ (pd_state == PD_STATE_WRITE_REGS)? 1'b1 : (
+ (pd_state == PD_STATE_WRITE_LIVE)? com_inp_valid : (
+ 1'b0));
+
+ //The communication inspector ouput ready signal:
+ //Mux between the various destination ready signals.
+ wire pd_out_ready =
+ (pd_dest == PD_DEST_DSP)? pd_out_dsp_ready : (
+ (pd_dest == PD_DEST_EXT)? pd_out_ext_ready : (
+ (pd_dest == PD_DEST_CPU)? pd_out_cpu_ready : (
+ (pd_dest == PD_DEST_BOF)? pd_out_bof_ready : (
+ (pd_dest == PD_DEST_CTL)? pd_out_ctl_ready : (
+ 1'b0)))));
+
+ //Always connected output data lines.
+ assign pd_out_dsp_data = pd_out_data;
+ assign pd_out_ext_data = pd_out_data;
+ assign pd_out_cpu_data = pd_out_data;
+ assign pd_out_bof_data = pd_out_data;
+ assign pd_out_ctl_data = pd_out_data;
+
+ //Destination output valid signals:
+ //Comes from inspector valid when destination is selected, and otherwise low.
+ assign pd_out_dsp_valid = (pd_dest == PD_DEST_DSP)? pd_out_valid : 1'b0;
+ assign pd_out_ext_valid = (pd_dest == PD_DEST_EXT)? pd_out_valid : 1'b0;
+ assign pd_out_cpu_valid = (pd_dest == PD_DEST_CPU)? pd_out_valid : 1'b0;
+ assign pd_out_bof_valid = (pd_dest == PD_DEST_BOF)? pd_out_valid : 1'b0;
+ assign pd_out_ctl_valid = (pd_dest == PD_DEST_CTL)? pd_out_valid : 1'b0;
+
+ //The communication inspector ouput ready signal:
+ //Always ready when storing to data registers,
+ //comes from inspector ready output when live,
+ //and otherwise low.
+ assign com_inp_ready =
+ (pd_state == PD_STATE_READ_COM_PRE) ? 1'b1 : (
+ (pd_state == PD_STATE_READ_COM) ? 1'b1 : (
+ (pd_state == PD_STATE_WRITE_LIVE) ? pd_out_ready : (
+ 1'b0)));
+
+ //inspect the incoming data and mark register booleans
+ always @(posedge clk)
+ if (com_inp_ready & com_inp_valid) begin
+ case(pd_dreg_count)
+ 0: begin
+ is_eth_dst_mac_bcast <= (com_inp_data[15:0] == 16'hffff);
+ end
+ 1: begin
+ is_eth_dst_mac_bcast <= is_eth_dst_mac_bcast && (com_inp_data[31:0] == 32'hffffffff);
+ end
+ 3: begin
+ is_eth_type_ipv4 <= (com_inp_data[15:0] == 16'h800);
+ end
+ 6: begin
+ is_eth_ipv4_proto_udp <= (com_inp_data[23:16] == 8'h11);
+ end
+ 8: begin
+ is_eth_ipv4_dst_addr_here <= (com_inp_data[31:0] == my_ip_addr);
+ end
+ 9: begin
+ is_eth_udp_dsp_port_here <= (com_inp_data[15:0] == dsp_udp_port);
+ is_eth_udp_ctl_port_here <= (com_inp_data[15:0] == ctl_udp_port);
+ end
+ endcase //pd_dreg_count
+ end
+
+ always @(posedge clk)
+ if(rst | clr) begin
+ pd_state <= PD_STATE_READ_COM_PRE;
+ pd_dreg_count <= 0;
+ end
+ else begin
+ case(pd_state)
+ PD_STATE_READ_COM_PRE: begin
+ if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin
+ pd_state <= PD_STATE_READ_COM;
+ pd_dreg_count <= pd_dreg_count_next;
+ pd_dregs[pd_dreg_count] <= com_inp_data;
+ end
+ end
+
+ PD_STATE_READ_COM: begin
+ if (com_inp_ready & com_inp_valid) begin
+ pd_dregs[pd_dreg_count] <= com_inp_data;
+ if (pd_dreg_counter_done | com_inp_data[33]) begin
+ pd_state <= PD_STATE_WRITE_REGS;
+ pd_dreg_count <= 0;
+
+ //---------- begin inspection decision -----------//
+ //EOF or bcast or not IPv4 or not UDP:
+ if (
+ com_inp_data[33] || is_eth_dst_mac_bcast ||
+ ~is_eth_type_ipv4 || ~is_eth_ipv4_proto_udp
+ ) begin
+ pd_dest <= PD_DEST_BOF;
+ end
+
+ //not my IP address:
+ else if (~is_eth_ipv4_dst_addr_here) begin
+ pd_dest <= PD_DEST_EXT;
+ end
+
+ //UDP control port and VRT:
+ else if (is_eth_udp_ctl_port_here && ~is_vrt_size_zero) begin
+ pd_dest <= PD_DEST_CTL;
+ pd_dreg_count <= PD_DREGS_DSP_OFFSET;
+ end
+
+ //UDP data port and VRT:
+ else if (is_eth_udp_dsp_port_here && ~is_vrt_size_zero) begin
+ pd_dest <= PD_DEST_DSP;
+ pd_dreg_count <= PD_DREGS_DSP_OFFSET;
+ end
+
+ //other:
+ else begin
+ pd_dest <= PD_DEST_CPU;
+ end
+ //---------- end inspection decision -------------//
+
+ end
+ else begin
+ pd_dreg_count <= pd_dreg_count_next;
+ end
+ end
+ end
+
+ PD_STATE_WRITE_REGS: begin
+ if (pd_out_ready & pd_out_valid) begin
+ if (pd_out_data[33]) begin
+ pd_state <= PD_STATE_READ_COM_PRE;
+ pd_dreg_count <= 0;
+ end
+ else if (pd_dreg_counter_done) begin
+ pd_state <= PD_STATE_WRITE_LIVE;
+ pd_dreg_count <= 0;
+ end
+ else begin
+ pd_dreg_count <= pd_dreg_count_next;
+ end
+ end
+ end
+
+ PD_STATE_WRITE_LIVE: begin
+ if (pd_out_ready & pd_out_valid & pd_out_data[33]) begin
+ pd_state <= PD_STATE_READ_COM_PRE;
+ end
+ end
+
+ endcase //pd_state
+ end
+
+ //connect this fast-path signals directly to the DSP out
+ assign dsp_out_data = pd_out_dsp_data;
+ assign dsp_out_valid = pd_out_dsp_valid;
+ assign pd_out_dsp_ready = dsp_out_ready;
+
+ assign ctl_out_data = pd_out_ctl_data;
+ assign ctl_out_valid = pd_out_ctl_valid;
+ assign pd_out_ctl_ready = ctl_out_ready;
+
+ ////////////////////////////////////////////////////////////////////
+ // Splitter and output muxes for the bof packets
+ // - split the bof packets into two streams
+ // - mux split packets into cpu out and ext out
+ ////////////////////////////////////////////////////////////////////
+
+ //dummy signals to join the the splitter and muxes below
+ wire [35:0] _split_to_ext_data, _split_to_cpu_data;
+ wire _split_to_ext_valid, _split_to_cpu_valid;
+ wire _split_to_ext_ready, _split_to_cpu_ready;
+
+ splitter36 bof_out_splitter(
+ .clk(clk), .rst(rst), .clr(clr),
+ .inp_data(pd_out_bof_data), .inp_valid(pd_out_bof_valid), .inp_ready(pd_out_bof_ready),
+ .out0_data(_split_to_ext_data), .out0_valid(_split_to_ext_valid), .out0_ready(_split_to_ext_ready),
+ .out1_data(_split_to_cpu_data), .out1_valid(_split_to_cpu_valid), .out1_ready(_split_to_cpu_ready)
+ );
+
+ fifo36_mux ext_out_mux(
+ .clk(clk), .reset(rst), .clear(clr),
+ .data0_i(pd_out_ext_data), .src0_rdy_i(pd_out_ext_valid), .dst0_rdy_o(pd_out_ext_ready),
+ .data1_i(_split_to_ext_data), .src1_rdy_i(_split_to_ext_valid), .dst1_rdy_o(_split_to_ext_ready),
+ .data_o(ext_out_data), .src_rdy_o(ext_out_valid), .dst_rdy_i(ext_out_ready)
+ );
+
+ fifo36_mux cpu_out_mux(
+ .clk(clk), .reset(rst), .clear(clr),
+ .data0_i(pd_out_cpu_data), .src0_rdy_i(pd_out_cpu_valid), .dst0_rdy_o(pd_out_cpu_ready),
+ .data1_i(_split_to_cpu_data), .src1_rdy_i(_split_to_cpu_valid), .dst1_rdy_o(_split_to_cpu_ready),
+ .data_o(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready)
+ );
+
+endmodule // packet_dispatcher36_x3
diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v
index 7bfa6893d..4c0fe14b1 100644
--- a/fpga/usrp2/fifo/packet_router.v
+++ b/fpga/usrp2/fifo/packet_router.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -54,10 +54,12 @@ module packet_router
input [35:0] dsp1_inp_data, input dsp1_inp_valid, output dsp1_inp_ready,
input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready,
input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready,
+ input [35:0] ctl_inp_data, input ctl_inp_valid, output ctl_inp_ready,
// Output Interfaces (out of router)
output [35:0] ser_out_data, output ser_out_valid, input ser_out_ready,
output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready,
+ output [35:0] ctl_out_data, output ctl_out_valid, input ctl_out_ready,
output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready
);
@@ -188,9 +190,9 @@ module packet_router
////////////////////////////////////////////////////////////////////
//dummy signals to join the the muxes below
- wire [35:0] _combiner0_data, _combiner1_data;
- wire _combiner0_valid, _combiner1_valid;
- wire _combiner0_ready, _combiner1_ready;
+ wire [35:0] _combiner0_data, _combiner1_data, _combiner2_data;
+ wire _combiner0_valid, _combiner1_valid, _combiner2_valid;
+ wire _combiner0_ready, _combiner1_ready, _combiner2_ready;
fifo36_mux #(.prio(0)) // No priority, fair sharing
_com_output_combiner0(
@@ -201,6 +203,14 @@ module packet_router
);
fifo36_mux #(.prio(0)) // No priority, fair sharing
+ _com_output_combiner2(
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready),
+ .data1_i(ctl_inp_data), .src1_rdy_i(ctl_inp_valid), .dst1_rdy_o(ctl_inp_ready),
+ .data_o(_combiner2_data), .src_rdy_o(_combiner2_valid), .dst_rdy_i(_combiner2_ready)
+ );
+
+ fifo36_mux #(.prio(0)) // No priority, fair sharing
_com_output_combiner1(
.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
.data0_i(dsp0_inp_data), .src0_rdy_i(dsp0_inp_valid), .dst0_rdy_o(dsp0_inp_ready),
@@ -211,7 +221,7 @@ module packet_router
fifo36_mux #(.prio(1)) // Give priority to err/cpu over dsp
com_output_source(
.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
- .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready),
+ .data0_i(_combiner2_data), .src0_rdy_i(_combiner2_valid), .dst0_rdy_o(_combiner2_ready),
.data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready),
.data_o(udp_out_data), .src_rdy_o(udp_out_valid), .dst_rdy_i(udp_out_ready)
);
@@ -248,12 +258,13 @@ module packet_router
wire _cpu_out_valid;
wire _cpu_out_ready;
- packet_dispatcher36_x3 #(.BASE(CTRL_BASE+1)) packet_dispatcher(
+ packet_dispatcher36_x4 #(.BASE(CTRL_BASE+1)) packet_dispatcher(
.clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.com_inp_data(com_inp_data), .com_inp_valid(com_inp_valid), .com_inp_ready(com_inp_ready),
.ext_out_data(ext_out_data), .ext_out_valid(ext_out_valid), .ext_out_ready(ext_out_ready),
.dsp_out_data(dsp_out_data), .dsp_out_valid(dsp_out_valid), .dsp_out_ready(dsp_out_ready),
+ .ctl_out_data(ctl_out_data), .ctl_out_valid(ctl_out_valid), .ctl_out_ready(ctl_out_ready),
.cpu_out_data(_cpu_out_data), .cpu_out_valid(_cpu_out_valid), .cpu_out_ready(_cpu_out_ready)
);
diff --git a/fpga/usrp2/top/N2x0/bootloader.rmi b/fpga/usrp2/top/N2x0/bootloader.rmi
index 1b378b5d6..cf51f52b4 100644
--- a/fpga/usrp2/top/N2x0/bootloader.rmi
+++ b/fpga/usrp2/top/N2x0/bootloader.rmi
@@ -1,5 +1,5 @@
-defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_d7fc0400_3a0b0b80_80e4b40c_82700b0b_0b0b0b0b;
-defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80d8c62d_88080b0b_80088408;
+defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_dbaa0400_3a0b0b80_80e7e80c_82700b0b_0b0b0b0b;
+defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80dbf42d_88080b0b_80088408;
defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608;
defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608;
defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105;
@@ -18,404 +18,404 @@ defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_
defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981;
defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206;
defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608;
-defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_a0738306_0b0b80e4_71fc0608;
-defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_9d2d5050_0b0b80cf_88087575_80088408;
-defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_cf2d5050_0b0b80d0_88087575_80088408;
+defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_d4738306_0b0b80e7_71fc0608;
+defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_cb2d5050_0b0b80d2_88087575_80088408;
+defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_fd2d5050_0b0b80d3_88087575_80088408;
defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081;
defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081;
defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504;
-defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e4b00c_810b0b0b;
+defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e7e40c_810b0b0b;
defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552;
defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572;
defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff;
-defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d0c33f04_82813f80;
+defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d3f13f04_82813f80;
defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010;
defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04;
-defparam bootram.RAM0.INIT_23=256'h800b80e5_8c0c82a0_0b0b80e5_8380800b_822ebd38_80e4b408_802ea438_80e4b008;
-defparam bootram.RAM0.INIT_24=256'h0b80e590_80808280_e58c0cf8_0b0b0b80_808080a4_940c04f8_800b80e5_900c8290;
-defparam bootram.RAM0.INIT_25=256'h940b80e5_80c0a880_80e58c0c_8c0b0b0b_80c0a880_e5940c04_84800b80_0cf88080;
-defparam bootram.RAM0.INIT_26=256'h70085252_80e4bc08_5170a738_80e59833_04ff3d0d_80e5940c_80d8f80b_900c0b0b;
-defparam bootram.RAM0.INIT_27=256'h9834833d_810b80e5_5270ee38_08700852_2d80e4bc_e4bc0c70_38841280_70802e94;
-defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e58808_3d0d0b0b_0d040480;
-defparam bootram.RAM0.INIT_29=256'h3d225a79_80d33895_0d685b7a_0404ee3d_3f823d0d_0b0bf5d4_e588510b_040b0b80;
-defparam bootram.RAM0.INIT_2A=256'h2e973881_79838086_3881e439_80842e8e_8b387983_83808524_80c23879_8380852e;
-defparam bootram.RAM0.INIT_2B=256'h7a81e2c4_81e2c00c_39890a0b_e1880c99_840c7a81_0c7a81e1_0b81e180_da39890a;
-defparam bootram.RAM0.INIT_2C=256'h2e9e3879_79838085_973d225a_7c2eab38_0c805c7a_7a81e4d0_c80c8639_0c7a81e2;
-defparam bootram.RAM0.INIT_2D=256'h815c923d_38818039_80862e86_825c7983_38818c39_80842e92_8b387983_83808524;
-defparam bootram.RAM0.INIT_2E=256'h3d415e5c_0b883d99_5b5f4080_0284057d_943f8008_a9893f8a_84055241_7053963d;
-defparam bootram.RAM0.INIT_2F=256'h7d055b5b_7b1d963d_901f5e5c_ef38800b_5c887c26_7b34811c_5b5b7933_7b1d7f1d;
-defparam bootram.RAM0.INIT_30=256'h811c5c86_79337b34_601d5b5b_5e5c7b1d_800b881f_7c26ed38_811c5c88_79337b34;
-defparam bootram.RAM0.INIT_31=256'h3d0d04ee_99ff3f94_7c26ef38_811c5c86_79337b34_611d5b5b_805c7b1e_7c26ef38;
-defparam bootram.RAM0.INIT_32=256'h75538b52_802e8c38_2e943875_0856758b_279c3877_5a588379_84120859_3d0d686a;
-defparam bootram.RAM0.INIT_33=256'h8b5ba05c_f93fa057_d9cc5194_53a45280_268e3878_e15778a3_958c3f80_80d8fc51;
-defparam bootram.RAM0.INIT_34=256'h89a23f80_0480c15c_05567508_2980dbbc_91387584_75922682_ff9f1756_8818085d;
-defparam bootram.RAM0.INIT_35=256'h962a8480_32703070_183380f2_2e923894_577580f2_33568880_fb399518_08085e81;
-defparam bootram.RAM0.INIT_36=256'h83388157_5775772e_97193357_0852800b_08538c18_33549018_76559618_06595156;
-defparam bootram.RAM0.INIT_37=256'h568cd23f_8c193352_3dea0553_33705495_b3398d18_80d35c81_3f80085f_765196a2;
-defparam bootram.RAM0.INIT_38=256'hb5053480_75028405_3f80c85c_52568ddf_538c1933_70548e19_398d1833_80c95c94;
-defparam bootram.RAM0.INIT_39=256'h0476085f_58567508_058c1908_2980dc88_c2387584_75852680_33ff0556_ff399418;
-defparam bootram.RAM0.INIT_3A=256'h70084056_80e59c05_39768429_2277239b_a2399218_1808770c_5fa93990_ae397622;
-defparam bootram.RAM0.INIT_3B=256'h55943ddc_5c8c1808_785e80cc_d25cad39_710c5680_05901908_2980e59c_8e397684;
-defparam bootram.RAM0.INIT_3C=256'ha439a05c_7826ed38_81185888_75337734_79055757_7719963d_833d5a58_0554800b;
-defparam bootram.RAM0.INIT_3D=256'h887826ed_34811858_57753377_3d790557_58771996_0b833d5a_dc055480_a455943d;
-defparam bootram.RAM0.INIT_3E=256'h2e9238a0_993f7280_98525392_705380da_fe3d0d74_943d0d04_519b8b3f_38838080;
-defparam bootram.RAM0.INIT_3F=256'h843d0d04_518fba3f_87c63f72_a0527251_9e3f8d39_8fcb3f9b_d73f8151_52a05187;
-defparam bootram.RAM1.INIT_00=256'h91d43f81_80daf451_dd3f8b52_dad45191_3f885280_b85188ba_8d3f80da_fa3d0d82;
-defparam bootram.RAM1.INIT_01=256'h3f800851_d43f8684_908f3f87_3f800851_843f85b1_859d3f86_0ca9a73f_0b80e5b8;
-defparam bootram.RAM1.INIT_02=256'h85528008_e73f8380_94b63f85_52800851_85933f73_3f800854_c83f85f8_90a93f87;
-defparam bootram.RAM1.INIT_03=256'hb2528380_94f23f8a_83808451_3f8ab252_805194fc_bf528380_94c03f8c_518e9a3f;
-defparam bootram.RAM1.INIT_04=256'h9251a584_d33f8380_80825194_c0865283_94de3f80_83808551_3f8ab252_865194e8;
-defparam bootram.RAM1.INIT_05=256'h802e80c9_08568008_8e873f80_3dfc0551_abe93f88_51a9d73f_903f8fcc_3f80518e;
-defparam bootram.RAM1.INIT_06=256'h055180c4_52800890_5380db98_06ad3884_ee2e0981_557382fd_8e052255_38768008;
-defparam bootram.RAM1.INIT_07=256'h3f883974_73518591_3f86963f_52548ef7_3f941670_a0519086_9a3880db_d43f8008;
-defparam bootram.RAM1.INIT_08=256'hb73f8787_91ce3f82_0d85df3f_9e39fe3d_8bfe3fff_3fa4d73f_8b3f8d8c_5275519a;
-defparam bootram.RAM1.INIT_09=256'h52845184_8af23f84_3f82ac51_80518588_ac3f9f52_52805185_88833f9f_3f8bb33f;
-defparam bootram.RAM1.INIT_0A=256'h82ac518a_5184e13f_3f905290_ac518ad8_84ee3f82_88528851_518ae53f_fb3f82ac;
-defparam bootram.RAM1.INIT_0B=256'haf3fff13_80e4518a_5184c53f_3f9f529c_e4518abc_84d23f80_9f528051_cb3f8253;
-defparam bootram.RAM1.INIT_0C=256'h800c843d_840c810b_890b81e0_5184a93f_3f9f5281_9e5184cd_df389f52_53728025;
-defparam bootram.RAM1.INIT_0D=256'h8c05a705_7a7d7f02_04f93d0d_51823d0d_8106800c_08708b2a_0d82808c_0d04803d;
-defparam bootram.RAM1.INIT_0E=256'h88388855_5575832e_80258805_2e933872_59577582_5a575758_80258205_33703070;
-defparam bootram.RAM1.INIT_0F=256'h2cff0577_97387681_5472802e_259e3872_80548177_9f2a5153_55733070_7383388a;
-defparam bootram.RAM1.INIT_10=256'h7281ff06_51aea93f_5474527b_73538180_80548639_07515454_7072842b_7131fe05;
-defparam bootram.RAM1.INIT_11=256'h0d029f05_0d04fb3d_8f3f893d_80da51ae_973f8152_811851ae_9f3f7352_527751ae;
-defparam bootram.RAM1.INIT_12=256'hade63f81_5280c551_fe3d0d81_873d0d04_51fee63f_53785275_80ca54bd_33568155;
-defparam bootram.RAM1.INIT_13=256'h0781e080_80087090_f33881e0_5372802e_0881ff06_feb83f80_3f8f883f_528151d6;
-defparam bootram.RAM1.INIT_14=256'h52527080_72177033_76279e38_54805372_57817056_0d787a57_0d04fa3d_0c53843d;
-defparam bootram.RAM1.INIT_15=256'h83388151_5170802e_39747407_811353df_83388055_7181ff2e_54713352_2e833880;
-defparam bootram.RAM1.INIT_16=256'h3f843d0d_c451beb1_a45280e4_865380dc_80e5c034_3d0d810b_3d0d04fe_70800c88;
-defparam bootram.RAM1.INIT_17=256'hd051ade5_56825280_873d7054_c0348654_810b80e5_5574bc38_80e5c033_04f93d0d;
-defparam bootram.RAM1.INIT_18=256'h86537552_55748c38_0881ff06_fef43f80_86527551_802e9c38_ff065574_3f800881;
-defparam bootram.RAM1.INIT_19=256'he4c00c04_dca00880_e5bc3480_04810b80_0c893d0d_e4c40b80_bde73f80_80e4c451;
-defparam bootram.RAM1.INIT_1A=256'h51ad863f_8c5280d0_3dfc0553_34845487_0b80e5bc_74b93881_e5bc3355_fb3d0d80;
-defparam bootram.RAM1.INIT_1B=256'h86387580_ff065574_3f800881_0551fe92_52873dfc_2e993884_06557480_800881ff;
-defparam bootram.RAM1.INIT_1C=256'hcc3f8008_80d051ab_75538c52_77568454_04fb3d0d_0c873d0d_e4c00b80_e4c00c80;
-defparam bootram.RAM1.INIT_1D=256'h803d0d73_873d0d04_3474800c_0b80e5bc_e4c00c81_38750880_74802e8d_81ff0655;
-defparam bootram.RAM1.INIT_1E=256'h73097375_04803d0d_51823d0d_81e08c0c_80e5c40c_08060770_7180e5c4_09737506;
-defparam bootram.RAM1.INIT_1F=256'h0d747053_3f04fe3d_0d0481af_0c51823d_0c81e098_7080e5c8_c8080607_067180e5;
-defparam bootram.RAM1.INIT_20=256'h3d0d7779_3d0d04fb_81b63f83_8a528051_04ff3d0d_0c843d0d_c73f7280_53805181;
-defparam bootram.RAM1.INIT_21=256'he539800b_5581913f_06537652_157481ff_2e903881_54547280_7081ff06_56567433;
-defparam bootram.RAM1.INIT_22=256'hffbd3f8a_53705253_3d0d7476_3d0d04fe_51cd3f83_0d735280_0d04ff3d_800c873d;
-defparam bootram.RAM1.INIT_23=256'h3d0d7251_3d0d0480_51dd3f83_0d735280_0d04ff3d_800c843d_e73f800b_52725180;
-defparam bootram.RAM1.INIT_24=256'h05702272_1080dcac_90800575_73a02982_04ff3d0d_34823d0d_80e4cc12_028f0533;
-defparam bootram.RAM1.INIT_25=256'h7251ce3f_d0133352_c63f80e4_33527251_80e4cc13_3d0d8053_3d0d04fe_0c535183;
-defparam bootram.RAM1.INIT_26=256'he4cc1433_06953880_8a2e0981_78565474_fc3d0d76_843d0d04_7325e538_81135382;
-defparam bootram.RAM1.INIT_27=256'h802ef838_14085372_80055484_a0298290_51de3f73_388d5273_09810687_5372812e;
-defparam bootram.RAM1.INIT_28=256'h85389012_5370802e_085252ff_80058811_a0298290_fe3d0d74_863d0d04_748c150c;
-defparam bootram.RAM1.INIT_29=256'h800c7088_ff0681a8_d8227081_880c80e4_800b81a8_04ff3d0d_0c843d0d_08537280;
-defparam bootram.RAM1.INIT_2A=256'h55535481_05970533_76780288_04fd3d0d_0c833d0d_0b81a888_0c518180_2a81a884;
-defparam bootram.RAM1.INIT_2B=256'ha88c0c81_10810781_70f13872_06515151_862a7081_a8900870_81863881_5171802e;
-defparam bootram.RAM1.INIT_2C=256'h2a708106_90087087_f13881a8_51515170_2a708106_90087081_900c81a8_900b81a8;
-defparam bootram.RAM1.INIT_2D=256'h81a8900c_38a05170_71812e83_3880e851_71802eb1_802eba38_51515170_70813251;
-defparam bootram.RAM1.INIT_2E=256'hff1252cc_81055634_51707470_81a88c08_5170f138_81065151_70812a70_81a89008;
-defparam bootram.RAM1.INIT_2F=256'h05335553_02880597_3d0d7678_3d0d04fd_70800c85_81a8900c_3980c00b_39815188;
-defparam bootram.RAM1.INIT_30=256'h2e843881_d0517180_a88c0c81_38721081_515170f1_70810651_0870862a_5481a890;
-defparam bootram.RAM1.INIT_31=256'h872a7081_a8900870_70f13881_06515151_812a7081_a8900870_a8900c81_90517081;
-defparam bootram.RAM1.INIT_32=256'h5171812e_8c0c80d0_733381a8_2e80c538_cf387180_70802e80_51515151_06708132;
-defparam bootram.RAM1.INIT_33=256'h0870872a_3881a890_515170f1_70810651_0870812a_0c81a890_7081a890_83389051;
-defparam bootram.RAM1.INIT_34=256'h80c00b81_81518a39_54ffb739_14ff1353_2e8e3881_51517080_81325151_70810670;
-defparam bootram.RAM1.INIT_35=256'h5281b8ac_81b8ac08_74259b38_54805372_fd3d0d75_853d0d04_5170800c_a8900c80;
-defparam bootram.RAM1.INIT_36=256'h80880c81_0dff0b82_0d04ff3d_e239853d_38811353_9f7127f1_5151868d_08707331;
-defparam bootram.RAM1.INIT_37=256'h8405540c_9efc7270_f0528751_8c0c80ef_ff0b8280_8280840c_800cef0b_e20b8280;
-defparam bootram.RAM1.INIT_38=256'h51528053_08710658_0982808c_80880870_fb3d0d82_833d0d04_8025f138_ff115170;
-defparam bootram.RAM1.INIT_39=256'h8f398113_82808c0c_52712d74_72517308_802e8f38_76065271_f0555574_810b80ef;
-defparam bootram.RAM1.INIT_3A=256'h2980eff0_9f387184_52718726_ff3d0d73_873d0d04_7325dc38_57555387_84157610;
-defparam bootram.RAM1.INIT_3B=256'h04ff3d0d_833d0d04_0c535152_06828088_88087072_70098280_5181722b_0575710c;
-defparam bootram.RAM1.INIT_3C=256'h0c81b8a0_0b81e0cc_803d0d81_833d0d04_81e0c80c_e0c40c52_74700881_02920522;
-defparam bootram.RAM1.INIT_3D=256'h04fe3d0d_81e0c00c_04de3f71_0c823d0d_0b81e0cc_2ef33882_51517080_08708406;
-defparam bootram.RAM1.INIT_3E=256'h80529a39_53538180_902a710c_a0087571_933881b8_5272802e_70810654_81b8a008;
-defparam bootram.RAM1.INIT_3F=256'h843d0d04_5271800c_ff9e3f72_51f8d33f_3880dcb8_71802e8b_81065152_71812a70;
-defparam bootram.RAM2.INIT_00=256'hff3d0d02_823d0d04_800b800c_f2388180_5170802e_80c00651_b8a00870_803d0d81;
-defparam bootram.RAM2.INIT_01=256'h0b81e0cc_2ef33884_51517080_08709006_5281b8a0_81e0cc0c_902b8807_8e052270;
-defparam bootram.RAM2.INIT_02=256'ha5c63f81_70335252_a53f7214_38ba51f7_72802e86_75548053_04fd3d0d_0c833d0d;
-defparam bootram.RAM2.INIT_03=256'h33535680_11335470_11335581_11335682_3d0d7783_3d0d04fb_27e63885_13538573;
-defparam bootram.RAM2.INIT_04=256'h515b5f5d_30709f2a_bb053370_63029005_0d7c7e61_0d04f63d_ed3f873d_dcbc5180;
-defparam bootram.RAM2.INIT_05=256'h55785480_26943879_30577777_51782d76_387952ad_75802e8a_80258f38_5b595776;
-defparam bootram.RAM2.INIT_06=256'h51782d8c_dcc80533_3f800880_7651ada4_bd3f7752_800851ff_51ad8c3f_53775276;
-defparam bootram.RAM2.INIT_07=256'h08a1e35c_70840552_0d8c3d70_0d04f73d_8d3f823d_053351f6_3d0d028b_3d0d0480;
-defparam bootram.RAM2.INIT_08=256'hdb388119_09810680_5675a52e_7681ff06_2e81d138_57577580_7081ff06_5a587833;
-defparam bootram.RAM2.INIT_09=256'h3875802e_80e3248a_2eb93875_387580e3_80f024a0_80fb3875_7580f02e_70335759;
-defparam bootram.RAM2.INIT_0A=256'h7580f32e_f5248b38_ac387580_7580f52e_38818b39_e42e80c6_95397580_819e3881;
-defparam bootram.RAM2.INIT_0B=256'h792d80da_80527551_33525956_84198312_80ec3977_f82eba38_f5397580_80db3880;
-defparam bootram.RAM2.INIT_0C=256'ha1e35481_59568055_19710852_90397784_e3548053_568055a1_71085259_39778419;
-defparam bootram.RAM2.INIT_0D=256'h39778419_fdd03f9e_90527551_e3548053_568055a1_71085259_39778419_538a5292;
-defparam bootram.RAM2.INIT_0E=256'h59fea339_ec398119_3351792d_70810558_38805276_75802e8e_56763356_71085959;
-defparam bootram.RAM2.INIT_0F=256'h51515170_2a708106_90087088_3d0d81a0_940c0480_810b81a0_8b3d0d04_800b800c;
-defparam bootram.RAM2.INIT_10=256'h5354d03f_c0800755_06077080_067b8c80_337980ff_0d029705_0d04fd3d_f138823d;
-defparam bootram.RAM2.INIT_11=256'h73517380_81a0900c_80c28007_a0900c71_800c7281_0c7781a0_0681a098_7683ffff;
-defparam bootram.RAM2.INIT_12=256'h53727427_54555580_0d76787a_0d04fc3d_800c853d_80085170_aa3f81a0_2e8938ff;
-defparam bootram.RAM2.INIT_13=256'hff067290_387183ff_70802e8d_71902a51_5351ee39_05811555_15702273_8f387210;
-defparam bootram.RAM2.INIT_14=256'h0880e5d8_f43f7670_e5d051ae_53755280_fd3d0d86_863d0d04_3971800c_2a0552ec;
-defparam bootram.RAM2.INIT_15=256'h38833d0d_708025f3_ff125252_720c8812_52895180_0d80e5e0_0d04ff3d_0c54853d;
-defparam bootram.RAM2.INIT_16=256'h52528972_81128812_742e8e38_70225472_e5dc5252_53800b80_02960522_04fd3d0d;
-defparam bootram.RAM2.INIT_17=256'h08802e89_56c73f80_ff065358_7a7183ff_fa3d0d78_853d0d04_5170800c_25ee3880;
-defparam bootram.RAM2.INIT_18=256'h802e8f38_15555271_55730888_e5dc5555_e5e00b80_39800880_84050cad_38768008;
-defparam bootram.RAM2.INIT_19=256'h86705493_04f13d0d_0c883d0d_23768414_883f7573_25eb389c_54558975_81158814;
-defparam bootram.RAM2.INIT_1A=256'h028405a2_b43f9080_dc0551ad_0552913d_53923d88_adc33f73_d6055254_3d53923d;
-defparam bootram.RAM2.INIT_1B=256'h052380c0_028405aa_23818080_800b8c3d_05a60523_23800284_800b8b3d_0523818a;
-defparam bootram.RAM2.INIT_1C=256'h80080284_51fdb73f_913de405_80538a52_685d665e_05ae0523_23800284_910b8d3d;
-defparam bootram.RAM2.INIT_1D=256'hbe0523ac_80028405_0b913d23_ba052380_22028405_3d23963d_983d2290_05ae0523;
-defparam bootram.RAM2.INIT_1E=256'h0b973d23_0d805b80_0d04e83d_8c3f913d_8405519e_c02981e6_05526980_53913dd4;
-defparam bootram.RAM2.INIT_1F=256'h80f20522_ac933f02_3df80551_e5d0529a_3f865380_0551aca1_529a3df2_86539b3d;
-defparam bootram.RAM2.INIT_20=256'ha13d0845_05436e44_c41143f0_800b9b3d_8008585a_f73f8008_e20523f7_02840580;
-defparam bootram.RAM2.INIT_21=256'h7508701a_3d568458_fc06408c_3d088305_3d085fa3_5d6e5ea1_59845c90_a33d0846;
-defparam bootram.RAM2.INIT_22=256'h83065473_2e9a3873_08547380_73760c75_75278438_565a5573_80713151_787c3190;
-defparam bootram.RAM2.INIT_23=256'h519cde3f_16085276_75085394_51effb3f_3880dce4_73802e88_08830654_8c389416;
-defparam bootram.RAM2.INIT_24=256'h51f6fd3f_5978822a_843880c0_3878bf26_8025ffac_19595777_570817ff_75708405;
-defparam bootram.RAM2.INIT_25=256'hca052380_02840580_94055a79_3d237f1f_8a800b94_6e404081_ea3d0d6b_9a3d0d04;
-defparam bootram.RAM2.INIT_26=256'h80d20523_80028405_79963d23_c080075a_05236980_840580ce_81808002_0b953d23;
-defparam bootram.RAM2.INIT_27=256'hd2052391_02840580_08095a79_fae03f80_3d70525c_538a5293_46684780_80e5d808;
-defparam bootram.RAM2.INIT_28=256'h7a51f6cb_51f7d73f_3880dd90_065a7992_800881ff_5e8ac83f_3d70535c_3d705398;
-defparam bootram.RAM2.INIT_29=256'h1f5b5b79_5c7b1d7c_90805380_94557b54_586b575d_5a6d5960_a939027f_3fedea3f;
-defparam bootram.RAM2.INIT_2A=256'h3d238d3d_ae05228a_0d7f5802_0d04f73d_893f983d_26ef38fd_1c5c867c_337b3481;
-defparam bootram.RAM2.INIT_2B=256'h3df80553_5588548b_2377567e_8405a605_3d238002_1857768b_a2052388_22028405;
-defparam bootram.RAM2.INIT_2C=256'h0b8f3d34_b2052386_80028405_8e3d2390_3d0d810b_3d0d04ee_fe9e3f8b_91527d51;
-defparam bootram.RAM2.INIT_2D=256'hd03feb80_ec0551a8_0852943d_3f865380_0523eab1_028405b6_b5053481_84028405;
-defparam bootram.RAM2.INIT_2E=256'h3f800808_cd3feae4_f60551a9_8052943d_c03f8653_f20551a8_0852943d_3f845380;
-defparam bootram.RAM2.INIT_2F=256'hdc1b337a_1c5a80dc_53805b7a_05549086_55943de4_5780569c_59805880_43025c80;
-defparam bootram.RAM2.INIT_30=256'h90862e09_225f5d7d_3d088e11_d93d0daa_943d0d04_38fbcb3f_867b26ef_34811b5b;
-defparam bootram.RAM2.INIT_31=256'hb53f86ee_ddc051f5_38795280_799b268d_f2055b5b_3d088429_38901dac_8106829d;
-defparam bootram.RAM2.INIT_32=256'h1b225a79_86d43884_2e098106_5a799080_38821b22_810686e2_79812e09_397a225a;
-defparam bootram.RAM2.INIT_33=256'h853fa81d_70524088_b9389e1d_09810686_5a79812e_38861b22_810686c6_8c842e09;
-defparam bootram.RAM2.INIT_34=256'h08868f38_80085c80_51a6823f_3dffa805_e5d852a9_43845380_fd3f8008_70525f87;
-defparam bootram.RAM2.INIT_35=256'h23841b33_0580fe05_1b220284_a13d2382_e03f7a22_527951a6_5380e5d0_a73d5a86;
-defparam bootram.RAM2.INIT_36=256'h0551a6ad_52a93de4_23865379_05818205_34820284_05818105_1b330284_a23d3485;
-defparam bootram.RAM2.INIT_37=256'h903f7953_527a51a6_8653981d_818e055b_a69f3f02_ea05525a_7f53aa3d_3f847054;
-defparam bootram.RAM2.INIT_38=256'h587c575d_5a7c597c_f83f027c_527e51a5_5f86537a_843f9e3d_f40551a6_7f52a93d;
-defparam bootram.RAM2.INIT_39=256'h993f84ee_26ef38f9_1c5c867c_337b3481_1d5b5b79_537b1d7f_dc05547d_9c55a93d;
-defparam bootram.RAM2.INIT_3A=256'hd1387988_09810684_5b60842e_8c2a435b_1d702270_84e43890_2e098106_397d9080;
-defparam bootram.RAM2.INIT_3B=256'h5e865380_84b4387e_ff065f7e_1b2280ff_84c03886_2e098106_515a7985_2a708f06;
-defparam bootram.RAM2.INIT_3C=256'ha3fb3f80_70535b5c_80e5d854_901c6255_38815e7e_3f800883_1d51a491_dcdc5282;
-defparam bootram.RAM2.INIT_3D=256'h22ec1140_1b33821c_84b83f89_529c1d51_8138881d_7b802e84_5c7d8738_08833881;
-defparam bootram.RAM2.INIT_3E=256'h5d42407d_8411225d_7a08a41f_388c1b08_810683de_7f912e09_2e81bb38_5d407f81;
-defparam bootram.RAM2.INIT_3F=256'hf5c33f80_22535d5d_e41d821d_bd39ac1d_f2843f83_80dde051_79537d52_7a2e8f38;
-defparam bootram.RAM3.INIT_00=256'ha3ef3f9c_7d527951_5f5a8853_9a3d993d_3d237f49_387a2299_802e83a6_08428008;
-defparam bootram.RAM3.INIT_01=256'h51a3ce3f_b4055279_53a93dff_23604788_1b22973d_a3e33f82_79527f51_3d408853;
-defparam bootram.RAM3.INIT_02=256'h811c5c88_79337b34_7c1f5b5b_5e5c7b1d_557e843d_3f7b567c_7d51a3c5_88537952;
-defparam bootram.RAM3.INIT_03=256'h5a792d82_61840508_7b26ef38_811b5b88_84051c34_5a793302_805b7f1b_7c26ef38;
-defparam bootram.RAM3.INIT_04=256'h335a7983_9539811a_81bb3882_387d882e_7d832e8a_33405b42_08a41e70_ad398c1b;
-defparam bootram.RAM3.INIT_05=256'h2251f481_81f4387c_2e098106_5e5c7991_8912335c_1d80c01e_81a238ac_2e098106;
-defparam bootram.RAM3.INIT_06=256'h88537a52_9b3d5c5e_794b983d_229b3d23_1c085a7c_80fe388c_8008802e_3f800841;
-defparam bootram.RAM3.INIT_07=256'h4d8853a9_9d3d2379_5a821d22_3f901c08_7f51a29d_88537d52_3f963d40_7d51a2a9;
-defparam bootram.RAM3.INIT_08=256'h1d7c1f5b_3d5e5c7b_7e557e84_fc3f7e56_527d51a1_3f88537a_7a51a285_3dcc0552;
-defparam bootram.RAM3.INIT_09=256'h887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c_5b79337b;
-defparam bootram.RAM3.INIT_0A=256'h02840580_953d347e_1d5d5d7e_39ac1de4_ad3f80de_80e951e5_085a792d_38608405;
-defparam bootram.RAM3.INIT_0B=256'h53605294_d205237e_02840580_23861a22_1a22963d_ce052384_02840580_cd05347e;
-defparam bootram.RAM3.INIT_0C=256'hce05237b_02840580_08095a79_f1c03f80_2a527c51_08537b81_f1cc3f80_3d70525b;
-defparam bootram.RAM3.INIT_0D=256'h53727427_e6ac0855_0d800b80_0d04fc3d_f73fa93d_526151f5_547a537f_567c557d;
-defparam bootram.RAM3.INIT_0E=256'h39811353_3872518b_09810685_5170752e_088c1353_54565171_0880e6b4_a4387670;
-defparam bootram.RAM3.INIT_0F=256'h8025ba38_b93f8008_535755ff_0d777971_0d04fb3d_800c863d_38ff5170_737326e7;
-defparam bootram.RAM3.INIT_10=256'hb00c5473_870680e6_b0088111_8e3980e6_80e6ac0c_89388114_54738726_80e6ac08;
-defparam bootram.RAM3.INIT_11=256'h80080554_39800810_b8145194_755280e6_51548653_e6b4120c_2b760880_10147082;
-defparam bootram.RAM3.INIT_12=256'h54738008_fed83f80_3d0d7551_3d0d04fd_9fbf3f87_e6b80551_73842980_86537552;
-defparam bootram.RAM3.INIT_13=256'h800c853d_3f815473_76519f95_e6b80552_73842980_05548653_08108008_24993880;
-defparam bootram.RAM3.INIT_14=256'h33710780_72078316_3370882b_2b078214_982b7190_81123371_0d757033_0d04fd3d;
-defparam bootram.RAM3.INIT_15=256'hffff068b_a8387383_56595776_80e79422_3d0d7d7f_3d0d04f9_56545285_0c525354;
-defparam bootram.RAM3.INIT_16=256'h742380c0_05515476_2980e798_29147090_d3387390_73832680_31525654_3d227072;
-defparam bootram.RAM3.INIT_17=256'h3d527390_5488538a_74902915_8326ad38_57575474_22707231_ff068d3d_397383ff;
-defparam bootram.RAM3.INIT_18=256'h1656ec39_e3b23f81_53547451_75177033_78279138_3f805675_05519e85_2980e798;
-defparam bootram.RAM3.INIT_19=256'h88140c80_23800b82_54548073_0b80e798_e7942380_9a052280_fc3d0d02_893d0d04;
-defparam bootram.RAM3.INIT_1A=256'hd938863d_54837427_82901454_9b3f8114_740551ef_80e79422_0cb5ab52_0b828c14;
-defparam bootram.RAM3.INIT_1B=256'h881a085b_be387582_51567581_32708106_847c2c81_e7985a5c_0d800b80_0d04f43d;
-defparam bootram.RAM3.INIT_1C=256'hff06708a_38800881_ff2e80c5_f73f8008_5b7b51e2_781a8805_2680d638_5d7981ff;
-defparam bootram.RAM3.INIT_1D=256'h777b7081_8338815d_5876802e_51595158_80250753_72802571_8d327030_32703072;
-defparam bootram.RAM3.INIT_1E=256'h38828819_7a27ffb1_1a5a81ff_8c1a0c81_0c800b82_0582881a_88190881_055d3482;
-defparam bootram.RAM3.INIT_1F=256'h75802eab_38782256_8b7627bf_8c1b0c56_08811182_38828c19_d2387c91_08802e80;
-defparam bootram.RAM3.INIT_20=256'h887826ef_34811858_57753377_1a781a57_3d5b5877_54800b83_08558819_38828819;
-defparam bootram.RAM3.INIT_21=256'h5a5c837c_1c82901a_8c1a0c81_0c800b82_0b82881a_f2a83f80_227c0551_3880e794;
-defparam bootram.RAM3.INIT_22=256'h9d055755_80028405_5194d53f_80c05268_3d705457_ea3d0d88_8e3d0d04_27fea938;
-defparam bootram.RAM3.INIT_23=256'h81992e09_33515473_38741670_09810694_7381aa2e_ff2e9d38_51547381_74177033;
-defparam bootram.RAM3.INIT_24=256'h863d7054_04f93d0d_0c983d0d_80547380_7527d138_811555be_81548b39_81068538;
-defparam bootram.RAM3.INIT_25=256'h83388155_2e098106_3f800875_735199e5_80de8452_80558453_5194853f_54845279;
-defparam bootram.RAM3.INIT_26=256'h55805189_0881ff06_8add3f80_0d8df23f_0c04fc3d_0b81e094_3d0d0481_74800c89;
-defparam bootram.RAM3.INIT_27=256'h80dec051_3974b538_88518183_883880de_51515473_2a708106_b408708d_dc3f81b8;
-defparam bootram.RAM3.INIT_28=256'h82ac51e3_5189a23f_ded83f81_80deec51_802e9a38_bf3f8008_800a51fe_deec3fb0;
-defparam bootram.RAM3.INIT_29=256'h3880dff0_08802ebb_fee33f80_98800a51_5180cc39_3f80dfa4_0a5184b5_8b3fb080;
-defparam bootram.RAM3.INIT_2A=256'h51e2cd3f_953f82ac_e09c51de_92da3f80_98800a51_80ffff52_83808053_51deab3f;
-defparam bootram.RAM3.INIT_2B=256'hf13f863d_e0fc51dd_3f883980_805183e9_51e2bd3f_853f82ac_e0c051de_fee53f80;
-defparam bootram.RAM3.INIT_2C=256'h3f80efd8_a051dca0_dd3fa052_c85254e6_705380e1_fd3d0d75_efd80c04_0d047180;
-defparam bootram.RAM3.INIT_2D=256'h08537280_3f80efd8_8051dc84_3d0da052_3d0d04fe_51722d85_2e853873_08537280;
-defparam bootram.RAM3.INIT_2E=256'h51535481_2a708106_0b800886_89a83fff_3d0d9a51_3d0d04fc_51722d84_2e853880;
-defparam bootram.RAM3.INIT_2F=256'h248a388a_38718280_82802e9b_80e45471_80065355_0b800886_80ec3882_5571802e;
-defparam bootram.RAM3.INIT_30=256'h5188db3f_80085285_5188e33f_38ff5484_84802e83_87e85471_8e388a39_5471802e;
-defparam bootram.RAM3.INIT_31=256'h53515452_80e28055_80efe40c_c0113370_720780e2_2c708306_0680088a_71882a8c;
-defparam bootram.RAM3.INIT_32=256'hefdc0c74_98387480_efdc082e_9d3f7480_085252dc_80e4e011_822b8c06_dc843f71;
-defparam bootram.RAM3.INIT_33=256'he0082e8e_387380ef_09810696_3974822e_fec13f9e_8106a338_74812e09_822ea638;
-defparam bootram.RAM3.INIT_34=256'h3f800851_3d0dd8c5_3d0d04fd_87e83f86_fb3f9951_3f7351fd_e00cfea7_387380ef;
-defparam bootram.RAM3.INIT_35=256'hae80529c_87f13f81_8d529851_5187c73f_efe00c99_0cff0b80_0b80efdc_87bd3f80;
-defparam bootram.RAM3.INIT_36=256'h845187cb_06705354_8007f49f_3f800890_845187aa_51e1853f_bbcb5284_5187e83f;
-defparam bootram.RAM3.INIT_37=256'h3f800884_805186fe_51e3fb3f_5280e298_80085373_082e8d38_953f7380_3f845187;
-defparam bootram.RAM3.INIT_38=256'h71832a84_71872a07_852a8206_97053370_fd3d0d02_853d0d04_5187a43f_80075280;
-defparam bootram.RAM3.INIT_39=256'h852b80c0_81ff0676_73070770_2ba00671_90067483_07077310_88067173_0672812a;
-defparam bootram.RAM3.INIT_3A=256'h04fe3d0d_52853d0d_55525555_51525351_82c0800c_7081ff06_78872b07_06707207;
-defparam bootram.RAM3.INIT_3B=256'h9951ff8c_ff923f81_3f81aa51_ff51ff98_ff9e3f81_5381ff51_81d00a07_74d00a06;
-defparam bootram.RAM3.INIT_3C=256'h51feed3f_7281ff06_52fef53f_81ff0652_72882a70_51ff813f_873f80e1_3fb251ff;
-defparam bootram.RAM3.INIT_3D=256'hcf3fb051_065253fe_2a7081ff_db3f7290_982a51fe_fee23f72_3f818151_b251fee8;
-defparam bootram.RAM3.INIT_3E=256'h3fa051fe_8051feb0_51feb53f_feba3fa0_bf3f8e51_3f8051fe_a151fec4_feca3f81;
-defparam bootram.RAM3.INIT_3F=256'h3f863d22_d05183e9_53805280_873dfc05_3d0d8254_3d0d04fb_fea63f84_ab3f8051;
-defparam bootram.RAM4.INIT_00=256'h90387753_77829326_08585957_3d088412_3d0880d7_3d0d80d5_0d04ffb2_800c873d;
-defparam bootram.RAM4.INIT_01=256'h9c055675_842980e3_81cc3875_56759626_39ff9f16_c93f81d6_e2d051e1_82945280;
-defparam bootram.RAM4.INIT_02=256'he1880c89_0c800b81_0b81e184_e1800c80_890a0b81_8008085e_5cd5f93f_080480c1;
-defparam bootram.RAM4.INIT_03=256'h9a3f8008_818a398c_81e4d00c_c80c800b_800b81e2_81e2c40c_c00c800b_0a0b81e2;
-defparam bootram.RAM4.INIT_04=256'h39901708_d65c80e8_ff065e80_800883ff_39fedc3f_c65c80f8_80085f80_5e8c9e3f;
-defparam bootram.RAM4.INIT_05=256'hff065675_3f800881_90518abb_d33980f0_80c55c80_5189f63f_5280f090_538c1708;
-defparam bootram.RAM4.INIT_06=256'h80d75ca4_5188dd3f_528c1708_53901708_b7399417_3980c25c_80c45cbc_802e8638;
-defparam bootram.RAM4.INIT_07=256'h51fcde3f_80d35c80_d25c8d39_8bba3f80_8c170851_90170852_fe800553_3980d03d;
-defparam bootram.RAM4.INIT_08=256'h57753377_3d790557_771980d2_833d5a58_0554800b_d03dfdec_82945580_8339a05c;
-defparam bootram.RAM4.INIT_09=256'hd6883fff_80e3f851_04803d0d_80d03d0d_51e8a33f_38838082_887826ec_34811858;
-defparam bootram.RAM4.INIT_0A=256'h75538152_80559854_07575788_3371882b_8405ab05_a7053302_f93d0d02_5183983f;
-defparam bootram.RAM4.INIT_0B=256'hb7387581_54807425_74ff1656_5a575758_7a7c7f7f_04f83d0d_3f893d0d_8051e1a2;
-defparam bootram.RAM4.INIT_0C=256'hff0651d8_05527781_538a3dfc_a1053482_33028405_70810558_8a3d3476_17575473;
-defparam bootram.RAM4.INIT_0D=256'h04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e_8a51da80_81ff0654_d23f8008;
-defparam bootram.RAM4.INIT_0E=256'hd051ff89_81f75280_3dfc0553_34815488_5675883d_748338dc_5580de56_02a30533;
-defparam bootram.RAM4.INIT_0F=256'h705256d7_02a70533_3dfc0552_34815389_0533893d_7c5702ab_04f93d0d_3f883d0d;
-defparam bootram.RAM4.INIT_10=256'h3f800881_7551d6b5_76537b52_77259738_2e9e3880_56547380_81ff0670_f23f8008;
-defparam bootram.RAM4.INIT_11=256'h5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89_83388155_5473802e_ff067056;
-defparam bootram.RAM4.INIT_12=256'h3d0d0499_75800c88_83388156_2e098106_567480de_883d3356_a03f800b_80d051ff;
-defparam bootram.RAM4.INIT_13=256'h0d72882b_0c04803d_0b81c0b0_ac0c89b0_a60b81c0_81c0800c_0c80eb0b_0b81c094;
-defparam bootram.RAM4.INIT_14=256'h515170f1_70810651_0870812a_0c81c0a4_0b81c0a0_980c5182_810781c0_be800670;
-defparam bootram.RAM4.INIT_15=256'h7381c09c_c0980c51_70810781_2bbe8006_3d0d7288_3d0d0480_08800c82_3881c0a8;
-defparam bootram.RAM4.INIT_16=256'h39fa3d0d_3d0d04ff_70f13882_06515151_812a7081_c0a40870_c0a00c81_0c840b81;
-defparam bootram.RAM4.INIT_17=256'h38815188_71802e86_72830652_52718a38_38758306_57577191_83065555_787a7c72;
-defparam bootram.RAM4.INIT_18=256'h1454e939_52545281_7008720c_77117712_3873822b_73752794_2a725555_ca3f7282;
-defparam bootram.RAM4.INIT_19=256'h0680e484_c13f728f_515353d1_84113354_8f0680e4_70842a70_fe3d0d74_883d0d04;
-defparam bootram.RAM4.INIT_1A=256'hf138823d_51515170_2a708106_90087088_3d0d82e0_3d0d0480_d1b43f84_11335253;
-defparam bootram.RAM4.INIT_1B=256'h70882a70_82e09008_80075353_060780c0_067a8c80_337880ff_0d029305_0d04fe3d;
-defparam bootram.RAM4.INIT_1C=256'h800782e0_980c7182_ff0682e0_900c7581_0c7182e0_7682e080_5170f138_81065151;
-defparam bootram.RAM4.INIT_1D=256'h08517080_3882e080_515170f1_70810651_0870882a_3882e090_72802e96_900c7251;
-defparam bootram.RAM4.INIT_1E=256'h863d0d04_51ff873f_53805280_55885480_940c8880_810b82e0_04fc3d0d_0c843d0d;
-defparam bootram.RAM4.INIT_1F=256'h04fc3d0d_0c863d0d_81ff0680_f13f8008_528151fe_8a805381_80559054_fc3d0d88;
-defparam bootram.RAM4.INIT_20=256'h06800c82_08813281_0dca3f80_0d04803d_d53f863d_528051fe_54865381_88805588;
-defparam bootram.RAM4.INIT_21=256'h84e33f75_3d0d7756_3d0d04fb_2ef43882_06517080_800881ff_3d0deb3f_3d0d0480;
-defparam bootram.RAM4.INIT_22=256'hfe843f87_81528051_9b0a0753_fe9b0a06_55a05475_b43f8880_38dd3fff_8008269b;
-defparam bootram.RAM4.INIT_23=256'h38751754_ff2681b4_80557381_11565757_cb3d08ff_c93d0880_ba3d0d80_3d0d04ff;
-defparam bootram.RAM4.INIT_24=256'h3d085273_755380cb_548c8f3f_883d7052_5381ff52_a7388280_80082681_849f3f73;
-defparam bootram.RAM4.INIT_25=256'h0a0680c0_0c76fec0_0b82e090_980c8880_3f7482e0_d43ffd9f_fefd3ffe_518aea3f;
-defparam bootram.RAM4.INIT_26=256'h3f80c83d_900cfcef_a00b82e0_e0900c8a_88a00b82_82e0980c_800c810b_0a0782e0;
-defparam bootram.RAM4.INIT_27=256'h82e0840c_88157008_880c54fe_700882e0_54fe8415_82e08c0c_80157008_558f56fe;
-defparam bootram.RAM4.INIT_28=256'hff169016_0cfcb03f_0b82e090_900c8a80_800b82e0_800c5488_700882e0_54fe8c15;
-defparam bootram.RAM4.INIT_29=256'h7b7d7212_f93d0d79_c83d0d04_74800c80_980c8155_800b82e0_25ffbc38_56567580;
-defparam bootram.RAM4.INIT_2A=256'h5473802e_7581ff06_2e80c338_81577480_2680cb38_57738008_82db3f80_575a5656;
-defparam bootram.RAM4.INIT_2B=256'h19767631_3f731674_7551fdeb_77537352_83387654_57767527_74317555_a2388280;
-defparam bootram.RAM4.INIT_2C=256'h0c893d0d_81577680_39fd8c3f_828054dc_7527e138_74548280_802e8e38_57595674;
-defparam bootram.RAM4.INIT_2D=256'h0b88160c_27903880_3f800874_135481ed_2e8d3873_54557380_76787a56_04fc3d0d;
-defparam bootram.RAM4.INIT_2E=256'h08307276_81bd3f80_16565152_707406ff_3f800830_a63981cb_0c80750c_800b8416;
-defparam bootram.RAM4.INIT_2F=256'h0881ff06_fc983f80_3d0d7554_3d0d04fd_fcc93f86_160c7151_160c7188_0c740684;
-defparam bootram.RAM4.INIT_30=256'h7088160c_08800805_823f8814_2e943881_08841508_81538814_802e9f38_70545271;
-defparam bootram.RAM4.INIT_31=256'h51faa33f_53815281_5481f90a_888055a0_04fc3d0d_0c853d0d_80537280_51fc943f;
-defparam bootram.RAM4.INIT_32=256'h81ff0680_08882a70_38d73f80_efe808a0_ff3d0d80_863d0d04_0a06800c_8008fe80;
-defparam bootram.RAM4.INIT_33=256'h82712784_ea115252_80efe808_80efe80c_06933871_a02e0981_54515170_0881ff06;
-defparam bootram.RAM4.INIT_34=256'h082b800c_3f810b80_800c04f3_e4da0533_3f800880_3d0d04c0_71800c83_38f5b23f;
-defparam bootram.RAM4.INIT_35=256'h0b82e090_980c8880_800b82e0_56f9983f_f63d0d7d_2b800c04_810b8008_04ffa93f;
-defparam bootram.RAM4.INIT_36=256'ha80b82e0_e0900c8a_88a80b82_82e0980c_800c810b_882b82e0_e0840c7c_0c8b0b82;
-defparam bootram.RAM4.INIT_37=256'h0cf8cc3f_0b82e090_900c8a80_800b82e0_80d33888_54737627_3f7e5580_900cf8e7;
-defparam bootram.RAM4.INIT_38=256'h53707327_31525790_883d7675_e080085b_84085a82_085982e0_5882e088_82e08c08;
-defparam bootram.RAM4.INIT_39=256'h1454ffa9_52ec3972_57348112_75708105_17517033_27913871_80527173_83387053;
-defparam bootram.RAM4.INIT_3A=256'h538c088c_fd3d0d80_08028c0c_f7893f8c_3d0d7251_3d0d0480_e0980c8c_39800b82;
-defparam bootram.RAM4.INIT_3B=256'h0cfd3d0d_8c08028c_0d8c0c04_0c54853d_80087080_5182de3f_08880508_0508528c;
-defparam bootram.RAM4.INIT_3C=256'h048c0802_3d0d8c0c_800c5485_3f800870_085182b9_8c088805_8c050852_81538c08;
-defparam bootram.RAM4.INIT_3D=256'h0888050c_0508308c_388c0888_088025ab_8c088805_08fc050c_0d800b8c_8c0cf93d;
-defparam bootram.RAM4.INIT_3E=256'hfc050c8c_05088c08_0c8c08f4_8c08f405_8838810b_08fc0508_f4050c8c_800b8c08;
-defparam bootram.RAM4.INIT_3F=256'hfc050888_050c8c08_0b8c08f0_8c050c80_08308c08_8c088c05_8025ab38_088c0508;
-defparam bootram.RAM5.INIT_00=256'h88050851_08528c08_8c088c05_050c8053_088c08fc_8c08f005_08f0050c_38810b8c;
-defparam bootram.RAM5.INIT_01=256'h08f8050c_0508308c_388c08f8_08802e8c_8c08fc05_f8050c54_08708c08_81a73f80;
-defparam bootram.RAM5.INIT_02=256'h050c8c08_0b8c08fc_fb3d0d80_08028c0c_8c0c048c_54893d0d_0870800c_8c08f805;
-defparam bootram.RAM5.INIT_03=256'h05088025_0c8c088c_8c08fc05_050c810b_308c0888_08880508_2593388c_88050880;
-defparam bootram.RAM5.INIT_04=256'h3f800870_050851ad_528c0888_088c0508_0c81538c_8c088c05_8c050830_8c388c08;
-defparam bootram.RAM5.INIT_05=256'hf8050870_050c8c08_308c08f8_08f80508_2e8c388c_fc050880_0c548c08_8c08f805;
-defparam bootram.RAM5.INIT_06=256'hf8050c8c_800b8c08_08fc050c_0d810b8c_8c0cfd3d_048c0802_3d0d8c0c_800c5487;
-defparam bootram.RAM5.INIT_07=256'h2499388c_088c0508_38800b8c_08802ea3_8c08fc05_0827ac38_8c088805_088c0508;
-defparam bootram.RAM5.INIT_08=256'h802e80c9_08fc0508_0cc9398c_8c08fc05_fc050810_050c8c08_108c088c_088c0508;
-defparam bootram.RAM5.INIT_09=256'h050c8c08_318c0888_088c0508_8805088c_a1388c08_88050826_05088c08_388c088c;
-defparam bootram.RAM5.INIT_0A=256'h8c050881_050c8c08_2a8c08fc_fc050881_050c8c08_078c08f8_08fc0508_f805088c;
-defparam bootram.RAM5.INIT_0B=256'h0c518d39_8c08f405_88050870_8f388c08_0508802e_398c0890_050cffaf_2a8c088c;
-defparam bootram.RAM5.INIT_0C=256'h78777956_04fc3d0d_3d0d8c0c_08800c85_8c08f405_f4050c51_08708c08_8c08f805;
-defparam bootram.RAM5.INIT_0D=256'h74335253_a0387433_5271ff2e_b038ff12_5170802e_74078306_278c3874_56528372;
-defparam bootram.RAM5.INIT_0E=256'h0c863d0d_38800b80_098106e2_5571ff2e_ff145455_81158115_8106bd38_72712e09;
-defparam bootram.RAM5.INIT_0F=256'h38707355_718326e9_14545451_118414fc_068f3884_082e0981_51700873_04747454;
-defparam bootram.RAM5.INIT_10=256'h38727507_8f72278c_55555555_7670797b_04fc3d0d_0c863d0d_72713180_55ffaf39;
-defparam bootram.RAM5.INIT_11=256'hff125271_81055634_54337470_72708105_ff2e9838_ff125271_802ea738_83065170;
-defparam bootram.RAM5.INIT_12=256'h72708405_8405530c_54087170_72708405_0d047451_800c863d_06ea3874_ff2e0981;
-defparam bootram.RAM5.INIT_13=256'h8405530c_54087170_72708405_8405530c_54087170_72708405_8405530c_54087170;
-defparam bootram.RAM5.INIT_14=256'h718326ed_0cfc1252_70840553_05540871_38727084_83722795_8f26c938_f0125271;
-defparam bootram.RAM5.INIT_15=256'h83065170_278a3874_53558372_05335755_028c059f_0d767971_8339fc3d_387054ff;
-defparam bootram.RAM5.INIT_16=256'hef387480_2e098106_125271ff_055534ff_73737081_ff2e9338_ff125271_802ea238;
-defparam bootram.RAM5.INIT_17=256'h05530c72_72717084_7227a538_5154518f_71902b07_2b750770_04747488_0c863d0d;
-defparam bootram.RAM5.INIT_18=256'h83722790_8f26dd38_f0125271_8405530c_0c727170_70840553_530c7271_71708405;
-defparam bootram.RAM5.INIT_19=256'h54555552_787a7c70_39fa3d0d_7053ff90_8326f238_fc125271_8405530c_38727170;
-defparam bootram.RAM5.INIT_1A=256'h74335651_b1387133_5372ff2e_d438ff13_70802e80_07830651_d9387174_72802e80;
-defparam bootram.RAM5.INIT_1B=256'h15ff1555_38811281_802e80fc_ff065170_87387081_72802e81_8106a938_74712e09;
-defparam bootram.RAM5.INIT_1C=256'h52527080_71713151_7581ff06_7081ff06_74335651_d1387133_2e098106_555272ff;
-defparam bootram.RAM5.INIT_1D=256'hfc135372_52ff9739_38747655_74082e88_88387108_55837327_04717457_0c883d0d;
-defparam bootram.RAM5.INIT_1E=256'h15841757_709a3884_06515151_84828180_120670f8_f7fbfdff_74087009_802eb138;
-defparam bootram.RAM5.INIT_1F=256'hfd3d0d80_883d0d04_800b800c_52fedf39_38747655_76082ed0_d0387408_55837327;
-defparam bootram.RAM5.INIT_20=256'h528151ff_3f80e4f4_3fffafe8_0cffb0cc_7380efec_812e9e38_08545472_0b80e4b4;
-defparam bootram.RAM5.INIT_21=256'hffb7c13f_f4528151_cb3f80e4_af3fffaf_ec0cffb0_3f7280ef_0851f6a3_b7de3f80;
-defparam bootram.RAM5.INIT_22=256'h2dfc1270_2e913870_525270ff_fc057008_80e4fc0b_39ff3d0d_863f00ff_800851f6;
-defparam bootram.RAM5.INIT_23=256'h21457272_00000040_04000000_ffb0da3f_3d0d0404_06f13883_ff2e0981_08525270;
-defparam bootram.RAM5.INIT_24=256'h3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f_6f722069;
-defparam bootram.RAM5.INIT_25=256'h25642c20_62657220_206e756d_6c697479_74696269_6f6d7061_65642063_70656374;
-defparam bootram.RAM5.INIT_26=256'h6c207061_6e74726f_6e20636f_6f722069_21457272_25640a00_676f7420_62757420;
-defparam bootram.RAM5.INIT_27=256'h6164206c_61796c6f_65642070_70656374_3a204578_646c6572_2068616e_636b6574;
-defparam bootram.RAM5.INIT_28=256'h206c696e_0a657468_0a000000_74202564_7420676f_2c206275_68202564_656e6774;
-defparam bootram.RAM5.INIT_29=256'h50204e32_0a555352_640a0000_203d2025_70656564_643a2073_616e6765_6b206368;
-defparam bootram.RAM5.INIT_2A=256'h70617469_20636f6d_46504741_720a0000_6f616465_6f6f746c_44502062_31302055;
-defparam bootram.RAM5.INIT_2B=256'h20636f6d_77617265_4669726d_640a0000_723a2025_756d6265_7479206e_62696c69;
-defparam bootram.RAM5.INIT_2C=256'h00000000_61646472_640a0000_723a2025_756d6265_7479206e_62696c69_70617469;
-defparam bootram.RAM5.INIT_2D=256'h00000699_00000000_65743a20_7061636b_65727920_65636f76_69702072_476f7420;
-defparam bootram.RAM5.INIT_2E=256'h000006ee_00000705_0000079e_0000079e_0000079e_0000079e_0000079e_0000079e;
-defparam bootram.RAM5.INIT_2F=256'h0000079e_0000079e_0000079e_0000079e_0000079e_00000774_0000079e_0000079e;
-defparam bootram.RAM5.INIT_30=256'h00000762_00000755_0000074e_00000747_00000742_0000073d_000006a6_00000722;
-defparam bootram.RAM5.INIT_31=256'h25642e25_45000000_01b200d9_05160364_14580a2c_3fff0000_0050c285_c0a80a02;
-defparam bootram.RAM5.INIT_32=256'hffffffff_00000000_43444546_38394142_34353637_30313233_2e256400_642e2564;
-defparam bootram.RAM5.INIT_33=256'h6f66206c_656e7420_69676e6d_6420616c_3a206261_5f706b74_73656e64_ffff0000;
-defparam bootram.RAM5.INIT_34=256'h6661696c_6f6e3a20_636f6d6d_6e65745f_66000000_72206275_6e642f6f_656e2061;
-defparam bootram.RAM5.INIT_35=256'h00000000_666f7220_696e6720_6c6f6f6b_63686520_74206361_6f206869_65642074;
-defparam bootram.RAM5.INIT_36=256'h0a000000_3d202564_697a6520_72642073_20776569_6172703a_646c655f_0a68616e;
-defparam bootram.RAM5.INIT_37=256'h2025640a_3a202564_67746873_206c656e_74656e74_6e736973_696e636f_55445020;
-defparam bootram.RAM5.INIT_38=256'h61666520_696e2073_50322b20_20555352_74696e67_53746172_0b0b0b0b_00000000;
-defparam bootram.RAM5.INIT_39=256'h00000000_6172652e_69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465;
-defparam bootram.RAM5.INIT_3A=256'h6e204650_6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563;
-defparam bootram.RAM5.INIT_3B=256'h20465047_74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069;
-defparam bootram.RAM5.INIT_3C=256'h20626f6f_6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d;
-defparam bootram.RAM5.INIT_3D=256'h20696d61_46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000;
-defparam bootram.RAM5.INIT_3E=256'h20627569_6820746f_726f7567_67207468_6c6c696e_2e0a4661_6f756e64_67652066;
-defparam bootram.RAM5.INIT_3F=256'h74696f6e_6f647563_64207072_56616c69_72652e00_726d7761_6e206669_6c742d69;
-defparam bootram.RAM6.INIT_00=256'h46696e69_2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972;
-defparam bootram.RAM6.INIT_01=256'h2e000000_6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564;
-defparam bootram.RAM6.INIT_02=256'h72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f;
-defparam bootram.RAM6.INIT_03=256'h4e6f2076_6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869;
-defparam bootram.RAM6.INIT_04=256'h6e642e20_20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964;
-defparam bootram.RAM6.INIT_05=256'h6669726d_2d696e20_75696c74_746f2062_75676820_7468726f_696e6720_46616c6c;
-defparam bootram.RAM6.INIT_06=256'h4e4f4e45_00000000_2025640a_7420746f_64207365_53706565_2e000000_77617265;
-defparam bootram.RAM6.INIT_07=256'h43000000_45545249_53594d4d_58000000_57455f52_58000000_57455f54_00000000;
-defparam bootram.RAM6.INIT_08=256'h4155544f_5048595f_6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865;
-defparam bootram.RAM6.INIT_09=256'h780a0000_20307825_20676f74_7825782c_74652030_2077726f_4144563a_4e45475f;
-defparam bootram.RAM6.INIT_0A=256'h64617465_6e207570_6f722069_21457272_00030203_00000001_00030003_00000000;
-defparam bootram.RAM6.INIT_0B=256'h796c6f61_64207061_65637465_20457870_6c65723a_68616e64_6b657420_20706163;
-defparam bootram.RAM6.INIT_0C=256'h00002042_00000000_2025640a_20676f74_20627574_2025642c_6e677468_64206c65;
-defparam bootram.RAM6.INIT_0D=256'h00002102_00002102_00002102_0000207b_0000209d_000020b2_00002102_00002102;
-defparam bootram.RAM6.INIT_0E=256'h00002102_00002102_00002102_00002102_00002102_00002102_00002102_00002102;
-defparam bootram.RAM6.INIT_0F=256'h6f72740a_0a0a6162_000020ce_0000208d_00002102_00002102_000020f8_000020e1;
-defparam bootram.RAM6.INIT_10=256'h65000000_792e6578_64756d6d_43444546_38394142_34353637_30313233_00000000;
-defparam bootram.RAM6.INIT_11=256'h00003284_00000000_00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff;
-defparam bootram.RAM6.INIT_12=256'h000b0000_0018000f_ffff0031_05050400_01010100_3fff0000_0050c285_c0a80a02;
-defparam bootram.RAM6.INIT_13=256'h00000000_ffffffff_00003214_10101200_000030f4_000030ec_000030e4_000030dc;
-defparam bootram.RAM6.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_ffffffff;
-defparam bootram.RAM6.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_23=256'h800b80e8_b40c82a0_0b0b80e8_8380800b_822ebd38_80e7e808_802ea438_80e7e408;
+defparam bootram.RAM0.INIT_24=256'h0b80e8b8_80808280_e8b40cf8_0b0b0b80_808080a4_bc0c04f8_800b80e8_b80c8290;
+defparam bootram.RAM0.INIT_25=256'h940b80e8_80c0a880_80e8b40c_8c0b0b0b_80c0a880_e8bc0c04_84800b80_0cf88080;
+defparam bootram.RAM0.INIT_26=256'h70085252_80e7f008_5170a738_80e8c033_04ff3d0d_80e8bc0c_80dca40b_b80c0b0b;
+defparam bootram.RAM0.INIT_27=256'hc034833d_810b80e8_5270ee38_08700852_2d80e7f0_e7f00c70_38841280_70802e94;
+defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e8b008_3d0d0b0b_0d040480;
+defparam bootram.RAM0.INIT_29=256'h389d3d22_5b7a80c4_0da13d08_0404e63d_3f823d0d_0b0bf5d4_e8b0510b_040b0b80;
+defparam bootram.RAM0.INIT_2A=256'h862e8c38_39798380_8e3882fb_8380842e_248b3879_79838085_852eac38_5a798380;
+defparam bootram.RAM0.INIT_2B=256'h0c82d439_7a80e8c4_81e4d00c_0c86397a_0b81e2cc_0c8e3981_0b81e18c_82f13981;
+defparam bootram.RAM0.INIT_2C=256'h82b53979_842e9f38_38798380_8085248b_a7387983_8380852e_225b4079_800ba03d;
+defparam bootram.RAM0.INIT_2D=256'h4288539d_83409a3d_81408339_82408739_3882a439_80872e8c_8b387983_8380862e;
+defparam bootram.RAM0.INIT_2E=256'h9d3df405_963d7053_80cbe43f_3d526251_4388539d_f23f983d_615180cb_3d880552;
+defparam bootram.RAM0.INIT_2F=256'h3f800808_68458cde_22993d23_08498e1b_fb38881b_3d082780_3f8f0ba3_5241acb8;
+defparam bootram.RAM0.INIT_30=256'h9c3de405_08456052_cf3f8008_2e88388c_5b5b7a7a_06657b06_8008087a_5a8ccd3f;
+defparam bootram.RAM0.INIT_31=256'hff5b7a44_51a0da3f_9c3de405_81068b38_797b2e09_065a805b_800881ff_51abf93f;
+defparam bootram.RAM0.INIT_32=256'h887c26ed_34811c5c_5b79337b_3d7d055b_5c7b1d9e_0b833d5e_e0055480_84559c3d;
+defparam bootram.RAM0.INIT_33=256'h621d5b5b_5e5c7b1d_800b883d_615b5f5f_08028405_8bdc3f80_519ff53f_389f3d22;
+defparam bootram.RAM0.INIT_34=256'h811c5c88_79337b34_631d5b5b_5e5c7b1d_800b901f_7c26ef38_811c5c88_79337b34;
+defparam bootram.RAM0.INIT_35=256'h805c7b1e_7c26ef38_811c5c86_79337b34_7f1d5b5b_5e5c7b1d_800b881f_7c26ef38;
+defparam bootram.RAM0.INIT_36=256'h84120859_3d0d686a_3d0d04ee_9af13f9c_7c26ef38_811c5c86_79337b34_611d5b5b;
+defparam bootram.RAM0.INIT_37=256'h95e93f80_80dca851_75538c52_802e8c38_2e943875_0856758c_279c3877_5a588379;
+defparam bootram.RAM0.INIT_38=256'hff9f1756_8818085d_8c5ba05c_d63fa057_dcf85195_53a45280_268e3878_e15778a3;
+defparam bootram.RAM0.INIT_39=256'heb399518_08085e81_8a9a3f80_0480c15c_05567508_2980dee8_81387584_75922682;
+defparam bootram.RAM0.INIT_3A=256'h97193357_0852800b_08538c18_33549018_76559618_83388457_7580f22e_33568257;
+defparam bootram.RAM0.INIT_3B=256'h3dea0553_33705495_b3398d18_80d35c81_3f80085f_76519791_83388157_5775772e;
+defparam bootram.RAM0.INIT_3C=256'h3f80c85c_52568ecc_538c1933_70548e19_398d1833_80c95c94_568dbf3f_8c193352;
+defparam bootram.RAM0.INIT_3D=256'h058c1908_2980dfb4_c2387584_75852680_33ff0556_ff399418_b5053480_75028405;
+defparam bootram.RAM0.INIT_3E=256'h39768429_2277239b_a2399218_1808770c_5fa93990_ae397622_0476085f_58567508;
+defparam bootram.RAM0.INIT_3F=256'h785e80cc_d25cad39_710c5680_05901908_2980e8c4_8e397684_70084056_80e8c405;
+defparam bootram.RAM1.INIT_00=256'h81185888_75337734_79055757_7719963d_833d5a58_0554800b_55943ddc_5c8c1808;
+defparam bootram.RAM1.INIT_01=256'h57753377_3d790557_58771996_0b833d5a_dc055480_a455943d_a439a05c_7826ed38;
+defparam bootram.RAM1.INIT_02=256'hc4525393_705380dd_fe3d0d74_943d0d04_519c8d3f_38838080_887826ed_34811858;
+defparam bootram.RAM1.INIT_03=256'h88b33f72_a0527251_a33f8d39_90b83f9d_c43f8151_52a05188_2e9238a0_863f7280;
+defparam bootram.RAM1.INIT_04=256'h805192c7_8a5280de_5189a43f_3f80dde4_973fa5de_fa3d0d82_843d0d04_5190a73f;
+defparam bootram.RAM1.INIT_05=256'h90fc3f88_3f800851_e23f878e_abe53f87_80e8e00c_be3f820b_dea05192_3f8c5280;
+defparam bootram.RAM1.INIT_06=256'h95b83f86_52800851_86f03f73_3f800854_b53f8780_91963f88_3f800851_c13f878c;
+defparam bootram.RAM1.INIT_07=256'h83808451_3f8ab252_805195fe_d7528380_95c23f8d_518f873f_85528008_ef3f8380;
+defparam bootram.RAM1.INIT_08=256'h875195d6_b2528380_95e03f8a_83808551_3f8ab252_865195ea_b2528380_95f43f8a;
+defparam bootram.RAM1.INIT_09=256'h8e3faea0_90d451ac_518ef33f_a7bb3f80_83809251_5195cb3f_52838082_3f80c3cf;
+defparam bootram.RAM1.INIT_0A=256'h82fdee2e_22555573_80088e05_80c93876_8008802e_3f800856_05518eea_3f883dfc;
+defparam bootram.RAM1.INIT_0B=256'h90e93f94_80decc51_80089a38_80c6f03f_08900551_dec45280_38845380_098106ad;
+defparam bootram.RAM1.INIT_0C=256'h8e3f8ce1_8def3fa7_519c863f_39745275_85e03f88_f93f7351_8fda3f86_16705254;
+defparam bootram.RAM1.INIT_0D=256'h51868f3f_3f9f5280_963f88e6_87ea3f8c_3f82b73f_c23f92b1_fe3d0d86_3fff9e39;
+defparam bootram.RAM1.INIT_0E=256'h885185d1_c83f8852_82ac518b_5185de3f_3f845284_ac518bd5_85eb3f82_9f528051;
+defparam bootram.RAM1.INIT_0F=256'h3f80e451_805185b5_82539f52_518bae3f_c43f82ac_52905185_8bbb3f90_3f82ac51;
+defparam bootram.RAM1.INIT_10=256'h85b03f9f_9f529e51_8025df38_ff135372_518b923f_a83f80e4_529c5185_8b9f3f9f;
+defparam bootram.RAM1.INIT_11=256'h8b2a8106_808c0870_803d0d82_843d0d04_810b800c_81e0840c_8c3f890b_52815185;
+defparam bootram.RAM1.INIT_12=256'h57585957_82055a57_30708025_a7053370_7f028c05_3d0d7a7d_3d0d04f9_800c5182;
+defparam bootram.RAM1.INIT_13=256'h51538054_30709f2a_388a5573_88557383_832e8838_88055575_38728025_75822e93;
+defparam bootram.RAM1.INIT_14=256'h54548054_842b0751_fe057072_05777131_76812cff_802e9738_38725472_8177259e;
+defparam bootram.RAM1.INIT_15=256'h51b0b43f_73528118_51b0bc3f_ff065277_c63f7281_527b51b0_81805474_86397353;
+defparam bootram.RAM1.INIT_16=256'h527551fe_54bd5378_815580ca_9f053356_fb3d0d02_893d0d04_51b0ac3f_815280da;
+defparam bootram.RAM1.INIT_17=256'h81ff0653_bb3f8008_51d63ffe_3f815281_c551b083_0d815280_0d04fe3d_e63f873d;
+defparam bootram.RAM1.INIT_18=256'h81705654_787a5757_04fa3d0d_53843d0d_81e0800c_08709007_3881e080_72802ef3;
+defparam bootram.RAM1.INIT_19=256'h38805581_81ff2e83_71335271_83388054_5270802e_17703352_279e3872_80537276;
+defparam bootram.RAM1.INIT_1A=256'h33557481_0d80e8e4_0d04fc3d_800c883d_38815170_70802e83_74740751_1353df39;
+defparam bootram.RAM1.INIT_1B=256'h74802e95_81ff0655_9e3f8008_80d051b0_e8538252_865480e8_80e8e434_e138810b;
+defparam bootram.RAM1.INIT_1C=256'he8e85180_dfcc5280_38865380_74802e8f_81ff0655_8c3f8008_e8e851ff_38865280;
+defparam bootram.RAM1.INIT_1D=256'h845280e8_802e9538_ff065574_3f800881_d051afe3_538c5280_5480e8f0_c0993f84;
+defparam bootram.RAM1.INIT_1E=256'hf453b852_845480e8_80e8f00c_80dfd408_802e8938_ff065574_3f800881_f051fed1;
+defparam bootram.RAM1.INIT_1F=256'h81ff0655_9c3f8008_e8f451fe_38845280_74802e95_81ff0655_ae3f8008_80d051af;
+defparam bootram.RAM1.INIT_20=256'h0881ff06_aef93f80_5280d051_e8f85388_0c845480_0880e8f4_3880dfd8_74802e89;
+defparam bootram.RAM1.INIT_21=256'hdc0880e8_893880df_5574802e_0881ff06_fde73f80_80e8f851_95388452_5574802e;
+defparam bootram.RAM1.INIT_22=256'h3f80e8f8_0c04fdfa_e8f00b80_fe843f80_0b800c04_3f80e8e8_0d04fe8e_f80c863d;
+defparam bootram.RAM1.INIT_23=256'had993f80_5280d051_5475538c_0d775684_0c04fb3d_e8f40b80_fdf03f80_0b800c04;
+defparam bootram.RAM1.INIT_24=256'h80e8e434_3d0d810b_3d0d04fe_74800c87_80e8f00c_87387508_5574802e_0881ff06;
+defparam bootram.RAM1.INIT_25=256'hfc080607_067180e8_73097375_04803d0d_3f843d0d_e851be8f_cc5280e8_945380df;
+defparam bootram.RAM1.INIT_26=256'h077080e9_e9800806_75067180_0d730973_0d04803d_0c51823d_0c81e08c_7080e8fc;
+defparam bootram.RAM1.INIT_27=256'h800c843d_81c73f72_53538051_3d0d7470_af3f04fe_3d0d0481_980c5182_800c81e0;
+defparam bootram.RAM1.INIT_28=256'h06545472_337081ff_79565674_fb3d0d77_833d0d04_5181b63f_0d8a5280_0d04ff3d;
+defparam bootram.RAM1.INIT_29=256'h3d0d7352_3d0d04ff_0b800c87_3fe53980_52558191_ff065376_81157481_802e9038;
+defparam bootram.RAM1.INIT_2A=256'h0b800c84_80e73f80_8a527251_53ffbd3f_76537052_fe3d0d74_833d0d04_8051cd3f;
+defparam bootram.RAM1.INIT_2B=256'h1234823d_3380e7f4_51028f05_803d0d72_833d0d04_8051dd3f_3d0d7352_3d0d04ff;
+defparam bootram.RAM1.INIT_2C=256'hfe3d0d80_833d0d04_720c5351_e0057022_751080df_82908005_0d73a029_0d04ff3d;
+defparam bootram.RAM1.INIT_2D=256'h38843d0d_827325e5_3f811353_527251ce_e7f81333_51c63f80_13335272_5380e7f4;
+defparam bootram.RAM1.INIT_2E=256'h87388d52_2e098106_33537281_80e7f414_81069538_748a2e09_76785654_04fc3d0d;
+defparam bootram.RAM1.INIT_2F=256'h04fe3d0d_0c863d0d_38748c15_72802ef8_84140853_90800554_73a02982_7351de3f;
+defparam bootram.RAM1.INIT_30=256'h0d04ff3d_800c843d_12085372_2e853890_ff537080_11085252_90800588_74a02982;
+defparam bootram.RAM1.INIT_31=256'h800b81a8_840c5181_882a81a8_a8800c70_81ff0681_e8802270_a8880c80_0d800b81;
+defparam bootram.RAM1.INIT_32=256'h81a89008_2e818638_81517180_33555354_88059705_0d767802_0d04fd3d_880c833d;
+defparam bootram.RAM1.INIT_33=256'ha8900870_a8900c81_81900b81_81a88c0c_72108107_5170f138_81065151_70862a70;
+defparam bootram.RAM1.INIT_34=256'h70802eba_51515151_06708132_872a7081_a8900870_70f13881_06515151_812a7081;
+defparam bootram.RAM1.INIT_35=256'h70810651_0870812a_0c81a890_7081a890_8338a051_5171812e_b13880e8_3871802e;
+defparam bootram.RAM1.INIT_36=256'h0b81a890_883980c0_cc398151_34ff1252_70810556_08517074_3881a88c_515170f1;
+defparam bootram.RAM1.INIT_37=256'h2a708106_90087086_535481a8_97053355_78028805_fd3d0d76_853d0d04_0c70800c;
+defparam bootram.RAM1.INIT_38=256'h81a89008_81a8900c_81905170_802e8438_81d05171_81a88c0c_f1387210_51515170;
+defparam bootram.RAM1.INIT_39=256'h5170802e_32515151_81067081_70872a70_81a89008_5170f138_81065151_70812a70;
+defparam bootram.RAM1.INIT_3A=256'h900c81a8_517081a8_2e833890_d0517181_a88c0c80_38733381_802e80c5_80cf3871;
+defparam bootram.RAM1.INIT_3B=256'h51515170_70813251_2a708106_90087087_f13881a8_51515170_2a708106_90087081;
+defparam bootram.RAM1.INIT_3C=256'h0c853d0d_80517080_81a8900c_3980c00b_3981518a_5354ffb7_8114ff13_802e8e38;
+defparam bootram.RAM1.INIT_3D=256'h8d9f7127_31515186_ac087073_085281b8_3881b8ac_7274259b_75548053_04fd3d0d;
+defparam bootram.RAM1.INIT_3E=256'h0b828084_80800cef_81e20b82_8280880c_3d0dff0b_3d0d04ff_53e23985_f1388113;
+defparam bootram.RAM1.INIT_3F=256'h38833d0d_708025f1_0cff1151_70840554_51a0f172_f3a85287_808c0c80_0cff0b82;
+defparam bootram.RAM2.INIT_00=256'h74760652_f3a85555_53810b80_58515280_8c087106_70098280_82808808_04fb3d0d;
+defparam bootram.RAM2.INIT_01=256'h877325dc_10575553_13841576_0c8f3981_7482808c_0852712d_38725173_71802e8f;
+defparam bootram.RAM2.INIT_02=256'h2b700982_0c518172_a8057571_842980f3_269f3871_73527187_04ff3d0d_38873d0d;
+defparam bootram.RAM2.INIT_03=256'h81e0c40c_22747008_0d029205_0404ff3d_52833d0d_880c5351_72068280_80880870;
+defparam bootram.RAM2.INIT_04=256'h802ef338_06515170_a0087084_cc0c81b8_810b81e0_04803d0d_0c833d0d_5281e0c8;
+defparam bootram.RAM2.INIT_05=256'h54527280_08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f_cc0c823d_820b81e0;
+defparam bootram.RAM2.INIT_06=256'h5271802e_70810651_3971812a_8080529a_0c535381_71902a71_b8a00875_2e933881;
+defparam bootram.RAM2.INIT_07=256'h7080c006_81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f_ec51f8d3_8b3880df;
+defparam bootram.RAM2.INIT_08=256'h0781e0cc_70902b88_028e0522_04ff3d0d_0c823d0d_80800b80_2ef23881_51517080;
+defparam bootram.RAM2.INIT_09=256'h0d755480_0d04fd3d_cc0c833d_840b81e0_802ef338_06515170_a0087090_0c5281b8;
+defparam bootram.RAM2.INIT_0A=256'h853d0d04_7327e638_81135385_52a6ff3f_14703352_f7a53f72_8638ba51_5372802e;
+defparam bootram.RAM2.INIT_0B=256'h3d0d04f6_80ed3f87_80dff051_70335356_81113354_82113355_83113356_fb3d0d77;
+defparam bootram.RAM2.INIT_0C=256'h3875802e_7680258f_5d5b5957_2a515b5f_7030709f_05bb0533_61630290_3d0d7c7e;
+defparam bootram.RAM2.INIT_0D=256'h3f800851_7651aec5_80537752_79557854_77269438_76305777_ad51782d_8a387952;
+defparam bootram.RAM2.INIT_0E=256'h8b053351_803d0d02_8c3d0d04_3351782d_80dffc05_dd3f8008_527651ae_ffbd3f77;
+defparam bootram.RAM2.INIT_0F=256'h06575775_337081ff_5c5a5878_5208a3d8_70708405_3d0d8c3d_3d0d04f7_f68d3f82;
+defparam bootram.RAM2.INIT_10=256'h2e80fb38_597580f0_19703357_80db3881_2e098106_065675a5_387681ff_802e81d1;
+defparam bootram.RAM2.INIT_11=256'h80e42e80_81953975_2e819e38_8a387580_7580e324_e32eb938_a0387580_7580f024;
+defparam bootram.RAM2.INIT_12=256'h80f82eba_80f53975_2e80db38_387580f3_80f5248b_2eac3875_397580f5_c638818b;
+defparam bootram.RAM2.INIT_13=256'h59568055_19710852_da397784_51792d80_56805275_12335259_77841983_3880ec39;
+defparam bootram.RAM2.INIT_14=256'h19710852_92397784_81538a52_55a3d854_52595680_84197108_53903977_a3d85480;
+defparam bootram.RAM2.INIT_15=256'h5675802e_59567633_19710859_9e397784_51fdd03f_53905275_a3d85480_59568055;
+defparam bootram.RAM2.INIT_16=256'h048a0b81_0c8b3d0d_39800b80_1959fea3_2dec3981_58335179_76708105_8e388052;
+defparam bootram.RAM2.INIT_17=256'h04fc3d0d_38823d0d_515170ef_70810651_8c2a8132_b8b40870_803d0d81_e0d00c04;
+defparam bootram.RAM2.INIT_18=256'h0a075272_86387181_5570802e_55555654_07728106_72982b7b_059b0533_797b0288;
+defparam bootram.RAM2.INIT_19=256'h7181e0d4_51ffa93f_79712b51_52a07531_71820a07_802e8638_06515170_822a7081;
+defparam bootram.RAM2.INIT_1A=256'hfc3d0d76_863d0d04_5170800c_81b88008_38ff953f_73802e89_d80c7351_0c7081e0;
+defparam bootram.RAM2.INIT_1B=256'h2a517080_ee397190_15555351_22730581_72101570_74278f38_55805372_787a5455;
+defparam bootram.RAM2.INIT_1C=256'h5280e988_0d865375_0d04fd3d_800c863d_52ec3971_72902a05_83ffff06_2e8d3871;
+defparam bootram.RAM2.INIT_1D=256'h8812ff12_5180720c_e9985289_ff3d0d80_853d0d04_e9900c54_76700880_51b0983f;
+defparam bootram.RAM2.INIT_1E=256'h5472742e_52527022_0b80e994_05225380_3d0d0296_3d0d04fd_25f33883_52527080;
+defparam bootram.RAM2.INIT_1F=256'h83ffff06_0d787a71_0d04fa3d_800c853d_38805170_897225ee_88125252_8e388112;
+defparam bootram.RAM2.INIT_20=256'h55555573_0b80e994_0880e998_0cad3980_80088405_2e893876_3f800880_535856c7;
+defparam bootram.RAM2.INIT_21=256'h84140c88_75732376_389dad3f_897525eb_88145455_8f388115_5271802e_08881555;
+defparam bootram.RAM2.INIT_22=256'h913ddc05_3d880552_3f735392_5254aee7_923dd605_54933d53_3d0d8670_3d0d04f1;
+defparam bootram.RAM2.INIT_23=256'h8c3d2381_0523800b_028405a6_8b3d2380_818a800b_05a20523_90800284_51aed83f;
+defparam bootram.RAM2.INIT_24=256'h8a52913d_665e8053_0523685d_028405ae_8d3d2380_80c0910b_05aa0523_80800284;
+defparam bootram.RAM2.INIT_25=256'h23800b91_8405ba05_963d2202_22903d23_0523983d_028405ae_b73f8008_e40551fd;
+defparam bootram.RAM2.INIT_26=256'h913d0d04_519fb03f_81e68405_6980c029_3dd40552_23ac5391_8405be05_3d238002;
+defparam bootram.RAM2.INIT_27=256'h529a3df8_5380e988_adc53f86_3df20551_9b3d529a_3d238653_5b800b97_e83d0d80;
+defparam bootram.RAM2.INIT_28=256'h9b3dc411_585a800b_80088008_23f7e23f_0580e205_05220284_3f0280f2_0551adb7;
+defparam bootram.RAM2.INIT_29=256'h8305fc06_5fa33d08_5ea13d08_5c905d6e_08465984_0845a33d_6e44a13d_43f00543;
+defparam bootram.RAM2.INIT_2A=256'h0c750854_84387376_55737527_3151565a_31908071_701a787c_84587508_408c3d56;
+defparam bootram.RAM2.INIT_2B=256'he63f7508_e09851ef_2e883880_06547380_94160883_54738c38_38738306_73802e9a;
+defparam bootram.RAM2.INIT_2C=256'hbf268438_ffac3878_57778025_17ff1959_84055708_823f7570_5276519e_53941608;
+defparam bootram.RAM2.INIT_2D=256'h7f1f9405_0b943d23_40818a80_0d6b6e40_0d04ea3d_e83f9a3d_822a51f6_80c05978;
+defparam bootram.RAM2.INIT_2E=256'h075a7996_6980c080_80ce0523_80028405_3d238180_23800b95_0580ca05_5a790284;
+defparam bootram.RAM2.INIT_2F=256'h3f800809_525cfae0_52933d70_4780538a_90084668_052380e9_840580d2_3d238002;
+defparam bootram.RAM2.INIT_30=256'h79923880_81ff065a_873f8008_535c5e8c_53983d70_23913d70_0580d205_5a790284;
+defparam bootram.RAM2.INIT_31=256'h7b549080_575d9455_5960586b_027f5a6d_d53fa939_f6b63fed_c23f7a51_e0c451f7;
+defparam bootram.RAM2.INIT_32=256'hf73d0d7f_983d0d04_38fd893f_867c26ef_34811c5c_5b79337b_1d7c1f5b_53805c7b;
+defparam bootram.RAM2.INIT_33=256'ha6052377_80028405_768b3d23_23881857_8405a205_8d3d2202_228a3d23_5802ae05;
+defparam bootram.RAM2.INIT_34=256'h23908002_810b8e3d_04ee3d0d_3f8b3d0d_7d51fe9e_05539152_548b3df8_567e5588;
+defparam bootram.RAM2.INIT_35=256'h53800852_eb8c3f86_05b60523_34810284_8405b505_3d348402_23860b8f_8405b205;
+defparam bootram.RAM2.INIT_36=256'h943df605_86538052_51a9e43f_943df205_53800852_eb863f84_51a9f43f_943dec05;
+defparam bootram.RAM2.INIT_37=256'h53805b7a_05549086_55943de4_5780569c_59805880_5a025c80_64700844_51aaf13f;
+defparam bootram.RAM2.INIT_38=256'h0b8e3d23_ee3d0d81_943d0d04_38fbcd3f_867b26ef_34811b5b_901b337a_1c5a80e0;
+defparam bootram.RAM2.INIT_39=256'h893f8653_b60523ea_81028405_05b50534_34840284_860b8f3d_05b20523_90800284;
+defparam bootram.RAM2.INIT_3A=256'h53805294_a8e13f86_3df20551_80085294_833f8453_a8f13fea_3dec0551_80085294;
+defparam bootram.RAM2.INIT_3B=256'he4055490_9c55943d_80578056_80598058_0843025c_e73f8008_a9ee3fe9_3df60551;
+defparam bootram.RAM2.INIT_3C=256'h04d83d0d_3f943d0d_ef38fac8_5b867b26_7a34811b_e0901b33_7a1c5a80_8653805b;
+defparam bootram.RAM2.INIT_3D=256'h5c799b26_29f2055b_ad3d0884_cc38901d_09810682_7e90862e_1122405d_ab3d088e;
+defparam bootram.RAM2.INIT_3E=256'h225a7990_9138821c_09810687_5a79812e_9d397b22_f49d3f87_80e0f451_8d387952;
+defparam bootram.RAM2.INIT_3F=256'h2e098106_225a7982_f538861c_09810686_798c842e_841c225a_06878338_802e0981;
+defparam bootram.RAM3.INIT_00=256'h79527a51_51a7a03f_981d5279_3d5a8653_a7ad3fa8_1d527a51_5b84539e_a238943d;
+defparam bootram.RAM3.INIT_01=256'h5b888c3f_a81d7052_4088943f_9e1d7052_0686bb38_812e0981_1c225a79_87953f86;
+defparam bootram.RAM3.INIT_02=256'h5a865380_9138a83d_5e800886_f63f8008_a40551a5_52aa3dff_5380e990_80084384;
+defparam bootram.RAM3.INIT_03=256'h34851c33_1c33a33d_82052384_02840581_23821c22_7b22a23d_51a6d43f_e9885279;
+defparam bootram.RAM3.INIT_04=256'h70547b53_a6a13f84_3de40551_537952aa_86052386_02840581_85053482_02840581;
+defparam bootram.RAM3.INIT_05=256'haa3df405_79537f52_51a6843f_981d527a_055b8653_3f028192_525aa693_ab3dea05;
+defparam bootram.RAM3.INIT_06=256'haa3ddc05_575d9c55_597e587e_027e5a7e_51a5ec3f_537a527f_9f3d4086_51a5f83f;
+defparam bootram.RAM3.INIT_07=256'h397e9080_e73f84ee_26ef38f7_1c5c867c_337b3481_1d5b5b79_5c7b1d60_547e537d;
+defparam bootram.RAM3.INIT_08=256'h2a708f06_d1387988_09810684_5b60842e_8c2a435b_1d702270_84e43890_2e098106;
+defparam bootram.RAM3.INIT_09=256'he0905282_5e865380_84b4387e_ff065f7e_1b2280ff_84c03886_2e098106_515a7985;
+defparam bootram.RAM3.INIT_0A=256'h08833881_a3ed3f80_70535b5c_80e99054_901c6255_38815e7e_3f800883_1d51a483;
+defparam bootram.RAM3.INIT_0B=256'h5d407f81_22ec1140_1b33821c_84c53f89_529c1d51_8138881d_7b802e84_5c7d8738;
+defparam bootram.RAM3.INIT_0C=256'h7a2e8f38_5d42407d_8411225d_7a08a41f_388c1b08_810683de_7f912e09_2e81bb38;
+defparam bootram.RAM3.INIT_0D=256'h08428008_f4913f80_22535d5d_e41d821d_bd39ac1d_f0bd3f83_80e19451_79537d52;
+defparam bootram.RAM3.INIT_0E=256'h3d408853_a3e13f9d_7d527951_5f5a8853_9b3d9a3d_3d237f4a_387a229a_802e83a6;
+defparam bootram.RAM3.INIT_0F=256'h88537952_51a3c03f_b4055279_53aa3dff_23604888_1b22983d_a3d53f82_79527f51;
+defparam bootram.RAM3.INIT_10=256'h7c26ef38_811c5c88_79337b34_7c1f5b5b_5e5c7b1d_557e843d_3f7b567c_7d51a3b7;
+defparam bootram.RAM3.INIT_11=256'had398c1b_5a792d82_61840508_7b26ef38_811b5b88_84051c34_5a793302_805b7f1b;
+defparam bootram.RAM3.INIT_12=256'h2e098106_335a7983_9539811a_81bb3882_387d882e_7d832e8a_33405b42_08a41e70;
+defparam bootram.RAM3.INIT_13=256'h3f800841_2251f2cf_81f4387c_2e098106_5e5c7991_8912335c_1d80c01e_81a238ac;
+defparam bootram.RAM3.INIT_14=256'h7d51a29b_88537a52_9c3d5c5e_794c993d_229c3d23_1c085a7c_80fe388c_8008802e;
+defparam bootram.RAM3.INIT_15=256'h3dcc0552_4e8853aa_9e3d2379_5a821d22_3f901c08_7f51a28f_88537d52_3f973d40;
+defparam bootram.RAM3.INIT_16=256'h5b79337b_1d7c1f5b_3d5e5c7b_7e557e84_ee3f7e56_527d51a1_3f88537a_7a51a1f7;
+defparam bootram.RAM3.INIT_17=256'h38608405_887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c;
+defparam bootram.RAM3.INIT_18=256'hd105347e_02840580_963d347e_1d5d5d7e_39ac1de4_e63f80de_80e951e3_085a792d;
+defparam bootram.RAM3.INIT_19=256'h3d70525b_53605295_d605237e_02840580_23861a22_1a22973d_d2052384_02840580;
+defparam bootram.RAM3.INIT_1A=256'h567c557d_d205237b_02840580_08095a79_f08e3f80_2a527c51_08537b81_f09a3f80;
+defparam bootram.RAM3.INIT_1B=256'h3d0d800b_e80c04fc_800b80e9_80e9e40c_0d04800b_c53faa3d_526151f4_547a537f;
+defparam bootram.RAM3.INIT_1C=256'h2e098106_53517075_71088c13_ec545651_700880e9_27a43876_55537274_80e9e408;
+defparam bootram.RAM3.INIT_1D=256'h71535755_3d0d7779_3d0d04fb_70800c86_e738ff51_53737326_8b398113_85387251;
+defparam bootram.RAM3.INIT_1E=256'he9e80881_0c8e3980_1480e9e4_26893881_08547387_3880e9e4_088025ba_ffb93f80;
+defparam bootram.RAM3.INIT_1F=256'he9f01451_53755280_0c515486_80e9ec12_822b7608_73101470_e9e80c54_11870680;
+defparam bootram.RAM3.INIT_20=256'hfd3d0d75_873d0d04_519fa43f_80e9f005_52738429_54865375_10800805_94398008;
+defparam bootram.RAM3.INIT_21=256'h5276519e_80e9f005_53738429_08055486_80081080_08249938_80547380_51fed83f;
+defparam bootram.RAM3.INIT_22=256'h14337088_902b0782_71982b71_33811233_3d0d7570_3d0d04fd_73800c85_fa3f8154;
+defparam bootram.RAM3.INIT_23=256'h22565957_7f80eacc_f93d0d7d_853d0d04_54565452_800c5253_16337107_2b720783;
+defparam bootram.RAM3.INIT_24=256'h902980ea_90291470_80d33873_54738326_72315256_8b3d2270_83ffff06_76a83873;
+defparam bootram.RAM3.INIT_25=256'h38749029_748326ad_31575754_3d227072_ffff068d_c0397383_76742380_d0055154;
+defparam bootram.RAM3.INIT_26=256'h33535474_38751770_75782791_ea3f8056_d005519d_902980ea_8a3d5273_15548853;
+defparam bootram.RAM3.INIT_27=256'hd0545480_800b80ea_80eacc23_029a0522_04fc3d0d_39893d0d_811656ec_51e1de3f;
+defparam bootram.RAM3.INIT_28=256'h14829014_eddc3f81_22740551_5280eacc_140cb8f4_800b828c_8288140c_7323800b;
+defparam bootram.RAM3.INIT_29=256'h06515675_81327081_5c847c2c_80ead05a_3d0d800b_3d0d04f4_27d93886_54548374;
+defparam bootram.RAM3.INIT_2A=256'h08ff2e80_e1a33f80_055b7b51_38781a88_ff2680d6_5b5d7981_82881a08_81be3875;
+defparam bootram.RAM3.INIT_2B=256'h58587680_53515951_71802507_30728025_728d3270_8a327030_81ff0670_c5388008;
+defparam bootram.RAM3.INIT_2C=256'h811a5a81_828c1a0c_1a0c800b_81058288_82881908_81055d34_5d777b70_2e833881;
+defparam bootram.RAM3.INIT_2D=256'h568b7627_828c1b0c_19088111_9138828c_80d2387c_1908802e_b1388288_ff7a27ff;
+defparam bootram.RAM3.INIT_2E=256'h57577533_771a781a_833d5b58_1954800b_19085588_ab388288_5675802e_bf387822;
+defparam bootram.RAM3.INIT_2F=256'h828c1a0c_1a0c800b_800b8288_51f0e93f_cc227c05_ef3880ea_58887826_77348118;
+defparam bootram.RAM3.INIT_30=256'h685194ba_5780c052_883d7054_04ea3d0d_388e3d0d_7c27fea9_1a5a5c83_811c8290;
+defparam bootram.RAM3.INIT_31=256'h94387416_2e098106_387381aa_81ff2e9d_33515473_55741770_059d0557_3f800284;
+defparam bootram.RAM3.INIT_32=256'h800c983d_38805473_be7527d1_39811555_3881548b_09810685_7381992e_70335154;
+defparam bootram.RAM3.INIT_33=256'hca3f8008_52735199_5380e1b8_3f805584_795193ea_54548452_0d863d70_0d04f93d;
+defparam bootram.RAM3.INIT_34=256'h3f8ac23f_3d0d8dd7_940c04fc_810b81e0_893d0d04_5574800c_06833881_752e0981;
+defparam bootram.RAM3.INIT_35=256'he1bc5181_73883880_06515154_8d2a7081_b8b40870_89c13f81_06558051_800881ff;
+defparam bootram.RAM3.INIT_36=256'h51dd843f_3880e2a0_08802e9a_febf3f80_b0800a51_51dd983f_3880e1f4_833974b5;
+defparam bootram.RAM3.INIT_37=256'h51fee33f_3998800a_d85180cc_b53f80e2_800a5184_e1b73fb0_3f82ac51_81518987;
+defparam bootram.RAM3.INIT_38=256'h80e3d051_5192bf3f_5298800a_5380ffff_3f838080_a451dcd7_bb3880e3_8008802e;
+defparam bootram.RAM3.INIT_39=256'he93f8839_3f805183_ac51e0e9_dcb13f82_80e3f451_3ffee53f_ac51e0f9_dcc13f82;
+defparam bootram.RAM3.INIT_3A=256'he5893fa0_e4fc5254_75705380_04fd3d0d_80f3900c_3d0d0471_dc9d3f86_80e4b051;
+defparam bootram.RAM3.INIT_3B=256'h528051da_fe3d0da0_853d0d04_7351722d_802e8538_90085372_cc3f80f3_52a051da;
+defparam bootram.RAM3.INIT_3C=256'hff0b8008_51898d3f_fc3d0d9a_843d0d04_8051722d_802e8538_90085372_b03f80f3;
+defparam bootram.RAM3.INIT_3D=256'h7182802e_5580e454_86800653_820b8008_2e80ec38_81557180_06515354_862a7081;
+defparam bootram.RAM3.INIT_3E=256'h845188c8_8338ff54_7184802e_3987e854_2e8e388a_8a547180_80248a38_9b387182;
+defparam bootram.RAM3.INIT_3F=256'h7080f39c_e5f41133_06720780_8a2c7083_8c068008_3f71882a_855188c0_3f800852;
+defparam bootram.RAM4.INIT_00=256'h80f39408_dac93f74_11085252_0680e888_71822b8c_52dab03f_55535154_0c80e5b4;
+defparam bootram.RAM4.INIT_01=256'h2e098106_9e397482_38fec13f_098106a3_3874812e_74822ea6_80f3940c_2e983874;
+defparam bootram.RAM4.INIT_02=256'h863d0d04_5187cd3f_fdfb3f99_a73f7351_f3980cfe_8e387380_f398082e_96387380;
+defparam bootram.RAM4.INIT_03=256'h3f8d5298_995187ac_80f3980c_940cff0b_800b80f3_5187a23f_e13f8008_fd3d0dd7;
+defparam bootram.RAM4.INIT_04=256'h908007f4_8f3f8008_3f845187_8451dfb1_3fbf9452_9c5187cd_81ae8052_5187d63f;
+defparam bootram.RAM4.INIT_05=256'hcc51e2a7_735280e5_38800853_80082e8d_86fa3f73_b03f8451_54845187_9f067053;
+defparam bootram.RAM4.INIT_06=256'h70852a82_02970533_04fd3d0d_3f853d0d_80518789_84800752_e33f8008_3f805186;
+defparam bootram.RAM4.INIT_07=256'h71730707_832ba006_10900674_73070773_2a880671_84067281_0771832a_0671872a;
+defparam bootram.RAM4.INIT_08=256'h51555255_0c515253_0682c080_077081ff_0778872b_c0067072_76852b80_7081ff06;
+defparam bootram.RAM4.INIT_09=256'h983f81aa_81ff51ff_51ff9e3f_075381ff_0681d00a_0d74d00a_0d04fe3d_5552853d;
+defparam bootram.RAM4.INIT_0A=256'h5252fef5_7081ff06_3f72882a_e151ff81_ff873f80_8c3fb251_819951ff_51ff923f;
+defparam bootram.RAM4.INIT_0B=256'h902a7081_fedb3f72_72982a51_51fee23f_e83f8181_3fb251fe_0651feed_3f7281ff;
+defparam bootram.RAM4.INIT_0C=256'ha051feb5_51feba3f_febf3f8e_c43f8051_81a151fe_51feca3f_fecf3fb0_ff065253;
+defparam bootram.RAM4.INIT_0D=256'h05538052_54873dfc_fb3d0d82_843d0d04_51fea63f_feab3f80_b03fa051_3f8051fe;
+defparam bootram.RAM4.INIT_0E=256'h12085859_d73d0884_d53d0880_b23d0d80_3d0d04ff_22800c87_ce3f863d_80d05183;
+defparam bootram.RAM4.INIT_0F=256'h2681b238_16567596_bc39ff9f_dff53f81_80e68451_53829452_26903877_57778293;
+defparam bootram.RAM4.INIT_10=256'h0b81e2cc_e18c0c81_5e810b81_3f800808_c15cd4c0_75080480_e6d00556_75842980;
+defparam bootram.RAM4.INIT_11=256'hfef63f80_5c80f839_085f80c6_8c9d3f80_3f80085e_8a398c99_e4d00c81_0c800b81;
+defparam bootram.RAM4.INIT_12=256'hc55c80d3_89f53f80_80f3c851_8c170852_90170853_5c80e839_065e80d6_0883ffff;
+defparam bootram.RAM4.INIT_13=256'h39941753_80c25cb7_c45cbc39_2e863880_06567580_800881ff_518aba3f_3980f3c8;
+defparam bootram.RAM4.INIT_14=256'h1708518b_1708528c_80055390_80d03dfe_d75ca439_88dc3f80_8c170851_90170852;
+defparam bootram.RAM4.INIT_15=256'h54800b83_3dfdec05_945580d0_39a05c82_fcf83f83_d35c8051_5c8d3980_b93f80d2;
+defparam bootram.RAM4.INIT_16=256'he6fe3f80_83808251_7826ec38_81185888_75337734_79055757_1980d23d_3d5a5877;
+defparam bootram.RAM4.INIT_17=256'h05ab0533_05330284_3d0d02a7_83973ff9_ce3fff51_e7ac51d4_803d0d80_d03d0d04;
+defparam bootram.RAM4.INIT_18=256'h7f7f5a57_3d0d7a7c_3d0d04f8_dfeb3f89_81528051_98547553_57578255_71882b07;
+defparam bootram.RAM4.INIT_19=256'h8405a105_05583302_34767081_54738a3d_75811757_7425b738_16565480_575874ff;
+defparam bootram.RAM4.INIT_1A=256'h802e8538_d8c73f73_06548a51_800881ff_51d7993f_7781ff06_3dfc0552_3482538a;
+defparam bootram.RAM4.INIT_1B=256'h883d3481_38dc5675_de567483_05335580_3d0d02a3_3d0d04fa_73800c8a_c1398154;
+defparam bootram.RAM4.INIT_1C=256'h893d3481_02ab0533_3d0d7c57_3d0d04f9_ff893f88_5280d051_055381f7_54883dfc;
+defparam bootram.RAM4.INIT_1D=256'h38807725_73802e9e_06705654_800881ff_56d6b93f_05337052_055202a7_53893dfc;
+defparam bootram.RAM4.INIT_1E=256'h0c893d0d_81557480_802e8338_70565473_0881ff06_d4fc3f80_7b527551_97387653;
+defparam bootram.RAM4.INIT_1F=256'h80de2e09_33565674_800b883d_51ffa03f_f75280d0_fc055381_8154883d_04fa3d0d;
+defparam bootram.RAM4.INIT_20=256'h81c0ac0c_800ca60b_eb0b81c0_c0940c80_04990b81_0c883d0d_81567580_81068338;
+defparam bootram.RAM4.INIT_21=256'hc0a00c81_51820b81_81c0980c_06708107_882bbe80_803d0d72_c0b00c04_89b00b81;
+defparam bootram.RAM4.INIT_22=256'h72882bbe_04803d0d_0c823d0d_c0a80880_70f13881_06515151_812a7081_c0a40870;
+defparam bootram.RAM4.INIT_23=256'h70810651_0870812a_0c81c0a4_0b81c0a0_c09c0c84_0c517381_0781c098_80067081;
+defparam bootram.RAM4.INIT_24=256'h83065271_71913875_55555757_7c728306_3d0d787a_04ff39fa_38823d0d_515170f1;
+defparam bootram.RAM4.INIT_25=256'h822b7711_27943873_55557375_72822a72_5188ca3f_2e863881_06527180_8a387283;
+defparam bootram.RAM4.INIT_26=256'h80e7b811_2a708f06_0d747084_0d04fe3d_e939883d_52811454_720c5254_77127008;
+defparam bootram.RAM4.INIT_27=256'h82e09008_04803d0d_3f843d0d_5253cffb_e7b81133_728f0680_53d0883f_33545153;
+defparam bootram.RAM4.INIT_28=256'h8c800607_80ff067a_93053378_fe3d0d02_823d0d04_5170f138_81065151_70882a70;
+defparam bootram.RAM4.INIT_29=256'h82e0900c_e0800c71_f1387682_51515170_2a708106_90087088_535382e0_80c08007;
+defparam bootram.RAM4.INIT_2A=256'h882a7081_e0900870_2e963882_72517280_82e0900c_71828007_82e0980c_7581ff06;
+defparam bootram.RAM4.INIT_2B=256'h88805588_82e0940c_3d0d810b_3d0d04fc_70800c84_e0800851_70f13882_06515151;
+defparam bootram.RAM4.INIT_2C=256'h51fef13f_53815281_90548a80_0d888055_0d04fc3d_873f863d_528051ff_54805380;
+defparam bootram.RAM4.INIT_2D=256'h863d0d04_51fed53f_53815280_55885486_3d0d8880_3d0d04fc_06800c86_800881ff;
+defparam bootram.RAM4.INIT_2E=256'h70802ef4_81ff0651_eb3f8008_04803d0d_0c823d0d_32810680_3f800881_803d0dca;
+defparam bootram.RAM4.INIT_2F=256'h5475fe9b_888055a0_3fffb43f_269b38dd_3f758008_775684e3_04fb3d0d_38823d0d;
+defparam bootram.RAM4.INIT_30=256'h08ff1156_0880cb3d_0d80c93d_04ffba3d_3f873d0d_8051fe84_07538152_0a069b0a;
+defparam bootram.RAM4.INIT_31=256'hff52883d_82805381_2681a738_3f738008_1754849f_81b43875_7381ff26_57578055;
+defparam bootram.RAM4.INIT_32=256'h82e0980c_fd9f3f74_3ffed43f_ea3ffefd_5273518a_80cb3d08_8f3f7553_7052548c;
+defparam bootram.RAM4.INIT_33=256'h0b82e090_980c88a0_810b82e0_82e0800c_80c00a07_fec00a06_e0900c76_88800b82;
+defparam bootram.RAM4.INIT_34=256'h84157008_8c0c54fe_700882e0_56fe8015_c83d558f_fcef3f80_82e0900c_0c8aa00b;
+defparam bootram.RAM4.INIT_35=256'h82e0900c_5488800b_82e0800c_8c157008_840c54fe_700882e0_54fe8815_82e0880c;
+defparam bootram.RAM4.INIT_36=256'h81557480_82e0980c_bc38800b_758025ff_90165656_b03fff16_e0900cfc_8a800b82;
+defparam bootram.RAM4.INIT_37=256'hcb388157_80082680_3f805773_565682db_7212575a_0d797b7d_0d04f93d_0c80c83d;
+defparam bootram.RAM4.INIT_38=256'h76547753_75278338_75555776_82807431_802ea238_ff065473_c3387581_74802e80;
+defparam bootram.RAM4.INIT_39=256'he1388280_82807527_8e387454_5674802e_76315759_16741976_fdeb3f73_73527551;
+defparam bootram.RAM4.INIT_3A=256'h38731354_73802e8d_7a565455_3d0d7678_3d0d04fc_76800c89_8c3f8157_54dc39fd;
+defparam bootram.RAM4.INIT_3B=256'h08307074_81cb3f80_750ca639_84160c80_160c800b_38800b88_08742790_81ed3f80;
+defparam bootram.RAM4.INIT_3C=256'h3f863d0d_7151fcc9_7188160c_0684160c_72760c74_3f800830_515281bd_06ff1656;
+defparam bootram.RAM4.INIT_3D=256'h15082e94_88140884_9f388153_5271802e_ff067054_3f800881_7554fc98_04fd3d0d;
+defparam bootram.RAM4.INIT_3E=256'h3d0d8880_3d0d04fc_72800c85_943f8053_160c51fc_08057088_88140880_3881823f;
+defparam bootram.RAM4.INIT_3F=256'h0d80f3a0_0d04ff3d_800c863d_fe800a06_a33f8008_528151fa_f90a5381_55a05481;
+defparam bootram.RAM5.INIT_00=256'h387180f3_09810693_5170a02e_ff065451_06800881_2a7081ff_3f800888_08a038d7;
+defparam bootram.RAM5.INIT_01=256'h0880e882_04c03f80_0c833d0d_b33f7180_278438f5_52528271_a008ea11_a00c80f3;
+defparam bootram.RAM5.INIT_02=256'h0d7d56f9_0c04f63d_80082b80_a93f810b_800c04ff_0b80082b_04f33f81_0533800c;
+defparam bootram.RAM5.INIT_03=256'h810b82e0_82e0800c_0c7c882b_0b82e084_e0900c8b_88800b82_82e0980c_983f800b;
+defparam bootram.RAM5.INIT_04=256'h3888800b_762780d3_55805473_f8e73f7e_82e0900c_0c8aa80b_0b82e090_980c88a8;
+defparam bootram.RAM5.INIT_05=256'h5a82e080_82e08408_e0880859_8c085882_cc3f82e0_e0900cf8_8a800b82_82e0900c;
+defparam bootram.RAM5.INIT_06=256'h70337570_38711751_71732791_70538052_73278338_57905370_76753152_085b883d;
+defparam bootram.RAM5.INIT_07=256'h7251f789_04803d0d_0c8c3d0d_0b82e098_ffa93980_39721454_811252ec_81055734;
+defparam bootram.RAM5.INIT_08=256'h70800c54_de3f8008_05085182_528c0888_088c0508_0d80538c_8c0cfd3d_3f8c0802;
+defparam bootram.RAM5.INIT_09=256'h82b93f80_88050851_08528c08_8c088c05_3d0d8153_028c0cfd_0c048c08_853d0d8c;
+defparam bootram.RAM5.INIT_0A=256'h88050880_050c8c08_0b8c08fc_f93d0d80_08028c0c_8c0c048c_54853d0d_0870800c;
+defparam bootram.RAM5.INIT_0B=256'h810b8c08_05088838_0c8c08fc_8c08f405_050c800b_308c0888_08880508_25ab388c;
+defparam bootram.RAM5.INIT_0C=256'h8c088c05_8c050830_ab388c08_05088025_0c8c088c_8c08fc05_08f40508_f4050c8c;
+defparam bootram.RAM5.INIT_0D=256'h08fc050c_f005088c_050c8c08_0b8c08f0_08883881_8c08fc05_08f0050c_0c800b8c;
+defparam bootram.RAM5.INIT_0E=256'hfc050880_0c548c08_8c08f805_3f800870_085181a7_8c088805_8c050852_80538c08;
+defparam bootram.RAM5.INIT_0F=256'h048c0802_3d0d8c0c_800c5489_f8050870_050c8c08_308c08f8_08f80508_2e8c388c;
+defparam bootram.RAM5.INIT_10=256'h0888050c_0508308c_388c0888_08802593_8c088805_08fc050c_0d800b8c_8c0cfb3d;
+defparam bootram.RAM5.INIT_11=256'h538c088c_8c050c81_08308c08_8c088c05_80258c38_088c0508_fc050c8c_810b8c08;
+defparam bootram.RAM5.INIT_12=256'h388c08f8_08802e8c_8c08fc05_f8050c54_08708c08_51ad3f80_08880508_0508528c;
+defparam bootram.RAM5.INIT_13=256'hfd3d0d81_08028c0c_8c0c048c_54873d0d_0870800c_8c08f805_08f8050c_0508308c;
+defparam bootram.RAM5.INIT_14=256'hfc050880_ac388c08_88050827_05088c08_0c8c088c_8c08f805_050c800b_0b8c08fc;
+defparam bootram.RAM5.INIT_15=256'h08108c08_8c08fc05_088c050c_0508108c_388c088c_05082499_0b8c088c_2ea33880;
+defparam bootram.RAM5.INIT_16=256'h8c088805_0826a138_8c088805_088c0508_80c9388c_0508802e_398c08fc_fc050cc9;
+defparam bootram.RAM5.INIT_17=256'h8c08fc05_08f8050c_0508078c_088c08fc_8c08f805_0888050c_0508318c_088c088c;
+defparam bootram.RAM5.INIT_18=256'h802e8f38_08900508_ffaf398c_088c050c_08812a8c_8c088c05_08fc050c_08812a8c;
+defparam bootram.RAM5.INIT_19=256'hf4050880_0c518c08_8c08f405_f8050870_8d398c08_f4050c51_08708c08_8c088805;
+defparam bootram.RAM5.INIT_1A=256'h802eb038_83065170_38747407_8372278c_79565652_3d0d7877_8c0c04fc_0c853d0d;
+defparam bootram.RAM5.INIT_1B=256'h54555571_8115ff14_bd388115_2e098106_52537271_74337433_ff2ea038_ff125271;
+defparam bootram.RAM5.INIT_1C=256'h38841184_0981068f_0873082e_74545170_3d0d0474_0b800c86_06e23880_ff2e0981;
+defparam bootram.RAM5.INIT_1D=256'h3d0d7670_3d0d04fc_31800c86_af397271_735555ff_26e93870_54517183_14fc1454;
+defparam bootram.RAM5.INIT_1E=256'h98387270_5271ff2e_a738ff12_5170802e_75078306_278c3872_55558f72_797b5555;
+defparam bootram.RAM5.INIT_1F=256'h74517270_863d0d04_3874800c_098106ea_5271ff2e_5634ff12_74708105_81055433;
+defparam bootram.RAM5.INIT_20=256'h71708405_84055408_530c7270_71708405_84055408_530c7270_71708405_84055408;
+defparam bootram.RAM5.INIT_21=256'h70840554_27953872_c9388372_52718f26_530cf012_71708405_84055408_530c7270;
+defparam bootram.RAM5.INIT_22=256'h059f0533_7971028c_fc3d0d76_54ff8339_26ed3870_12527183_05530cfc_08717084;
+defparam bootram.RAM5.INIT_23=256'h70810555_93387373_5271ff2e_a238ff12_5170802e_38748306_8372278a_57555355;
+defparam bootram.RAM5.INIT_24=256'h2b075154_07707190_74882b75_3d0d0474_74800c86_8106ef38_71ff2e09_34ff1252;
+defparam bootram.RAM5.INIT_25=256'h71708405_05530c72_72717084_8405530c_0c727170_70840553_a5387271_518f7227;
+defparam bootram.RAM5.INIT_26=256'hf2387053_52718326_530cfc12_71708405_27903872_dd388372_52718f26_530cf012;
+defparam bootram.RAM5.INIT_27=256'h2e80d438_06517080_71740783_2e80d938_55527280_7c705455_3d0d787a_ff9039fa;
+defparam bootram.RAM5.INIT_28=256'h7081ff06_2e818738_a9387280_2e098106_56517471_71337433_ff2eb138_ff135372;
+defparam bootram.RAM5.INIT_29=256'h56517081_71337433_8106d138_72ff2e09_15555552_128115ff_80fc3881_5170802e;
+defparam bootram.RAM5.INIT_2A=256'h71087408_73278838_74575583_3d0d0471_70800c88_31515252_ff067171_ff067581;
+defparam bootram.RAM5.INIT_2B=256'h70f88482_fdff1206_7009f7fb_b1387408_5372802e_9739fc13_765552ff_2e883874;
+defparam bootram.RAM5.INIT_2C=256'h765552fe_2ed03874_74087608_7327d038_17575583_38841584_5151709a_81800651;
+defparam bootram.RAM5.INIT_2D=256'hf3a40cff_9e387380_5472812e_e7e80854_0d800b80_0d04fd3d_800c883d_df39800b;
+defparam bootram.RAM5.INIT_2E=256'hffad813f_80f3a40c_f6a33f72_3f800851_51ffb5b8_e89c5281_acba3f80_ad9e3fff;
+defparam bootram.RAM5.INIT_2F=256'ha40bfc05_3d0d80e8_00ff39ff_51f6863f_9b3f8008_8151ffb5_80e89c52_ffac9d3f;
+defparam bootram.RAM5.INIT_30=256'h0404ffad_38833d0d_098106f1_5270ff2e_12700852_38702dfc_70ff2e91_70085252;
+defparam bootram.RAM5.INIT_31=256'h636b6574_6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_ac3f0400;
+defparam bootram.RAM5.INIT_32=256'h6c697479_74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e;
+defparam bootram.RAM5.INIT_33=256'h6f722069_21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d;
+defparam bootram.RAM5.INIT_34=256'h70656374_3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f;
+defparam bootram.RAM5.INIT_35=256'h74202564_7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070;
+defparam bootram.RAM5.INIT_36=256'h203d2025_70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000;
+defparam bootram.RAM5.INIT_37=256'h720a0000_6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000;
+defparam bootram.RAM5.INIT_38=256'h640a0000_723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741;
+defparam bootram.RAM5.INIT_39=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d;
+defparam bootram.RAM5.INIT_3A=256'h7061636b_65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000;
+defparam bootram.RAM5.INIT_3B=256'h00000826_00000826_00000826_00000826_00000826_00000731_00000000_65743a20;
+defparam bootram.RAM5.INIT_3C=256'h00000826_00000826_000007fc_00000826_00000826_00000776_0000078d_00000826;
+defparam bootram.RAM5.INIT_3D=256'h000007cf_000007ca_000007c5_0000073e_000007aa_00000826_00000826_00000826;
+defparam bootram.RAM5.INIT_3E=256'hffffff00_c0a80a01_c0a80a02_3fff0000_0050c285_000007ea_000007dd_000007d6;
+defparam bootram.RAM5.INIT_3F=256'h30313233_2e256400_642e2564_25642e25_45000000_01b200d9_05160364_14580a2c;
+defparam bootram.RAM6.INIT_00=256'h5f706b74_73656e64_ffff0000_ffffffff_00000000_43444546_38394142_34353637;
+defparam bootram.RAM6.INIT_01=256'h72206275_6e642f6f_656e2061_6f66206c_656e7420_69676e6d_6420616c_3a206261;
+defparam bootram.RAM6.INIT_02=256'h74206361_6f206869_65642074_6661696c_6f6e3a20_636f6d6d_6e65745f_66000000;
+defparam bootram.RAM6.INIT_03=256'h6172703a_646c655f_0a68616e_00000000_666f7220_696e6720_6c6f6f6b_63686520;
+defparam bootram.RAM6.INIT_04=256'h6e736973_696e636f_55445020_0a000000_3d202564_697a6520_72642073_20776569;
+defparam bootram.RAM6.INIT_05=256'h53746172_0b0b0b0b_00000000_2025640a_3a202564_67746873_206c656e_74656e74;
+defparam bootram.RAM6.INIT_06=256'h6164696e_2e204c6f_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67;
+defparam bootram.RAM6.INIT_07=256'h20666f72_6b696e67_43686563_00000000_6172652e_69726d77_66652066_67207361;
+defparam bootram.RAM6.INIT_08=256'h2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070_2076616c;
+defparam bootram.RAM6.INIT_09=256'h666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072_56616c69;
+defparam bootram.RAM6.INIT_0A=256'h616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d_642e2041;
+defparam bootram.RAM6.INIT_0B=256'h2e0a4661_6f756e64_67652066_20696d61_46504741_696f6e20_64756374_2070726f;
+defparam bootram.RAM6.INIT_0C=256'h726d7761_6e206669_6c742d69_20627569_6820746f_726f7567_67207468_6c6c696e;
+defparam bootram.RAM6.INIT_0D=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_72652e00;
+defparam bootram.RAM6.INIT_0E=256'h64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67_204c6f61_756e642e;
+defparam bootram.RAM6.INIT_0F=256'h65747572_523a2052_4552524f_2e000000_6d616765_6e672069_61727469_2e205374;
+defparam bootram.RAM6.INIT_10=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672;
+defparam bootram.RAM6.INIT_11=256'h64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068_206e6576;
+defparam bootram.RAM6.INIT_12=256'h7468726f_696e6720_46616c6c_6e642e20_20666f75_77617265_6669726d_696f6e20;
+defparam bootram.RAM6.INIT_13=256'h53706565_2e000000_77617265_6669726d_2d696e20_75696c74_746f2062_75676820;
+defparam bootram.RAM6.INIT_14=256'h58000000_57455f54_00000000_4e4f4e45_00000000_2025640a_7420746f_64207365;
+defparam bootram.RAM6.INIT_15=256'h20666c6f_726e6574_65746865_43000000_45545249_53594d4d_58000000_57455f52;
+defparam bootram.RAM6.INIT_16=256'h2077726f_4144563a_4e45475f_4155544f_5048595f_6c3a2000_6e74726f_7720636f;
+defparam bootram.RAM6.INIT_17=256'h00000001_00030003_00000000_780a0000_20307825_20676f74_7825782c_74652030;
+defparam bootram.RAM6.INIT_18=256'h68616e64_6b657420_20706163_64617465_6e207570_6f722069_21457272_00030203;
+defparam bootram.RAM6.INIT_19=256'h2025642c_6e677468_64206c65_796c6f61_64207061_65637465_20457870_6c65723a;
+defparam bootram.RAM6.INIT_1A=256'h00002261_000022b1_000022b1_0000220b_00000000_2025640a_20676f74_20627574;
+defparam bootram.RAM6.INIT_1B=256'h000022b1_000022b1_000022b1_000022b1_000022b1_000022b1_0000222a_0000224c;
+defparam bootram.RAM6.INIT_1C=256'h000022b1_000022a7_00002290_000022b1_000022b1_000022b1_000022b1_000022b1;
+defparam bootram.RAM6.INIT_1D=256'h34353637_30313233_00000000_6f72740a_0a0a6162_0000227d_0000223c_000022b1;
+defparam bootram.RAM6.INIT_1E=256'hffff00ff_ff00ffff_00ffffff_65000000_792e6578_64756d6d_43444546_38394142;
+defparam bootram.RAM6.INIT_1F=256'hffff0031_05050400_01010100_0000342c_00000000_00000000_00000000_ffffff00;
+defparam bootram.RAM6.INIT_20=256'h000033c8_10101200_000032a8_000032a0_00003298_00003290_000b0000_0018000f;
+defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff;
defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v
index abc32406e..e2539e183 100644
--- a/fpga/usrp2/top/N2x0/u2plus_core.v
+++ b/fpga/usrp2/top/N2x0/u2plus_core.v
@@ -149,10 +149,10 @@ module u2plus_core
);
localparam SR_MISC = 0; // 7 regs
- localparam SR_SIMTIMER = 8; // 2
+ localparam SR_USER_REGS = 8; // 2
localparam SR_TIME64 = 10; // 6
localparam SR_BUF_POOL = 16; // 4
- localparam SR_USER_REGS = 20; // 2
+ localparam SR_SPI_CORE = 20; // 3
localparam SR_RX_FRONT = 24; // 5
localparam SR_RX_CTRL0 = 32; // 9
localparam SR_RX_DSP0 = 48; // 7
@@ -278,9 +278,11 @@ module u2plus_core
.sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
.sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
- // Unused Slaves 9, b, c
+ assign s2_ack = 0;
assign s4_ack = 0;
- assign s9_ack = 0; assign sb_ack = 0; assign sc_ack = 0;
+ assign s9_ack = 0;
+ assign sb_ack = 0;
+ assign sc_ack = 0;
// ////////////////////////////////////////////////////////////////////////////////////////
// Reset Controller
@@ -373,6 +375,10 @@ module u2plus_core
wire wr3_ready_i, wr3_ready_o;
wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+ wire [35:0] sfc_wr_data, sfc_rd_data;
+ wire sfc_wr_ready, sfc_rd_ready;
+ wire sfc_wr_valid, sfc_rd_valid;
+
wire [35:0] tx_err_data;
wire tx_err_src_rdy, tx_err_dst_rdy;
@@ -393,21 +399,27 @@ module u2plus_core
.dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o),
.dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o),
.eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
- .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
+ .err_inp_data(tx_err_data), .err_inp_valid(tx_err_src_rdy), .err_inp_ready(tx_err_dst_rdy),
+ .ctl_inp_data(sfc_wr_data), .ctl_inp_valid(sfc_wr_valid), .ctl_inp_ready(sfc_wr_ready),
.ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
.dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+ .ctl_out_data(sfc_rd_data), .ctl_out_valid(sfc_rd_valid), .ctl_out_ready(sfc_rd_ready),
.eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
);
// /////////////////////////////////////////////////////////////////////////
// SPI -- Slave #2
- spi_top shared_spi
- (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
- .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
- .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
- .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
- .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+ wire [31:0] spi_debug;
+ wire [31:0] spi_readback;
+ wire spi_ready;
+ simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(9)) shared_spi(
+ .clock(dsp_clk), .reset(dsp_rst),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+ .readback(spi_readback), .ready(spi_ready),
+ .sen({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+ .sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug)
+ );
// /////////////////////////////////////////////////////////////////////////
// I2C -- Slave #3
@@ -436,18 +448,19 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd9, 16'd1}; //major, minor
- wire [31:0] churn = 0; //tweak churn until timing meets!
+ localparam compat_num = {16'd10, 16'd0}; //major, minor
+
+ wire [31:0] irq_readback = {18'b0, button, spi_ready, clk_status, serdes_link_up, 10'b0};
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
- .word00(churn),.word01(32'b0),.word02(32'b0),.word03(32'b0),
- .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
- .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13({18'b0, button, 1'b0, clk_status, serdes_link_up, 10'b0}),
- .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
+ .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff),
+ .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff),
+ .word08(status),.word09(32'hffff_ffff),.word10(32'hffff_ffff),
+ .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
+ .word14(32'hffff_ffff),.word15(32'hffff_ffff)
);
// /////////////////////////////////////////////////////////////////////////
@@ -477,9 +490,19 @@ module u2plus_core
assign s7_dat_i = 32'd0;
- settings_bus_crossclock settings_bus_crossclock
+ wire set_stb_dsp0, set_stb_dsp1;
+ wire [31:0] set_data_dsp0, set_data_dsp1;
+ wire [7:0] set_addr_dsp0, set_addr_dsp1;
+
+ //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio
+ assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1;
+ assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0;
+ assign set_data_dsp = set_stb_dsp1? set_data_dsp1 : set_data_dsp0;
+
+ settings_bus_crossclock #(.FLOW_CTRL(1/*on*/)) settings_bus_crossclock
(.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
- .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+ .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0),
+ .blocked(set_stb_dsp1));
user_settings #(.BASE(SR_USER_REGS)) user_settings
(.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp),
@@ -487,6 +510,29 @@ module u2plus_core
.set_addr_user(set_addr_user),.set_data_user(set_data_user),
.set_stb_user(set_stb_user) );
+ // /////////////////////////////////////////////////////////////////////////
+ // Settings + Readback Bus -- FIFO controlled
+
+ wire [31:0] sfc_debug;
+ wire sfc_clear;
+ settings_fifo_ctrl #(.PROT_DEST(3), .PROT_HDR(1)) sfc
+ (
+ .clock(dsp_clk), .reset(dsp_rst), .clear(sfc_clear),
+ .vita_time(vita_time), .perfs_ready(spi_ready),
+ .in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready),
+ .out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready),
+ .strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1),
+ .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff),
+ .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff),
+ .word08(32'hffff_ffff),.word09(gpio_readback),.word10(vita_time[63:32]),
+ .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(irq_readback),
+ .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
+ .debug(sfc_debug)
+ );
+
+ setting_reg #(.my_addr(SR_BUF_POOL+1/*same as packet dispatcher*/),.width(1)) sr_clear_sfc
+ (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear));
+
// Output control lines
wire [7:0] clock_outs, serdes_outs, adc_outs;
assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
diff --git a/fpga/usrp2/top/USRP2/Makefile b/fpga/usrp2/top/USRP2/Makefile
index 10610c7dc..94480a811 100644
--- a/fpga/usrp2/top/USRP2/Makefile
+++ b/fpga/usrp2/top/USRP2/Makefile
@@ -70,7 +70,7 @@ SYNTHESIZE_PROPERTIES = \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto \
-"Verilog Macros" "$(CUSTOM_DEFS)"
+"Verilog Macros" "FIFO_CTRL_NO_TIME=1 $(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v
index 93064254f..d8fe8cf10 100644
--- a/fpga/usrp2/top/USRP2/u2_core.v
+++ b/fpga/usrp2/top/USRP2/u2_core.v
@@ -154,10 +154,10 @@ module u2_core
);
localparam SR_MISC = 0; // 7 regs
- localparam SR_SIMTIMER = 8; // 2
+ localparam SR_USER_REGS = 8; // 2
localparam SR_TIME64 = 10; // 6
localparam SR_BUF_POOL = 16; // 4
- localparam SR_USER_REGS = 20; // 2
+ localparam SR_SPI_CORE = 20; // 3
localparam SR_RX_FRONT = 24; // 5
localparam SR_RX_CTRL0 = 32; // 9
localparam SR_RX_DSP0 = 48; // 7
@@ -284,10 +284,14 @@ module u2_core
.sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
.sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
- // Unused Slaves 4, 9 and b-f
+ assign s2_ack = 0;
assign s4_ack = 0;
- assign s9_ack = 0; assign sb_ack = 0; assign sc_ack = 0;
- assign sd_ack = 0; assign se_ack = 0; assign fc_ack = 0;
+ assign s9_ack = 0;
+ assign sb_ack = 0;
+ assign sc_ack = 0;
+ assign sd_ack = 0;
+ assign se_ack = 0;
+ assign sf_ack = 0;
// ////////////////////////////////////////////////////////////////////////////////////////
// Reset Controller
@@ -379,6 +383,10 @@ module u2_core
wire wr3_ready_i, wr3_ready_o;
wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+ wire [35:0] sfc_wr_data, sfc_rd_data;
+ wire sfc_wr_ready, sfc_rd_ready;
+ wire sfc_wr_valid, sfc_rd_valid;
+
wire [35:0] tx_err_data;
wire tx_err_src_rdy, tx_err_dst_rdy;
@@ -399,21 +407,27 @@ module u2_core
.dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o),
.dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o),
.eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
- .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
+ .err_inp_data(tx_err_data), .err_inp_valid(tx_err_src_rdy), .err_inp_ready(tx_err_dst_rdy),
+ .ctl_inp_data(sfc_wr_data), .ctl_inp_valid(sfc_wr_valid), .ctl_inp_ready(sfc_wr_ready),
.ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
.dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+ .ctl_out_data(sfc_rd_data), .ctl_out_valid(sfc_rd_valid), .ctl_out_ready(sfc_rd_ready),
.eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
);
// /////////////////////////////////////////////////////////////////////////
// SPI -- Slave #2
- spi_top shared_spi
- (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
- .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
- .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
- .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
- .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+ wire [31:0] spi_debug;
+ wire [31:0] spi_readback;
+ wire spi_ready;
+ simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(8)) shared_spi(
+ .clock(dsp_clk), .reset(dsp_rst),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+ .readback(spi_readback), .ready(spi_ready),
+ .sen({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+ .sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug)
+ );
// /////////////////////////////////////////////////////////////////////////
// I2C -- Slave #3
@@ -442,17 +456,18 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd9, 16'd1}; //major, minor
- wire [31:0] churn = 0; //tweak churn until timing meets!
+ localparam compat_num = {16'd10, 16'd0}; //major, minor
+
+ wire [31:0] irq_readback = {19'b0, spi_ready, clk_status, serdes_link_up, 10'b0};
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
- .word00(churn),.word01(32'b0),.word02(32'b0),.word03(32'b0),
- .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
+ .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff),
+ .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff),
.word08(status),.word09(gpio_readback),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13({20'b0, clk_status, serdes_link_up, 10'b0}),
+ .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
);
@@ -483,9 +498,19 @@ module u2_core
assign s7_dat_i = 32'd0;
- settings_bus_crossclock settings_bus_crossclock
+ wire set_stb_dsp0, set_stb_dsp1;
+ wire [31:0] set_data_dsp0, set_data_dsp1;
+ wire [7:0] set_addr_dsp0, set_addr_dsp1;
+
+ //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio
+ assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1;
+ assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0;
+ assign set_data_dsp = set_stb_dsp1? set_data_dsp1 : set_data_dsp0;
+
+ settings_bus_crossclock #(.FLOW_CTRL(1/*on*/)) settings_bus_crossclock
(.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
- .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+ .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0),
+ .blocked(set_stb_dsp1));
user_settings #(.BASE(SR_USER_REGS)) user_settings
(.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp),
@@ -493,6 +518,38 @@ module u2_core
.set_addr_user(set_addr_user),.set_data_user(set_data_user),
.set_stb_user(set_stb_user) );
+ // /////////////////////////////////////////////////////////////////////////
+ // Settings + Readback Bus -- FIFO controlled
+
+ wire [31:0] sfc_debug;
+ wire sfc_clear;
+ /*
+ settings_fifo_ctrl #(.PROT_DEST(3), .PROT_HDR(1)) sfc
+ (
+ .clock(dsp_clk), .reset(dsp_rst), .clear(sfc_clear),
+ .vita_time(vita_time), .perfs_ready(spi_ready),
+ .in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready),
+ .out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready),
+ .strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1),
+ .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff),
+ .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff),
+ .word08(32'hffff_ffff),.word09(gpio_readback),.word10(vita_time[63:32]),
+ .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(irq_readback),
+ .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
+ .debug(sfc_debug)
+ );
+ */
+ assign sfc_debug = 0;
+ assign set_stb_dsp1 = 0;
+ assign set_addr_dsp1 = 0;
+ assign set_data_dsp1 = 0;
+ assign sfc_rd_ready = 1;
+ assign sfc_wr_valid = 0;
+ assign sfc_wr_data = 0;
+
+ setting_reg #(.my_addr(SR_BUF_POOL+1/*same as packet dispatcher*/),.width(1)) sr_clear_sfc
+ (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear));
+
// Output control lines
wire [7:0] clock_outs, serdes_outs, adc_outs;
assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v
index 514df1151..6e4b8025d 100644
--- a/fpga/usrp2/vrt/vita_rx_framer.v
+++ b/fpga/usrp2/vrt/vita_rx_framer.v
@@ -85,9 +85,11 @@ module vita_rx_framer
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(samples_per_packet),.changed());
- setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(1)) sr_numchan
+ assign numchan = 0;/*
+ setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(0)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
+ */
// Output FIFO for packetized data
localparam VITA_IDLE = 0;
@@ -164,7 +166,7 @@ module vita_rx_framer
VITA_PAYLOAD :
if(sample_fifo_src_rdy_i)
begin
- if(sample_phase == (numchan-4'd1))
+ if(sample_phase == numchan)
begin
sample_phase <= 0;
sample_ctr <= sample_ctr + 1;
@@ -213,7 +215,7 @@ module vita_rx_framer
assign data_o[35:34] = 2'b00; // Always write full lines
assign sample_fifo_dst_rdy_o = pkt_fifo_rdy &
( ((vita_state==VITA_PAYLOAD) &
- (sample_phase == (numchan-4'd1)) &
+ (sample_phase == numchan) &
~|flags_fifo_o[4:1]) |
(vita_state==VITA_ERR_PAYLOAD));
diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v
index 6919da11a..ed3916311 100644
--- a/fpga/usrp2/vrt/vita_tx_deframer.v
+++ b/fpga/usrp2/vrt/vita_tx_deframer.v
@@ -43,10 +43,11 @@ module vita_tx_deframer
localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
- wire [1:0] numchan;
+ wire [1:0] numchan = 0;/*
setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
+ */
reg [3:0] vita_state;
wire has_streamid, has_classid, has_secs, has_tics, has_trailer;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 15:24:40 +0000