diff options
Diffstat (limited to 'fpga/usrp3/top/x400')
| -rw-r--r-- | fpga/usrp3/top/x400/dboards/zbx/cpld/ctrlport_window.v | 73 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm | 3 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm | 188 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh | 15 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh | 4 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/rfdc_timing_control.v | 101 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/x4xx.v | 4 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/x4xx_core.v | 202 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/x4xx_core_common.v | 339 |
10 files changed, 626 insertions, 305 deletions
diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ctrlport_window.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/ctrlport_window.v deleted file mode 100644 index 4a886d34d..000000000 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/ctrlport_window.v +++ /dev/null @@ -1,73 +0,0 @@ -// -// Copyright 2021 Ettus Research, a National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: ctrlport_window -// -// Description: -// Copy requests from slave to master interface when s_ctrlport_req_addr is in -// address range specified by BASE_ADDRESS and WINDOW_SIZE. The modules does -// not use any registers and therefore does not need ctrlport_clk and -// ctrlport_rst. -// - -`default_nettype none - -module ctrlport_window #( - parameter BASE_ADDRESS = 0, - parameter WINDOW_SIZE = 32 -) ( - // Slave Interface - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [ 9:0] s_ctrlport_req_portid, - input wire [15:0] s_ctrlport_req_rem_epid, - input wire [ 9:0] s_ctrlport_req_rem_portid, - input wire [31:0] s_ctrlport_req_data, - input wire [ 3:0] s_ctrlport_req_byte_en, - input wire s_ctrlport_req_has_time, - input wire [63:0] s_ctrlport_req_time, - output wire s_ctrlport_resp_ack, - output wire [ 1:0] s_ctrlport_resp_status, - output wire [31:0] s_ctrlport_resp_data, - - // Master Interface - output wire m_ctrlport_req_wr, - output wire m_ctrlport_req_rd, - output wire [19:0] m_ctrlport_req_addr, - output wire [ 9:0] m_ctrlport_req_portid, - output wire [15:0] m_ctrlport_req_rem_epid, - output wire [ 9:0] m_ctrlport_req_rem_portid, - output wire [31:0] m_ctrlport_req_data, - output wire [ 3:0] m_ctrlport_req_byte_en, - output wire m_ctrlport_req_has_time, - output wire [63:0] m_ctrlport_req_time, - input wire m_ctrlport_resp_ack, - input wire [ 1:0] m_ctrlport_resp_status, - input wire [31:0] m_ctrlport_resp_data -); - - // Mask write and read flag - wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + WINDOW_SIZE); - assign m_ctrlport_req_wr = s_ctrlport_req_wr & address_in_range; - assign m_ctrlport_req_rd = s_ctrlport_req_rd & address_in_range; - - // Forward all other signals untouched. - assign m_ctrlport_req_addr = s_ctrlport_req_addr; - assign m_ctrlport_req_portid = s_ctrlport_req_portid; - assign m_ctrlport_req_rem_epid = s_ctrlport_req_rem_epid; - assign m_ctrlport_req_rem_portid = s_ctrlport_req_rem_portid; - assign m_ctrlport_req_data = s_ctrlport_req_data; - assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en; - assign m_ctrlport_req_has_time = s_ctrlport_req_has_time; - assign m_ctrlport_req_time = s_ctrlport_req_time; - - assign s_ctrlport_resp_ack = m_ctrlport_resp_ack; - assign s_ctrlport_resp_status = m_ctrlport_resp_status; - assign s_ctrlport_resp_data = m_ctrlport_resp_data; - -endmodule - -`default_nettype wire diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf index c164b34e5..0e75b610c 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf @@ -886,4 +886,4 @@ set_global_assignment -name TOP_LEVEL_ENTITY zbx_top_cpld -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm index 050be6b86..69ee17738 100644 --- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm @@ -543,7 +543,8 @@ </p> <div class="sh" id="div_RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS"> <p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|DB_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|DB_WINDOW');">DB_WINDOW</span></p> - <p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW');">RFDC_TIMING_WINDOW</span></p> + <p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW');">RFDC_TIMING_WINDOW</span></p> + <p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|DIO_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|DIO_WINDOW');">DIO_WINDOW</span></p> </div> </div> <p> diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm index 480da73d6..be0e58707 100644 --- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm +++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm @@ -3274,7 +3274,7 @@ Total Offset =</td></tr> </td> -<td class="outercell" rowspan="1"> +<td class="outercell" rowspan="2"> <table border="0" cellspacing="0" cellpadding="0"> <tr><td class="offset_info" align="right">DIO_MASTER_REGISTER</td></tr> @@ -3300,6 +3300,38 @@ Total Offset =</td></tr> </tr> +<tr> + +<td class="outercell" rowspan="1"></td> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + <tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr> + <tr><td class="offset_info" align="right"> 0x00C000</td></tr> +</table> + +</td> + +<td class="outercell" rowspan="1"></td> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + +<tr><td class="offset_info"> + + +Total Offset =</td></tr> +<tr><td class="offset_info"> 0x00C000 + +</td></tr> +</table> + +</td> + +</tr> + </table><p/> <p class="reg_info">Initial Value = 0x00000000 @@ -3397,7 +3429,7 @@ Sets whether the DIO signal line is driven by this register interface or the use </td> -<td class="outercell" rowspan="1"> +<td class="outercell" rowspan="2"> <table border="0" cellspacing="0" cellpadding="0"> <tr><td class="offset_info" align="right">DIO_DIRECTION_REGISTER</td></tr> @@ -3423,6 +3455,38 @@ Total Offset =</td></tr> </tr> +<tr> + +<td class="outercell" rowspan="1"></td> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + <tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr> + <tr><td class="offset_info" align="right"> 0x00C000</td></tr> +</table> + +</td> + +<td class="outercell" rowspan="1"></td> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + +<tr><td class="offset_info"> + + +Total Offset =</td></tr> +<tr><td class="offset_info"> 0x00C004 + +</td></tr> +</table> + +</td> + +</tr> + </table><p/> <p class="reg_info">Initial Value = 0x00000000 @@ -3520,7 +3584,7 @@ Set the direction of FPGA buffer connected to DIO ports on the DIO board.<br/> </td> -<td class="outercell" rowspan="1"> +<td class="outercell" rowspan="2"> <table border="0" cellspacing="0" cellpadding="0"> <tr><td class="offset_info" align="right">DIO_INPUT_REGISTER</td></tr> @@ -3546,6 +3610,38 @@ Total Offset =</td></tr> </tr> +<tr> + +<td class="outercell" rowspan="1"></td> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + <tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr> + <tr><td class="offset_info" align="right"> 0x00C000</td></tr> +</table> + +</td> + +<td class="outercell" rowspan="1"></td> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + +<tr><td class="offset_info"> + + +Total Offset =</td></tr> +<tr><td class="offset_info"> 0x00C008 + +</td></tr> +</table> + +</td> + +</tr> + </table><p/> <p class="reg_info">Initial Value not specified @@ -3642,7 +3738,7 @@ Status of each bit at the FPGA input. </td> -<td class="outercell" rowspan="1"> +<td class="outercell" rowspan="2"> <table border="0" cellspacing="0" cellpadding="0"> <tr><td class="offset_info" align="right">DIO_OUTPUT_REGISTER</td></tr> @@ -3668,6 +3764,38 @@ Total Offset =</td></tr> </tr> +<tr> + +<td class="outercell" rowspan="1"></td> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + <tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr> + <tr><td class="offset_info" align="right"> 0x00C000</td></tr> +</table> + +</td> + +<td class="outercell" rowspan="1"></td> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + +<tr><td class="offset_info"> + + +Total Offset =</td></tr> +<tr><td class="offset_info"> 0x00C00C + +</td></tr> +</table> + +</td> + +</tr> + </table><p/> <p class="reg_info">Initial Value = 0x00000000 @@ -14357,7 +14485,7 @@ Total Offset =</td></tr> </table><p/> -<p class="reg_info">This window is defined in HDL source file rfdc_timing_control.v.</p> +<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p> </div> @@ -14387,7 +14515,7 @@ Daughterboard GPIO interface. Register access within this space <table border="0" cellspacing="0" cellpadding="0"> <tr><td class="offset_info" align="right">RFDC_TIMING_WINDOW</td></tr> <tr><td class="offset_info" align="right"> offset=0x8000</td></tr> - <tr><td class="offset_info" align="right"> size=0x8000 (32 Kbytes)</td></tr> + <tr><td class="offset_info" align="right"> size=0x4000 (16 Kbytes)</td></tr> </table> </td> @@ -14396,7 +14524,7 @@ Daughterboard GPIO interface. Register access within this space </table><p/> -<p class="reg_info">This window is defined in HDL source file rfdc_timing_control.v.</p> +<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p> </div> @@ -14408,6 +14536,44 @@ RFDC timing control interface. </div> + <div class="register"> + <a name="RADIO_CTRLPORT_REGMAP|DIO_WINDOW"></a> + +<h3 class="register">Offset 0xC000: DIO_WINDOW Window (R|W)</h3> +<p class="offset_info"> Target regmap = <a href="#DIO_REGMAP">DIO_REGMAP</a></p> + <a class="sh_addrs" href="javascript:sa('RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in')">(<span id="show_RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in">show</span> extended info)</a> + <div class="sh_addrs" id="div_RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in"> + + <table class="extended_info"> + +<tr> + +<td class="outercell" rowspan="1"> + +<table border="0" cellspacing="0" cellpadding="0"> + <tr><td class="offset_info" align="right">DIO_WINDOW</td></tr> + <tr><td class="offset_info" align="right"> offset=0xC000</td></tr> + <tr><td class="offset_info" align="right"> size=0x4000 (16 Kbytes)</td></tr> +</table> + +</td> + +</tr> + +</table><p/> + +<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p> + +</div> + +<div class="info"> + +DIO control interface + +</div> + +</div> + </div> </div> @@ -21627,9 +21793,9 @@ FPGA version.<BR/> <tr valign="top"> - <td class='value'>3</td> + <td class='value'>4</td> - <td class='l'>0x00000003</td> + <td class='l'>0x00000004</td> <td class="l" style="text-align: left;"> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p> @@ -21666,9 +21832,9 @@ FPGA version.<BR/> <tr valign="top"> - <td class='value'>553915926</td> + <td class='value'>554176790</td> - <td class='l'>0x21041616</td> + <td class='l'>0x21081116</td> <td class="l" style="text-align: left;"> <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p> diff --git a/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh index 18d442cd1..d9ffa1b38 100644 --- a/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh @@ -11,8 +11,9 @@ // A numerically ordered list of registers and their HDL source files //=============================================================================== - // DB_WINDOW : 0x0 (rfdc_timing_control.v) - // RFDC_TIMING_WINDOW : 0x8000 (rfdc_timing_control.v) + // DB_WINDOW : 0x0 (x4xx_core_common.v) + // RFDC_TIMING_WINDOW : 0x8000 (x4xx_core_common.v) + // DIO_WINDOW : 0xC000 (x4xx_core_common.v) //=============================================================================== // RegTypes @@ -22,10 +23,14 @@ // Register Group RADIO_CTRLPORT_WINDOWS //=============================================================================== - // DB_WINDOW Window (from rfdc_timing_control.v) + // DB_WINDOW Window (from x4xx_core_common.v) localparam DB_WINDOW = 'h0; // Window Offset localparam DB_WINDOW_SIZE = 'h8000; // size in bytes - // RFDC_TIMING_WINDOW Window (from rfdc_timing_control.v) + // RFDC_TIMING_WINDOW Window (from x4xx_core_common.v) localparam RFDC_TIMING_WINDOW = 'h8000; // Window Offset - localparam RFDC_TIMING_WINDOW_SIZE = 'h8000; // size in bytes + localparam RFDC_TIMING_WINDOW_SIZE = 'h4000; // size in bytes + + // DIO_WINDOW Window (from x4xx_core_common.v) + localparam DIO_WINDOW = 'hC000; // Window Offset + localparam DIO_WINDOW_SIZE = 'h4000; // size in bytes diff --git a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh index 48401684a..6f34f9e25 100644 --- a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh @@ -82,10 +82,10 @@ localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD - localparam FPGA_CURRENT_VERSION_MINOR = 'h3; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR + localparam FPGA_CURRENT_VERSION_MINOR = 'h4; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21041616; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21081116; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_100M_VERSION localparam RF_CORE_100M_VERSION_SIZE = 7; diff --git a/fpga/usrp3/top/x400/rfdc_timing_control.v b/fpga/usrp3/top/x400/rfdc_timing_control.v index f1f1cfad1..6177505f7 100644 --- a/fpga/usrp3/top/x400/rfdc_timing_control.v +++ b/fpga/usrp3/top/x400/rfdc_timing_control.v @@ -8,10 +8,7 @@ // Description: // // This module handles timed register writes for the RFDC, such as NCO reset -// control. It takes the CtrlPort master from each radio block and splits it -// into a CtrlPort bus for the associated daughter board and another CtrlPort -// bus for the RFDC timing control. Timed commands on the RF timing bus are -// handled by the ctrlport_timer module. +// control. Timed commands are handled by the ctrlport_timer module. // // Parameters: // @@ -45,18 +42,6 @@ module rfdc_timing_control #( output wire [ 2*NUM_DBOARDS-1:0] s_ctrlport_resp_status, output wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_resp_data, - // CtrlPort Master (to Daughter Boards) - output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_req_wr, - output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_req_rd, - output wire [ 20*NUM_DBOARDS-1:0] m_ctrlport_req_addr, - output wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_req_data, - output wire [ 4*NUM_DBOARDS-1:0] m_ctrlport_req_byte_en, - output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_req_has_time, - output wire [ 64*NUM_DBOARDS-1:0] m_ctrlport_req_time, - input wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_resp_ack, - input wire [ 2*NUM_DBOARDS-1:0] m_ctrlport_resp_status, - input wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_resp_data, - // RF Reset Control output reg start_nco_reset, input wire nco_reset_done, @@ -64,7 +49,6 @@ module rfdc_timing_control #( output reg dac_reset_pulse ); - `include "regmap/radio_ctrlport_regmap_utils.vh" `include "regmap/rfdc_timing_regmap_utils.vh" // Reset registers @@ -77,54 +61,6 @@ module rfdc_timing_control #( for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_db_ctrlport //----------------------------------------------------------------------- - // CtrlPort Splitter - //----------------------------------------------------------------------- - - wire [ 1-1:0] rf_ctrlport_req_wr; - wire [ 1-1:0] rf_ctrlport_req_rd; - wire [ 20-1:0] rf_ctrlport_req_addr; - wire [ 32-1:0] rf_ctrlport_req_data; - wire [ 4-1:0] rf_ctrlport_req_byte_en; - wire [ 1-1:0] rf_ctrlport_req_has_time; - wire [ 64-1:0] rf_ctrlport_req_time; - wire [ 1-1:0] rf_ctrlport_resp_ack; - wire [ 2-1:0] rf_ctrlport_resp_status; - wire [ 32-1:0] rf_ctrlport_resp_data; - - localparam [31:0] RFDC_TIMING_WINDOW_SIZE_W = $clog2(RFDC_TIMING_WINDOW_SIZE); - localparam [31:0] DB_WINDOW_SIZE_W = $clog2(DB_WINDOW_SIZE); - - ctrlport_decoder_param #( - .NUM_SLAVES (2), - .PORT_BASE ({ RFDC_TIMING_WINDOW[19:0], DB_WINDOW[19:0] }), - .PORT_ADDR_W ({ RFDC_TIMING_WINDOW_SIZE_W, DB_WINDOW_SIZE_W }) - ) ctrlport_decoder_param_i ( - .ctrlport_clk (clk), - .ctrlport_rst (rst), - .s_ctrlport_req_wr (s_ctrlport_req_wr [ 1*db+: 1]), - .s_ctrlport_req_rd (s_ctrlport_req_rd [ 1*db+: 1]), - .s_ctrlport_req_addr (s_ctrlport_req_addr [20*db+:20]), - .s_ctrlport_req_data (s_ctrlport_req_data [32*db+:32]), - .s_ctrlport_req_byte_en (s_ctrlport_req_byte_en [ 4*db+: 4]), - .s_ctrlport_req_has_time (s_ctrlport_req_has_time [ 1*db+: 1]), - .s_ctrlport_req_time (s_ctrlport_req_time [64*db+:64]), - .s_ctrlport_resp_ack (s_ctrlport_resp_ack [ 1*db+: 1]), - .s_ctrlport_resp_status (s_ctrlport_resp_status [ 2*db+: 2]), - .s_ctrlport_resp_data (s_ctrlport_resp_data [32*db+:32]), - .m_ctrlport_req_wr ({ rf_ctrlport_req_wr, m_ctrlport_req_wr [ 1*db+: 1] }), - .m_ctrlport_req_rd ({ rf_ctrlport_req_rd, m_ctrlport_req_rd [ 1*db+: 1] }), - .m_ctrlport_req_addr ({ rf_ctrlport_req_addr, m_ctrlport_req_addr [20*db+:20] }), - .m_ctrlport_req_data ({ rf_ctrlport_req_data, m_ctrlport_req_data [32*db+:32] }), - .m_ctrlport_req_byte_en ({ rf_ctrlport_req_byte_en, m_ctrlport_req_byte_en [ 4*db+: 4] }), - .m_ctrlport_req_has_time ({ rf_ctrlport_req_has_time, m_ctrlport_req_has_time [ 1*db+: 1] }), - .m_ctrlport_req_time ({ rf_ctrlport_req_time, m_ctrlport_req_time [64*db+:64] }), - .m_ctrlport_resp_ack ({ rf_ctrlport_resp_ack, m_ctrlport_resp_ack [ 1*db+: 1] }), - .m_ctrlport_resp_status ({ rf_ctrlport_resp_status, m_ctrlport_resp_status [ 2*db+: 2] }), - .m_ctrlport_resp_data ({ rf_ctrlport_resp_data, m_ctrlport_resp_data [32*db+:32] }) - ); - - - //----------------------------------------------------------------------- // RF Reset Control //----------------------------------------------------------------------- @@ -143,16 +79,16 @@ module rfdc_timing_control #( .time_now (time_now), .time_now_stb (time_now_stb), .time_ignore_bits (time_ignore_bits), - .s_ctrlport_req_wr (rf_ctrlport_req_wr), - .s_ctrlport_req_rd (rf_ctrlport_req_rd), - .s_ctrlport_req_addr (rf_ctrlport_req_addr), - .s_ctrlport_req_data (rf_ctrlport_req_data), - .s_ctrlport_req_byte_en (rf_ctrlport_req_byte_en), - .s_ctrlport_req_has_time (rf_ctrlport_req_has_time), - .s_ctrlport_req_time (rf_ctrlport_req_time), - .s_ctrlport_resp_ack (rf_ctrlport_resp_ack), - .s_ctrlport_resp_status (rf_ctrlport_resp_status), - .s_ctrlport_resp_data (rf_ctrlport_resp_data), + .s_ctrlport_req_wr (s_ctrlport_req_wr [ 1*db+: 1]), + .s_ctrlport_req_rd (s_ctrlport_req_rd [ 1*db+: 1]), + .s_ctrlport_req_addr (s_ctrlport_req_addr [20*db+:20]), + .s_ctrlport_req_data (s_ctrlport_req_data [32*db+:32]), + .s_ctrlport_req_byte_en (s_ctrlport_req_byte_en [ 4*db+: 4]), + .s_ctrlport_req_has_time (s_ctrlport_req_has_time [ 1*db+: 1]), + .s_ctrlport_req_time (s_ctrlport_req_time [64*db+:64]), + .s_ctrlport_resp_ack (s_ctrlport_resp_ack [ 1*db+: 1]), + .s_ctrlport_resp_status (s_ctrlport_resp_status [ 2*db+: 2]), + .s_ctrlport_resp_data (s_ctrlport_resp_data [32*db+:32]), .m_ctrlport_req_wr (nco_ctrlport_req_wr), .m_ctrlport_req_rd (nco_ctrlport_req_rd), .m_ctrlport_req_addr (nco_ctrlport_req_addr), @@ -240,21 +176,6 @@ endmodule //XmlParse xml_on // -//<regmap name="RADIO_CTRLPORT_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true"> -// <group name="RADIO_CTRLPORT_WINDOWS"> -// <info>Each radio's CtrlPort peripheral interface is divided into the -// following memory spaces. Note that the CtrlPort peripheral interface -// starts at offset 0x80000 in the RFNoC Radio block's register space.</info> -// <window name="DB_WINDOW" offset="0x00000" size="0x08000"> -// <info>Daughterboard GPIO interface. Register access within this space -// is directed to the associated daughterboard CPLD.</info> -// </window> -// <window name="RFDC_TIMING_WINDOW" offset="0x08000" size="0x08000" targetregmap="RFDC_TIMING_REGMAP"> -// <info>RFDC timing control interface.</info> -// </window> -// </group> -//</regmap> -// //<regmap name="RFDC_TIMING_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true"> // <group name="RFDC_TIMING_REGS"> // <register name="NCO_RESET_REG" offset="0x00" size="32" readable="true" writable="true"> diff --git a/fpga/usrp3/top/x400/x4xx.v b/fpga/usrp3/top/x400/x4xx.v index 4b1ffd11c..69b4ea2de 100644 --- a/fpga/usrp3/top/x400/x4xx.v +++ b/fpga/usrp3/top/x400/x4xx.v @@ -2220,12 +2220,12 @@ endmodule // <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED // </info> // <value name="FPGA_CURRENT_VERSION_MAJOR" integer="7"/> -// <value name="FPGA_CURRENT_VERSION_MINOR" integer="3"/> +// <value name="FPGA_CURRENT_VERSION_MINOR" integer="4"/> // <value name="FPGA_CURRENT_VERSION_BUILD" integer="0"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="7"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/> // <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/> -// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x21041616"/> +// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x21081116"/> // </enumeratedtype> // </group> //</regmap> diff --git a/fpga/usrp3/top/x400/x4xx_core.v b/fpga/usrp3/top/x400/x4xx_core.v index e099b0c25..c02596e27 100644 --- a/fpga/usrp3/top/x400/x4xx_core.v +++ b/fpga/usrp3/top/x400/x4xx_core.v @@ -230,69 +230,107 @@ module x4xx_core #( .reset_out (ctrlport_rst) ); + wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_wr; + wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_rd; + wire [ 20*NUM_DBOARDS-1:0] ctrlport_radio_req_addr; + wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_req_data; + wire [ 4*NUM_DBOARDS-1:0] ctrlport_radio_req_byte_en; + wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_has_time; + wire [ 64*NUM_DBOARDS-1:0] ctrlport_radio_req_time; + wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_resp_ack; + wire [ 2*NUM_DBOARDS-1:0] ctrlport_radio_resp_status; + wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_resp_data; + + x4xx_core_common #( .CHDR_CLK_RATE (CHDR_CLK_RATE), .CHDR_W (CHDR_W), .RFNOC_PROTOVER (RFNOC_PROTOVER), + .NUM_DBOARDS (NUM_DBOARDS), .PCIE_PRESENT (0) ) x4xx_core_common_i ( - .radio_clk (radio_clk), - .radio_rst (radio_rst), - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_chdr_rst (rfnoc_chdr_rst), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst), - .ctrlport_clk (s_axi_aclk), - .ctrlport_rst (ctrlport_rst), - .s_ctrlport_req_wr (ctrlport_req_wr), - .s_ctrlport_req_rd (ctrlport_req_rd), - .s_ctrlport_req_addr (ctrlport_req_addr), - .s_ctrlport_req_portid (ctrlport_req_portid), - .s_ctrlport_req_rem_epid (ctrlport_req_rem_epid), - .s_ctrlport_req_rem_portid (ctrlport_req_rem_portid), - .s_ctrlport_req_data (ctrlport_req_data), - .s_ctrlport_req_byte_en (ctrlport_req_byte_en), - .s_ctrlport_req_has_time (ctrlport_req_has_time), - .s_ctrlport_req_time (ctrlport_req_time), - .s_ctrlport_resp_ack (ctrlport_resp_ack), - .s_ctrlport_resp_status (ctrlport_resp_status), - .s_ctrlport_resp_data (ctrlport_resp_data), - .pps_radioclk (pps_radioclk), - .pps_select (pps_select), - .trig_io_select (trig_io_select), - .pll_sync_trigger (pll_sync_trigger), - .pll_sync_delay (pll_sync_delay), - .pll_sync_done (pll_sync_done), - .pps_brc_delay (pps_brc_delay), - .pps_prc_delay (pps_prc_delay), - .prc_rc_divider (prc_rc_divider), - .pps_rc_enabled (pps_rc_enabled), - .radio_spc (RADIO_SPC), - .radio_time (radio_time), - .sample_rx_stb (radio_time_stb), - .gpio_in_a (gpio_in_a), - .gpio_in_b (gpio_in_b), - .gpio_out_a (gpio_out_a), - .gpio_out_b (gpio_out_b), - .gpio_en_a (gpio_en_a), - .gpio_en_b (gpio_en_b), - .gpio_in_fabric_a (), - .gpio_in_fabric_b (), - .gpio_out_fabric_a (12'b0), - .gpio_out_fabric_b (12'b0), - .qsfp_port_0_0_info (qsfp_port_0_0_info), - .qsfp_port_0_1_info (qsfp_port_0_1_info), - .qsfp_port_0_2_info (qsfp_port_0_2_info), - .qsfp_port_0_3_info (qsfp_port_0_3_info), - .qsfp_port_1_0_info (qsfp_port_1_0_info), - .qsfp_port_1_1_info (qsfp_port_1_1_info), - .qsfp_port_1_2_info (qsfp_port_1_2_info), - .qsfp_port_1_3_info (qsfp_port_1_3_info), - .device_id (device_id), - .mfg_test_en_fabric_clk (mfg_test_en_fabric_clk), - .mfg_test_en_gty_rcv_clk (mfg_test_en_gty_rcv_clk), - .fpga_aux_ref (fpga_aux_ref), - .version_info (version_info) + .radio_clk (radio_clk), + .radio_rst (radio_rst), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .ctrlport_clk (s_axi_aclk), + .ctrlport_rst (ctrlport_rst), + .s_ctrlport_req_wr (ctrlport_req_wr), + .s_ctrlport_req_rd (ctrlport_req_rd), + .s_ctrlport_req_addr (ctrlport_req_addr), + .s_ctrlport_req_portid (ctrlport_req_portid), + .s_ctrlport_req_rem_epid (ctrlport_req_rem_epid), + .s_ctrlport_req_rem_portid (ctrlport_req_rem_portid), + .s_ctrlport_req_data (ctrlport_req_data), + .s_ctrlport_req_byte_en (ctrlport_req_byte_en), + .s_ctrlport_req_has_time (ctrlport_req_has_time), + .s_ctrlport_req_time (ctrlport_req_time), + .s_ctrlport_resp_ack (ctrlport_resp_ack), + .s_ctrlport_resp_status (ctrlport_resp_status), + .s_ctrlport_resp_data (ctrlport_resp_data), + .pps_radioclk (pps_radioclk), + .pps_select (pps_select), + .trig_io_select (trig_io_select), + .pll_sync_trigger (pll_sync_trigger), + .pll_sync_delay (pll_sync_delay), + .pll_sync_done (pll_sync_done), + .pps_brc_delay (pps_brc_delay), + .pps_prc_delay (pps_prc_delay), + .prc_rc_divider (prc_rc_divider), + .pps_rc_enabled (pps_rc_enabled), + .radio_spc (RADIO_SPC), + .radio_time (radio_time), + .sample_rx_stb (radio_time_stb), + .time_ignore_bits ($clog2(RADIO_SPC)), + .gpio_in_a (gpio_in_a), + .gpio_in_b (gpio_in_b), + .gpio_out_a (gpio_out_a), + .gpio_out_b (gpio_out_b), + .gpio_en_a (gpio_en_a), + .gpio_en_b (gpio_en_b), + .gpio_in_fabric_a (), + .gpio_in_fabric_b (), + .gpio_out_fabric_a (12'b0), + .gpio_out_fabric_b (12'b0), + .s_radio_ctrlport_req_wr (ctrlport_radio_req_wr), + .s_radio_ctrlport_req_rd (ctrlport_radio_req_rd), + .s_radio_ctrlport_req_addr (ctrlport_radio_req_addr), + .s_radio_ctrlport_req_data (ctrlport_radio_req_data), + .s_radio_ctrlport_req_byte_en (ctrlport_radio_req_byte_en), + .s_radio_ctrlport_req_has_time (ctrlport_radio_req_has_time), + .s_radio_ctrlport_req_time (ctrlport_radio_req_time), + .s_radio_ctrlport_resp_ack (ctrlport_radio_resp_ack), + .s_radio_ctrlport_resp_status (ctrlport_radio_resp_status), + .s_radio_ctrlport_resp_data (ctrlport_radio_resp_data), + .m_radio_ctrlport_req_wr (m_ctrlport_radio_req_wr), + .m_radio_ctrlport_req_rd (m_ctrlport_radio_req_rd), + .m_radio_ctrlport_req_addr (m_ctrlport_radio_req_addr), + .m_radio_ctrlport_req_data (m_ctrlport_radio_req_data), + .m_radio_ctrlport_req_byte_en (m_ctrlport_radio_req_byte_en), + .m_radio_ctrlport_req_has_time (m_ctrlport_radio_req_has_time), + .m_radio_ctrlport_req_time (m_ctrlport_radio_req_time), + .m_radio_ctrlport_resp_ack (m_ctrlport_radio_resp_ack), + .m_radio_ctrlport_resp_status (m_ctrlport_radio_resp_status), + .m_radio_ctrlport_resp_data (m_ctrlport_radio_resp_data), + .start_nco_reset (start_nco_reset), + .nco_reset_done (nco_reset_done), + .adc_reset_pulse (adc_reset_pulse), + .dac_reset_pulse (dac_reset_pulse), + .qsfp_port_0_0_info (qsfp_port_0_0_info), + .qsfp_port_0_1_info (qsfp_port_0_1_info), + .qsfp_port_0_2_info (qsfp_port_0_2_info), + .qsfp_port_0_3_info (qsfp_port_0_3_info), + .qsfp_port_1_0_info (qsfp_port_1_0_info), + .qsfp_port_1_1_info (qsfp_port_1_1_info), + .qsfp_port_1_2_info (qsfp_port_1_2_info), + .qsfp_port_1_3_info (qsfp_port_1_3_info), + .device_id (device_id), + .mfg_test_en_fabric_clk (mfg_test_en_fabric_clk), + .mfg_test_en_gty_rcv_clk (mfg_test_en_gty_rcv_clk), + .fpga_aux_ref (fpga_aux_ref), + .version_info (version_info) ); // Provide information for ctrlport timed commands @@ -306,17 +344,6 @@ module x4xx_core #( // Calculate how may bits wide each channel is localparam CHAN_W = 32 * RADIO_SPC; - wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_wr; - wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_rd; - wire [ 20*NUM_DBOARDS-1:0] ctrlport_radio_req_addr; - wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_req_data; - wire [ 4*NUM_DBOARDS-1:0] ctrlport_radio_req_byte_en; - wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_has_time; - wire [ 64*NUM_DBOARDS-1:0] ctrlport_radio_req_time; - wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_resp_ack; - wire [ 2*NUM_DBOARDS-1:0] ctrlport_radio_resp_status; - wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_resp_data; - rfnoc_image_core #( .CHDR_W (CHDR_W), .MTU (MTU), @@ -412,43 +439,4 @@ module x4xx_core #( .m_dma_tready (dmao_tready) ); - - //------------------------------------------------------------------------- - // RF Timing Reset Control - //------------------------------------------------------------------------- - - rfdc_timing_control #( - .NUM_DBOARDS (NUM_DBOARDS) - ) rfdc_timing_control_i ( - .clk (radio_clk), - .rst (radio_rst), - .time_now (radio_time), - .time_now_stb (radio_time_stb), - .time_ignore_bits ($clog2(RADIO_SPC)), - .s_ctrlport_req_wr (ctrlport_radio_req_wr), - .s_ctrlport_req_rd (ctrlport_radio_req_rd), - .s_ctrlport_req_addr (ctrlport_radio_req_addr), - .s_ctrlport_req_data (ctrlport_radio_req_data), - .s_ctrlport_req_byte_en (ctrlport_radio_req_byte_en), - .s_ctrlport_req_has_time (ctrlport_radio_req_has_time), - .s_ctrlport_req_time (ctrlport_radio_req_time), - .s_ctrlport_resp_ack (ctrlport_radio_resp_ack), - .s_ctrlport_resp_status (ctrlport_radio_resp_status), - .s_ctrlport_resp_data (ctrlport_radio_resp_data), - .m_ctrlport_req_wr (m_ctrlport_radio_req_wr), - .m_ctrlport_req_rd (m_ctrlport_radio_req_rd), - .m_ctrlport_req_addr (m_ctrlport_radio_req_addr), - .m_ctrlport_req_data (m_ctrlport_radio_req_data), - .m_ctrlport_req_byte_en (m_ctrlport_radio_req_byte_en), - .m_ctrlport_req_has_time (m_ctrlport_radio_req_has_time), - .m_ctrlport_req_time (m_ctrlport_radio_req_time), - .m_ctrlport_resp_ack (m_ctrlport_radio_resp_ack), - .m_ctrlport_resp_status (m_ctrlport_radio_resp_status), - .m_ctrlport_resp_data (m_ctrlport_radio_resp_data), - .start_nco_reset (start_nco_reset), - .nco_reset_done (nco_reset_done), - .adc_reset_pulse (adc_reset_pulse), - .dac_reset_pulse (dac_reset_pulse) - ); - endmodule diff --git a/fpga/usrp3/top/x400/x4xx_core_common.v b/fpga/usrp3/top/x400/x4xx_core_common.v index 0ba0fa6cb..9920299c3 100644 --- a/fpga/usrp3/top/x400/x4xx_core_common.v +++ b/fpga/usrp3/top/x400/x4xx_core_common.v @@ -8,7 +8,8 @@ // Description: // // This module contains the common core infrastructure for RFNoC, such as the -// motherboard registers and timekeeper. +// motherboard registers and timekeeper, as well as distribution of the +// CtrlPort buses from each radio block. // // Parameters: // @@ -16,6 +17,7 @@ // CHDR_W : CHDR protocol width // RFNOC_PROTOVER : RFNoC protocol version (major in most-significant byte, // Minor is least significant byte) +// NUM_DBOARDS : Number of daughter boards to support // PCIE_PRESENT : Indicates if PCIe is present in this image // @@ -26,6 +28,7 @@ module x4xx_core_common #( parameter CHDR_CLK_RATE = 200000000, parameter CHDR_W = 64, parameter RFNOC_PROTOVER = {8'd1, 8'd0}, + parameter NUM_DBOARDS = 2, parameter PCIE_PRESENT = 0 ) ( // Clocks and resets @@ -73,8 +76,9 @@ module x4xx_core_common #( input wire [ 7:0] radio_spc, output wire [63:0] radio_time, input wire sample_rx_stb, + input wire [ 3:0] time_ignore_bits, - // GPIO to DIO board (Domain: rfnoc_ctrl_clk) + // GPIO to DIO board (Domain: radio_clk) output wire [11:0] gpio_en_a, output wire [11:0] gpio_en_b, // GPIO to DIO board (async) @@ -83,12 +87,42 @@ module x4xx_core_common #( output wire [11:0] gpio_out_a, output wire [11:0] gpio_out_b, - // GPIO to application (Domain: rfnoc_ctrl_clk) + // GPIO to application (Domain: async) output wire [11:0] gpio_in_fabric_a, output wire [11:0] gpio_in_fabric_b, input wire [11:0] gpio_out_fabric_a, input wire [11:0] gpio_out_fabric_b, + // CtrlPort Slave (from RFNoC Radio Blocks; Domain: radio_clk) + input wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_req_wr, + input wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_req_rd, + input wire [ 20*NUM_DBOARDS-1:0] s_radio_ctrlport_req_addr, + input wire [ 32*NUM_DBOARDS-1:0] s_radio_ctrlport_req_data, + input wire [ 4*NUM_DBOARDS-1:0] s_radio_ctrlport_req_byte_en, + input wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_req_has_time, + input wire [ 64*NUM_DBOARDS-1:0] s_radio_ctrlport_req_time, + output wire [ 1*NUM_DBOARDS-1:0] s_radio_ctrlport_resp_ack, + output wire [ 2*NUM_DBOARDS-1:0] s_radio_ctrlport_resp_status, + output wire [ 32*NUM_DBOARDS-1:0] s_radio_ctrlport_resp_data, + + // CtrlPort Master (to Daughter Boards, Domain: radio_clk) + output wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_wr, + output wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_rd, + output wire [ 20*NUM_DBOARDS-1:0] m_radio_ctrlport_req_addr, + output wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_req_data, + output wire [ 4*NUM_DBOARDS-1:0] m_radio_ctrlport_req_byte_en, + output wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_has_time, + output wire [ 64*NUM_DBOARDS-1:0] m_radio_ctrlport_req_time, + input wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_ack, + input wire [ 2*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_status, + input wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_data, + + // RF Reset Control + output wire start_nco_reset, + input wire nco_reset_done, + output wire adc_reset_pulse, + output wire dac_reset_pulse, + // Misc (Domain: rfnoc_ctrl_clk) input wire [31:0] qsfp_port_0_0_info, input wire [31:0] qsfp_port_0_1_info, @@ -109,10 +143,10 @@ module x4xx_core_common #( ); + `include "regmap/radio_ctrlport_regmap_utils.vh" `include "../../lib/rfnoc/core/ctrlport.vh" `include "regmap/core_regs_regmap_utils.vh" - //--------------------------------------------------------------------------- // AXI4-Lite to ctrlport //--------------------------------------------------------------------------- @@ -293,24 +327,284 @@ module x4xx_core_common #( ); + //----------------------------------------------------------------------- + // Radio CtrlPort Splitter + //----------------------------------------------------------------------- + + wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_req_wr; + wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_req_rd; + wire [ 20*NUM_DBOARDS-1:0] rf_ctrlport_req_addr; + wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_req_data; + wire [ 4*NUM_DBOARDS-1:0] rf_ctrlport_req_byte_en; + wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_req_has_time; + wire [ 64*NUM_DBOARDS-1:0] rf_ctrlport_req_time; + wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_resp_ack; + wire [ 2*NUM_DBOARDS-1:0] rf_ctrlport_resp_status; + wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_resp_data; + + wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_wr; + wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_rd; + wire [ 20*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_addr; + wire [ 32*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_data; + wire [ 4*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_byte_en; + wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_has_time; + wire [ 64*NUM_DBOARDS-1:0] dio_radio_ctrlport_req_time; + wire [ 1*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_ack; + wire [ 2*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_status; + wire [ 32*NUM_DBOARDS-1:0] dio_radio_ctrlport_resp_data; + + genvar db; + generate + for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_radio_ctrlport + + //----------------------------------------------------------------------- + // CtrlPort Splitter + //----------------------------------------------------------------------- + + // This section takes the CtrlPort master from each radio block and splits it + // into a CtrlPort bus for the associated daughter(m_radio_ctrlport_*), the + // RFDC timing control (rf_ctrlport_*) and DIO control(dio_radio_ctrlport_*). + + localparam [31:0] DIO_WINDOW_SIZE_W = $clog2(DIO_WINDOW_SIZE); + localparam [31:0] RFDC_TIMING_WINDOW_SIZE_W = $clog2(RFDC_TIMING_WINDOW_SIZE); + localparam [31:0] DB_WINDOW_SIZE_W = $clog2(DB_WINDOW_SIZE); + + ctrlport_decoder_param #( + .NUM_SLAVES (3), + .PORT_BASE ({ DIO_WINDOW[19:0], RFDC_TIMING_WINDOW[19:0], DB_WINDOW[19:0] }), + .PORT_ADDR_W ({ DIO_WINDOW_SIZE_W, RFDC_TIMING_WINDOW_SIZE_W, DB_WINDOW_SIZE_W }) + ) ctrlport_decoder_param_i ( + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), + .s_ctrlport_req_wr (s_radio_ctrlport_req_wr [ 1*db+: 1]), + .s_ctrlport_req_rd (s_radio_ctrlport_req_rd [ 1*db+: 1]), + .s_ctrlport_req_addr (s_radio_ctrlport_req_addr [20*db+:20]), + .s_ctrlport_req_data (s_radio_ctrlport_req_data [32*db+:32]), + .s_ctrlport_req_byte_en (s_radio_ctrlport_req_byte_en [ 4*db+: 4]), + .s_ctrlport_req_has_time (s_radio_ctrlport_req_has_time [ 1*db+: 1]), + .s_ctrlport_req_time (s_radio_ctrlport_req_time [64*db+:64]), + .s_ctrlport_resp_ack (s_radio_ctrlport_resp_ack [ 1*db+: 1]), + .s_ctrlport_resp_status (s_radio_ctrlport_resp_status [ 2*db+: 2]), + .s_ctrlport_resp_data (s_radio_ctrlport_resp_data [32*db+:32]), + .m_ctrlport_req_wr ({ dio_radio_ctrlport_req_wr [ 1*db+: 1], rf_ctrlport_req_wr [ 1*db+: 1], m_radio_ctrlport_req_wr [ 1*db+: 1] }), + .m_ctrlport_req_rd ({ dio_radio_ctrlport_req_rd [ 1*db+: 1], rf_ctrlport_req_rd [ 1*db+: 1], m_radio_ctrlport_req_rd [ 1*db+: 1] }), + .m_ctrlport_req_addr ({ dio_radio_ctrlport_req_addr [20*db+:20], rf_ctrlport_req_addr [20*db+:20], m_radio_ctrlport_req_addr [20*db+:20] }), + .m_ctrlport_req_data ({ dio_radio_ctrlport_req_data [32*db+:32], rf_ctrlport_req_data [32*db+:32], m_radio_ctrlport_req_data [32*db+:32] }), + .m_ctrlport_req_byte_en ({ dio_radio_ctrlport_req_byte_en [ 4*db+: 4], rf_ctrlport_req_byte_en [ 4*db+: 4], m_radio_ctrlport_req_byte_en [ 4*db+: 4] }), + .m_ctrlport_req_has_time ({ dio_radio_ctrlport_req_has_time [ 1*db+: 1], rf_ctrlport_req_has_time [ 1*db+: 1], m_radio_ctrlport_req_has_time [ 1*db+: 1] }), + .m_ctrlport_req_time ({ dio_radio_ctrlport_req_time [64*db+:64], rf_ctrlport_req_time [64*db+:64], m_radio_ctrlport_req_time [64*db+:64] }), + .m_ctrlport_resp_ack ({ dio_radio_ctrlport_resp_ack [ 1*db+: 1], rf_ctrlport_resp_ack [ 1*db+: 1], m_radio_ctrlport_resp_ack [ 1*db+: 1] }), + .m_ctrlport_resp_status ({ dio_radio_ctrlport_resp_status [ 2*db+: 2], rf_ctrlport_resp_status [ 2*db+: 2], m_radio_ctrlport_resp_status [ 2*db+: 2] }), + .m_ctrlport_resp_data ({ dio_radio_ctrlport_resp_data [32*db+:32], rf_ctrlport_resp_data [32*db+:32], m_radio_ctrlport_resp_data [32*db+:32] }) + ); + + end + endgenerate + + + //------------------------------------------------------------------------- + // RF Timing Reset Control + //------------------------------------------------------------------------- + + rfdc_timing_control #( + .NUM_DBOARDS (NUM_DBOARDS) + ) rfdc_timing_control_i ( + .clk (radio_clk), + .rst (radio_rst), + .time_now (radio_time), + .time_now_stb (sample_rx_stb), + .time_ignore_bits (time_ignore_bits), + .s_ctrlport_req_wr (rf_ctrlport_req_wr), + .s_ctrlport_req_rd (rf_ctrlport_req_rd), + .s_ctrlport_req_addr (rf_ctrlport_req_addr), + .s_ctrlport_req_data (rf_ctrlport_req_data), + .s_ctrlport_req_byte_en (rf_ctrlport_req_byte_en), + .s_ctrlport_req_has_time (rf_ctrlport_req_has_time), + .s_ctrlport_req_time (rf_ctrlport_req_time), + .s_ctrlport_resp_ack (rf_ctrlport_resp_ack), + .s_ctrlport_resp_status (rf_ctrlport_resp_status), + .s_ctrlport_resp_data (rf_ctrlport_resp_data), + .start_nco_reset (start_nco_reset), + .nco_reset_done (nco_reset_done), + .adc_reset_pulse (adc_reset_pulse), + .dac_reset_pulse (dac_reset_pulse) + ); + + //--------------------------------------------------------------------------- // DIO //--------------------------------------------------------------------------- + // + // DIO lines may be controlled via 3 different ctrlport interfaces. + // The diagram below shows how the different ctrlport interfaces are + // conditioned and combined. + // + // ________________ + // ps ctrlport | | + // ----------------------| CLK crossing |-------+ + // |(rfnoc_ctrl_clk)| | + // |________________| | + // radio 0 dio_ctrlport | _____________ + // -------------------------------------------+ +----| | + // | | Ctrlport | + // +--------| combiner |---- x4xx_dio + // radio 1 dio_ctrlport | | + // ----------------------------------------------------|_____________| + // (radio_clk) + // + // + + // MPM ctrlport signals to convert to radio_clk domain + wire mpm_dio_req_wr; + wire mpm_dio_req_rd; + wire [19:0] mpm_dio_req_addr; + wire [31:0] mpm_dio_req_data; + wire mpm_dio_resp_ack; + wire [ 1:0] mpm_dio_resp_status; + wire [31:0] mpm_dio_resp_data; + + ctrlport_clk_cross ctrlport_clk_cross_dio ( + .rst (rfnoc_ctrl_rst), + .s_ctrlport_clk (rfnoc_ctrl_clk), + .s_ctrlport_req_wr (dio_req_wr), + .s_ctrlport_req_rd (dio_req_rd), + .s_ctrlport_req_addr (dio_req_addr), + .s_ctrlport_req_portid (10'b0), + .s_ctrlport_req_rem_epid (16'b0), + .s_ctrlport_req_rem_portid (10'b0), + .s_ctrlport_req_data (dio_req_data), + .s_ctrlport_req_byte_en (4'hF), + .s_ctrlport_req_has_time (1'b0), + .s_ctrlport_req_time (64'b0), + .s_ctrlport_resp_ack (dio_resp_ack), + .s_ctrlport_resp_status (dio_resp_status), + .s_ctrlport_resp_data (dio_resp_data), + .m_ctrlport_clk (radio_clk), + .m_ctrlport_req_wr (mpm_dio_req_wr), + .m_ctrlport_req_rd (mpm_dio_req_rd), + .m_ctrlport_req_addr (mpm_dio_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (mpm_dio_req_data), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (mpm_dio_resp_ack), + .m_ctrlport_resp_status (mpm_dio_resp_status), + .m_ctrlport_resp_data (mpm_dio_resp_data) + ); + + // Since the PS ctrlport services other register endpoints + // outside the DIO register space, none of which are addressed + // through the ctrlport signals in the radio_clk domain. + // For this reason, ctrlport transactions not intended for the + // DIO register space will hang the bus if pushed into + // the ctrlport_combiner. For this reason, transactions out + // of said space will be filtered out from this clock crossed + // instance of the PS ctrlport. + + // Windowed ctrlport signals + wire windowed_mpm_dio_req_wr; + wire windowed_mpm_dio_req_rd; + wire [19:0] windowed_mpm_dio_req_addr; + wire [31:0] windowed_mpm_dio_req_data; + wire windowed_mpm_dio_resp_ack; + wire [ 1:0] windowed_mpm_dio_resp_status; + wire [31:0] windowed_mpm_dio_resp_data; + + ctrlport_window #( + .BASE_ADDRESS (DIO), + .WINDOW_SIZE (DIO_SIZE) + ) ctrlport_window_dio ( + .s_ctrlport_req_wr (mpm_dio_req_wr), + .s_ctrlport_req_rd (mpm_dio_req_rd), + .s_ctrlport_req_addr (mpm_dio_req_addr), + .s_ctrlport_req_portid (10'b0), + .s_ctrlport_req_rem_epid (16'b0), + .s_ctrlport_req_rem_portid (10'b0), + .s_ctrlport_req_data (mpm_dio_req_data), + .s_ctrlport_req_byte_en (4'hF), + .s_ctrlport_req_has_time (1'b0), + .s_ctrlport_req_time (64'b0), + .s_ctrlport_resp_ack (mpm_dio_resp_ack), + .s_ctrlport_resp_status (mpm_dio_resp_status), + .s_ctrlport_resp_data (mpm_dio_resp_data), + .m_ctrlport_req_wr (windowed_mpm_dio_req_wr), + .m_ctrlport_req_rd (windowed_mpm_dio_req_rd), + .m_ctrlport_req_addr (windowed_mpm_dio_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (windowed_mpm_dio_req_data), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (windowed_mpm_dio_resp_ack), + .m_ctrlport_resp_status (windowed_mpm_dio_resp_status), + .m_ctrlport_resp_data (windowed_mpm_dio_resp_data) + ); + // Combined ctrlport signals + wire dio_ctrlport_req_wr; + wire dio_ctrlport_req_rd; + wire [19:0] dio_ctrlport_req_addr; + wire [31:0] dio_ctrlport_req_data; + wire dio_ctrlport_resp_ack; + wire [ 1:0] dio_ctrlport_resp_status; + wire [31:0] dio_ctrlport_resp_data; + + // This combiner mixes the CtrlPort interfaces from each radio block with the + // filtered PS CtrlPort bus to allow these interfaces to interact with the + // DIO block. + ctrlport_combiner #( + .NUM_MASTERS (NUM_DBOARDS + 1), + .PRIORITY (1) + ) ctrlport_combiner_dio ( + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), + .s_ctrlport_req_wr ({dio_radio_ctrlport_req_wr, windowed_mpm_dio_req_wr}), + .s_ctrlport_req_rd ({dio_radio_ctrlport_req_rd, windowed_mpm_dio_req_rd}), + .s_ctrlport_req_addr ({dio_radio_ctrlport_req_addr, windowed_mpm_dio_req_addr}), + .s_ctrlport_req_portid ({(NUM_DBOARDS+1){10'b0}}), + .s_ctrlport_req_rem_epid ({(NUM_DBOARDS+1){16'b0}}), + .s_ctrlport_req_rem_portid ({(NUM_DBOARDS+1){10'b0}}), + .s_ctrlport_req_data ({dio_radio_ctrlport_req_data, windowed_mpm_dio_req_data}), + .s_ctrlport_req_byte_en ({(NUM_DBOARDS+1){4'hF}}), + .s_ctrlport_req_has_time ({(NUM_DBOARDS+1){1'b0}}), + .s_ctrlport_req_time ({(NUM_DBOARDS+1){64'b0}}), + .s_ctrlport_resp_ack ({dio_radio_ctrlport_resp_ack, windowed_mpm_dio_resp_ack}), + .s_ctrlport_resp_status ({dio_radio_ctrlport_resp_status, windowed_mpm_dio_resp_status}), + .s_ctrlport_resp_data ({dio_radio_ctrlport_resp_data, windowed_mpm_dio_resp_data}), + .m_ctrlport_req_wr (dio_ctrlport_req_wr), + .m_ctrlport_req_rd (dio_ctrlport_req_rd), + .m_ctrlport_req_addr (dio_ctrlport_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (dio_ctrlport_req_data), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (dio_ctrlport_resp_ack), + .m_ctrlport_resp_status (dio_ctrlport_resp_status), + .m_ctrlport_resp_data (dio_ctrlport_resp_data) + ); + x4xx_dio #( .REG_BASE (DIO), .REG_SIZE (DIO_SIZE) ) x4xx_dio_i ( - .ctrlport_clk (rfnoc_ctrl_clk), - .ctrlport_rst (rfnoc_ctrl_rst), - .s_ctrlport_req_wr (dio_req_wr), - .s_ctrlport_req_rd (dio_req_rd), - .s_ctrlport_req_addr (dio_req_addr), - .s_ctrlport_req_data (dio_req_data), - .s_ctrlport_resp_ack (dio_resp_ack), - .s_ctrlport_resp_status (dio_resp_status), - .s_ctrlport_resp_data (dio_resp_data), + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), + .s_ctrlport_req_wr (dio_ctrlport_req_wr), + .s_ctrlport_req_rd (dio_ctrlport_req_rd), + .s_ctrlport_req_addr (dio_ctrlport_req_addr), + .s_ctrlport_req_data (dio_ctrlport_req_data), + .s_ctrlport_resp_ack (dio_ctrlport_resp_ack), + .s_ctrlport_resp_status (dio_ctrlport_resp_status), + .s_ctrlport_resp_data (dio_ctrlport_resp_data), .gpio_in_a (gpio_in_a), .gpio_in_b (gpio_in_b), .gpio_out_a (gpio_out_a), @@ -330,6 +624,25 @@ endmodule //XmlParse xml_on +// +//<regmap name="RADIO_CTRLPORT_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true"> +// <group name="RADIO_CTRLPORT_WINDOWS"> +// <info>Each radio's CtrlPort peripheral interface is divided into the +// following memory spaces. Note that the CtrlPort peripheral interface +// starts at offset 0x80000 in the RFNoC Radio block's register space.</info> +// <window name="DB_WINDOW" offset="0x00000" size="0x08000"> +// <info>Daughterboard GPIO interface. Register access within this space +// is directed to the associated daughterboard CPLD.</info> +// </window> +// <window name="RFDC_TIMING_WINDOW" offset="0x08000" size="0x04000" targetregmap="RFDC_TIMING_REGMAP"> +// <info>RFDC timing control interface.</info> +// </window> +// <window name="DIO_WINDOW" offset="0x0C000" size="0x04000" targetregmap="DIO_REGMAP"> +// <info>DIO control interface</info> +// </window> +// </group> +//</regmap> +// //<regmap name="CORE_REGS_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true"> // <info> // This is the map for the registers that the CORE_REGS window has access to |