diff options
Diffstat (limited to 'fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints')
4 files changed, 60 insertions, 16 deletions
diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v index b208c020b..c3a89e887 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v @@ -38,6 +38,12 @@ module basic_regs #( //---------------------------------------------------------- reg [SCRATCH_REG_SIZE-1:0] scratch_reg = {SCRATCH_REG_SIZE {1'b0}}; +`ifdef VARIANT_XO3 + localparam VARIANT_ID = VARIANT_ID_XO3; +`else + localparam VARIANT_ID = VARIANT_ID_MAX10; +`endif + //---------------------------------------------------------- // Handling of CtrlPort //---------------------------------------------------------- @@ -105,7 +111,6 @@ module basic_regs #( s_ctrlport_resp_data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg; end - BASE_ADDRESS + GIT_HASH_REGISTER: begin `ifdef GIT_HASH s_ctrlport_resp_data <= `GIT_HASH; @@ -114,6 +119,11 @@ module basic_regs #( `endif end + BASE_ADDRESS + SLAVE_VARIANT: begin + s_ctrlport_resp_data[VARIANT_REG_MSB : VARIANT_REG] + <= VARIANT_ID[VARIANT_REG_SIZE-1:0]; + end + // error on undefined address default: begin s_ctrlport_resp_data <= {32{1'b0}}; @@ -150,8 +160,10 @@ endmodule // This enum is used to create the constants held in the basic registers in both verilog and vhdl. // </info> // <value name="BOARD_ID_VALUE" integer="0x4002"/> -// <value name="CPLD_REVISION" integer="0x21111614"/> +// <value name="CPLD_REVISION" integer="0x22031611"/> // <value name="OLDEST_CPLD_REVISION" integer="0x20110611"/> +// <value name="VARIANT_ID_XO3" integer="0x584F33"/> +// <value name="VARIANT_ID_MAX10" integer="0x4D4158"/> // </enumeratedtype> // // <register name="SLAVE_SIGNATURE" size="32" offset="0x00" attributes="Readable"> @@ -214,6 +226,19 @@ endmodule // <info>7 hex digit hash code of the commit</info> // </bitfield> // </register> +// +// <register name="SLAVE_VARIANT" size="32" offset="0x14" writable="false"> +// <info> +// Contains information pertaining the variant of the programmable. +// </info> +// <bitfield name="VARIANT_REG" range="31..0" initialvalue="0"> +// <info> +// Returns the variant of the programmable based on the part vendor. +// MAX10 variants return 0x583033(ASCII for MAX), while the XO3 variant +// returns 0x584F33 (ASCII for XO3) +// </info> +// </bitfield> +// </register> // </group> //</regmap> //XmlParse xml_off diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v index abc4b62f9..a84625d63 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v @@ -369,10 +369,16 @@ module dsa_control #( wire [31:0] ram_tx0_dia = select_gain_table ? table_tx0_doa : ram_datain; wire [31:0] ram_tx1_dia = select_gain_table ? table_tx1_doa : ram_datain; +`ifdef VARIANT_XO3 + localparam RAM_RW_MODE = "B-READ-ONLY" ; +`else + localparam RAM_RW_MODE = "READ-FIRST" ; +`endif + ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") @@ -394,7 +400,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") @@ -416,7 +422,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") @@ -438,7 +444,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") @@ -464,7 +470,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") @@ -486,7 +492,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex") @@ -508,7 +514,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") @@ -530,7 +536,7 @@ module dsa_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex") diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v index 5663d348e..f32b09296 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v @@ -163,10 +163,17 @@ module led_control #( ch1_rx_led <= ram_ch1_dob[CH1_TRX1_LED_EN + 0]; end +`ifdef VARIANT_XO3 + localparam RAM_RW_MODE = "B-READ-ONLY" ; +`else + localparam RAM_RW_MODE = "READ-FIRST" ; +`endif + + ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("") @@ -188,7 +195,7 @@ module led_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("") diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v index 63ce251b3..5b5290b18 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v @@ -370,10 +370,16 @@ module switch_control #( rx1_switch_11_reg <= ram_rx1_dob[RX_SWITCH_11_MSB: RX_SWITCH_11]; end +`ifdef VARIANT_XO3 + localparam RAM_RW_MODE = "B-READ-ONLY" ; +`else + localparam RAM_RW_MODE = "READ-FIRST" ; +`endif + ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx0_path_defaults.hex") @@ -394,7 +400,7 @@ module switch_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/tx1_path_defaults.hex") @@ -415,7 +421,7 @@ module switch_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx0_path_defaults.hex") @@ -436,7 +442,7 @@ module switch_control #( ram_2port #( .DWIDTH (32), .AWIDTH (8), - .RW_MODE ("READ-FIRST"), + .RW_MODE (RAM_RW_MODE), .RAM_TYPE ("AUTOMATIC"), .OUT_REG (0), .INIT_FILE ("register_endpoints/memory_init_files/rx1_path_defaults.hex") |