diff options
Diffstat (limited to 'fpga/usrp3/top/x300')
| -rw-r--r-- | fpga/usrp3/top/x300/bus_int.v | 12 | ||||
| -rw-r--r-- | fpga/usrp3/top/x300/capture_ddrlvds.v | 28 | ||||
| -rwxr-xr-x | fpga/usrp3/top/x300/coregen/bootram.coe | 6952 | ||||
| -rw-r--r-- | fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v | 56 | ||||
| -rw-r--r-- | fpga/usrp3/top/x300/x300.v | 52 | ||||
| -rw-r--r-- | fpga/usrp3/top/x300/x300_core.v | 79 |
6 files changed, 3600 insertions, 3579 deletions
diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v index 17c708f66..aa5998bd3 100644 --- a/fpga/usrp3/top/x300/bus_int.v +++ b/fpga/usrp3/top/x300/bus_int.v @@ -43,8 +43,8 @@ module bus_int inout SFPP1_RS0, inout SFPP1_RS1, // - input [3:0] clock_status, - output [5:0] clock_control, + input [4:0] clock_status, + output [6:0] clock_control, // ETH0 output [63:0] eth0_tx_tdata, output [3:0] eth0_tx_tuser, output eth0_tx_tlast, output eth0_tx_tvalid, input eth0_tx_tready, input [63:0] eth0_rx_tdata, input [3:0] eth0_rx_tuser, input eth0_rx_tlast, input eth0_rx_tvalid, output eth0_rx_tready, @@ -141,7 +141,7 @@ module bus_int localparam RB_BIST = 8'd128; - localparam COMPAT_MAJOR = 16'h0003; + localparam COMPAT_MAJOR = 16'h0004; localparam COMPAT_MINOR = 16'h0000; wire [31:0] set_data; @@ -295,8 +295,8 @@ module bus_int .strobe(set_stb), .addr(set_addr), .in(set_data), .out(sw_rst)); - setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(6), - .at_reset(6'b100000) //bit 5 high means GPSDO on by default + setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(7), + .at_reset(7'b1000000) //bit 6 high means GPSDO on by default ) set_clk_ctrl (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), @@ -341,7 +341,7 @@ module bus_int RB_COUNTER: rb_data = counter; RB_SPI_RDY: rb_data = {31'b0, spi_ready}; RB_SPI_DATA: rb_data = rb_spi_data; - RB_CLK_STATUS: rb_data = {28'b0, clock_status}; + RB_CLK_STATUS: rb_data = {27'b0, clock_status}; // SFPP Interface pins. RB_SFPP_STATUS0: rb_data = {26'b0,SFPP0_ModAbs_chgd,SFPP0_TxFault_chgd,SFPP0_RxLOS_chgd, SFPP0_ModAbs_reg2,SFPP0_TxFault_reg2,SFPP0_RxLOS_reg2}; diff --git a/fpga/usrp3/top/x300/capture_ddrlvds.v b/fpga/usrp3/top/x300/capture_ddrlvds.v index c33f78339..193caf6e1 100644 --- a/fpga/usrp3/top/x300/capture_ddrlvds.v +++ b/fpga/usrp3/top/x300/capture_ddrlvds.v @@ -7,7 +7,7 @@ module capture_ddrlvds #(parameter WIDTH=7, - parameter B250=0) + parameter X300=0) (input clk, input reset, input ssclk_p, @@ -20,15 +20,15 @@ module capture_ddrlvds wire ssclk; wire [(2*WIDTH)-1:0] out_pre1; wire ssclk_bufio1, ssclk_bufio2, ssclk_bufr, ssclk_bufmr; - - IBUFGDS #(.DIFF_TERM("TRUE")) + + IBUFGDS #(.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); BUFMR clkbufmr ( .I(ssclk), .O(ssclk_bufmr) ); - + BUFIO clkbufio1 ( .I(ssclk_bufmr), .O(ssclk_bufio1) @@ -37,22 +37,22 @@ module capture_ddrlvds .I(ssclk_bufmr), .O(ssclk_bufio2) ); - - BUFR + + BUFR #(.SIM_DEVICE("7SERIES"), .BUFR_DIVIDE("BYPASS")) clkbufr ( .I(ssclk_bufmr), .O(ssclk_bufr) ); - + genvar i; - + generate for(i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins - if ((i == 10) && (B250 == 1)) begin + if ((i == 10) && (X300 == 1)) begin IBUFDS #(.DIFF_TERM("FALSE")) ibufds (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) iddr @@ -68,12 +68,12 @@ module capture_ddrlvds end endgenerate - - + + reg rd_en; wire full, empty, almost_empty; - - + + input_sample_fifo input_sample_fifo_i ( .rst(reset), // input rst @@ -88,7 +88,7 @@ module capture_ddrlvds .almost_empty(almost_empty) // output almost_empty ); - + always @(posedge clk) begin if (reset) rd_en <= 0; diff --git a/fpga/usrp3/top/x300/coregen/bootram.coe b/fpga/usrp3/top/x300/coregen/bootram.coe index 075e91f39..c9045183a 100755 --- a/fpga/usrp3/top/x300/coregen/bootram.coe +++ b/fpga/usrp3/top/x300/coregen/bootram.coe @@ -2,15 +2,15 @@ memory_initialization_radix=16; memory_initialization_vector= 0b0b0b0b, 82700b0b, -8187b00c, +81978c0c, 3a0b0b80, -f28f0400, +ff8c0400, 00000000, 00000000, 00000000, 80088408, 88080b0b, -80f2da2d, +80ffd72d, 880c840c, 800c0400, 00000000, @@ -161,8 +161,8 @@ c4040000, 00000000, 00000000, 71fc0608, -0b0b8187, -9c738306, +0b0b8196, +f8738306, 10100508, 060b0b0b, 88aa0400, @@ -170,16 +170,16 @@ c4040000, 00000000, 80088408, 88087575, -0b0b80e9, -b42d5050, +0b0b80f6, +b12d5050, 80085688, 0c840c80, 0c510400, 00000000, 80088408, 88087575, -0b0b80ea, -e62d5050, +0b0b80f7, +e32d5050, 80085688, 0c840c80, 0c510400, @@ -209,7 +209,7 @@ e62d5050, 00000000, 00000000, 810b0b0b, -8187ac0c, +8197880c, 51040000, 00000000, 00000000, @@ -257,7 +257,7 @@ e62d5050, 00000000, 00000000, 82813f80, -ebfb3f04, +f8f83f04, 10101010, 10101010, 10101010, @@ -280,56 +280,56 @@ fc060c51, 0a100a53, 72ed3851, 51535104, -8187ac08, +81978808, 802ea438, -8187b008, +81978c08, 822ebd38, 8380800b, -0b0b818f, -a40c82a0, -800b818f, -a80c8290, -800b818f, -ac0c04f8, +0b0b819f, +800c82a0, +800b819f, +840c8290, +800b819f, +880c04f8, 808080a4, 0b0b0b81, -8fa40cf8, +9f800cf8, 80808280, -0b818fa8, +0b819f84, 0cf88080, 84800b81, -8fac0c04, +9f880c04, 80c0a880, 8c0b0b0b, -818fa40c, +819f800c, 80c0a880, -940b818f, -a80c0b0b, -80f4b00b, -818fac0c, +940b819f, +840c0b0b, +8181ac0b, +819f880c, 04ff3d0d, -818fb033, +819f8c33, 5170a738, -8187b808, +81979408, 70085252, 70802e94, 38841281, -87b80c70, -2d8187b8, +97940c70, +2d819794, 08700852, 5270ee38, -810b818f, -b034833d, +810b819f, +8c34833d, 0d040480, 3d0d0b0b, -818fa008, +819efc08, 802e8e38, 0b0b0b0b, 800b802e, 09810685, 38823d0d, 040b0b81, -8fa0510b, +9efc510b, 0b0bf5d4, 3f823d0d, 0404f93d, @@ -357,57 +357,57 @@ b1387218, 04e23d0d, 8bef5283, fa805198, -823f8bef, +c43f8bef, 5283f280, -5197f83f, +5198ba3f, 8b885280, -51a2a73f, -81af5280, -f4b851a2, -a83f80d3, +51a2e93f, +81af5281, +81b451a2, +ea3f80d3, b993c052, 83fc8051, -989e3f80, +98e03f80, d3b993c0, 5283fe80, -5198913f, +5198d33f, 80d3b993, c05283f8, -80519884, +805198c6, 3f810b82, c0840c82, c0900855, 8a567481, 2e833881, -56755280, -f4e451a1, -e43f82c0, +56755281, +81e051a2, +a63f82c0, 9408558a, 5674812e, 83388156, -755280f4, -fc51a1cd, +75528181, +f851a28f, 3fbffc53, 82808052, -818fb451, -a2e43f81, -8fb40852, -80f59451, -a1b33f81, -8fb451a7, -a83f80da, -843f8d3d, +819f9051, +a3a63f81, +9f900852, +81829051, +a1f53f81, +9f9051a7, +f03f80e7, +813f8d3d, 5b80cc53, -8187bc52, -7a5180e1, -e33f8254, -80f4b453, +81979852, +7a5180ee, +e03f8254, +8181b053, 80d05283, -fe805198, -d53f80cc, +fe805199, +973f80cc, 547a5380, d05283fe, -805197ad, +805197ef, 3f82c090, 08558257, 74833874, @@ -415,36 +415,36 @@ d05283fe, 0855835c, 74833881, 5c865381, -87c452a0, +97a052a0, 3dffbc05, 51fdab3f, 80085686, -538187cc, +538197a8, 52a03dc4, 0551fd9a, 3f800858, 84537682, -2b8187e8, +2b8197c4, 1153701c, ac115358, 55fd833f, 80085a84, -538187d8, +538197b4, 15529c17, 51fcf33f, 80085984, 537b822b, -8187e811, +8197c411, 53701cac, 11535855, fcdc3f80, 085b8453, -8187d815, +8197b415, 529c1751, fccc3f80, 0879557a, 54765357, -8051a681, +8051a6c9, 3f841633, 85173371, 882b0783, @@ -464,7 +464,7 @@ d00c9e80, 0b82c1d4, 0c76547a, 53775281, -51a5b23f, +51a5fa3f, 84183385, 19337188, 2b07831a, @@ -484,241 +484,243 @@ c2840c60, 82c2940c, 800b82c0, 840c80e4, -51bccb3f, -82c09008, -5574812e, -09810686, -388051b6, -903f82c0, -94085574, -812e0981, -06863874, -51b5fe3f, -805580e9, -397451a2, -e03f8008, -5180c9eb, -3f800853, -745280f5, -a8519e85, -3f7451a2, -b33f8008, -5180c9f9, -3f800853, -745280f5, -bc519ded, -3f7451a4, -bf3f8008, -5180c9e1, -3f800853, -745280f5, -d0519dd5, -3f7451a4, -bc3f8008, -5180c9c9, -3f800853, -745280f5, -e4519dbd, -3f811570, -81ff0651, -55b3a13f, -80087524, -ff8f38a0, -3d0d04f5, -3d0d7e60, -028805b7, -05337154, -5b5b54a1, -f43f8008, -58a85578, -802e8338, -b8557390, -2a7081ff, -06705575, -5480f5f8, -5351579c, -f43f7851, -a1b73f74, -822b82c0, -80118008, -33800881, -05337188, -2b07720c, -82c08413, -80088205, -33800883, -05337198, -2b71902b, -07800884, -05337088, -2b720780, -08850533, -7107760c, -5282c088, -18615a55, -535a4152, -525d5755, -a0d23f80, -0808760c, -82c08c15, -02840580, -c6052271, -0c5482c0, -90157771, -0c5482c0, -94157a08, -710c5682, -c0981502, -840580c2, -05227933, -71902b71, -882b0781, -1c337107, -740c5282, -c09c1882, -1c33831d, -3371982b, -71902b07, -841f3370, +5180c9c7, +3f82c090, +08557481, +2e098106, +86388051, +b6e23f82, +c0940855, +74812e09, +81068638, +7451b6d0, +3f805580, +e9397451, +a3a53f80, +085180d6, +e73f8008, +53745281, +82a4519e, +c63f7451, +a2f83f80, +085180d6, +f53f8008, +53745281, +82b8519e, +ae3f7451, +a5873f80, +085180d6, +dd3f8008, +53745281, +82cc519e, +963f7451, +a5843f80, +085180d6, +c53f8008, +53745281, +82e0519d, +fe3f8115, +7081ff06, +5155b3f3, +3f800875, +24ff8f38, +a03d0d04, +f53d0d7e, +60028805, +b7053371, +545b5b54, +a2b93f80, +0858a855, +78802e83, +38b85573, +902a7081, +ff067055, +75548182, +f4535157, +9db53f78, +51a1fc3f, +74822b82, +c0801180, +08338008, +81053371, +882b0772, +0c82c084, +13800882, +05338008, +83053371, +982b7190, +2b078008, +84053370, 882b7207, -60850533, -7107760c, -52555555, -40585955, -568d3d0d, -04fb3d0d, -7c567580, -2e9d3884, -16080284, -05ae0522, -56028405, -aa052255, -79545202, -9f053351, -fde53f87, -3d0d04f2, -3d0d655a, -79802e81, -b0388c3d, -5b905379, -527a5180, -dbba3f66, -8f268838, -7b82075c, -80f23979, -08832a70, -81065157, -76802eab, -38881a08, -70942a70, -81065158, -5876802e, -97388280, -80548053, -903dfc05, -5277bfff, -ff0651b9, -c43f8439, -77085f79, -08822a70, -81065157, -76802eac, -38881a08, -70942a70, -81068c1d, -085c5158, -5876802e, -94388280, -80548053, -785277bf, -ffff0651, -b8a63f84, -3978780c, -79088106, +80088505, +33710776, +0c5282c0, +8818615a, +55535a41, +52525d57, +55a1973f, +80080876, +0c82c08c, +15028405, +80c60522, +710c5482, +c0901577, +710c5482, +c094157a, +08710c56, +82c09815, +02840580, +c2052279, +3371902b, +71882b07, +811c3371, +07740c52, +82c09c18, +821c3383, +1d337198, +2b71902b, +07841f33, +70882b72, +07608505, +33710776, +0c525555, +55405859, +55568d3d, +0d04fb3d, +0d7c5675, +802e9d38, +84160802, +8405ae05, +22560284, +05aa0522, +55795452, +029f0533, +51fde53f, +873d0d04, +f23d0d65, +5a79802e, +81b2388c, +3d5b9053, +79527a51, +80e8b63f, +668f2688, +387b8207, +5c80f439, +7908832a, +70810651, 5776802e, -9c389056, -7a550280, -ce052254, -0280d205, -22536152, -0280c305, -3351a7be, -3f903d0d, -048c0802, -8c0cf03d, -0d8c089c, -05080284, -058c08f8, -050c8c08, -ec050c80, -0b8c08fc, -050c8c08, -ec050880, -2e86cc38, -8c08a005, -088f268b, -38820b8c, -08fc050c, -8681398c, -08ec0508, -0870822a, +ac38881a, +0870942a, 70810651, -8c08d405, -0c8c08d8, -050c8c08, -d4050880, -2e9038bb, -fa3f8008, +58587680, +2e983882, +80805480, +53903dfc, +055277bf, +ffff0651, +80c6bf3f, +84397708, +5f790882, +2a708106, +51577680, +2ead3888, +1a087094, +2a708106, +8c1d085c, +51585876, +802e9538, +82808054, +80537852, +77bfffff, +065180c5, +a03f8439, +78780c79, +08810657, +76802e9c, +3890567a, +550280ce, +05225402, +80d20522, +53615202, +80c30533, +51a88e3f, +903d0d04, +8c08028c, +0cf03d0d, +8c089c05, +08028405, +8c08f805, +0c8c08ec, +050c800b, +8c08fc05, +0c8c08ec, +0508802e, +86d3388c, +08a00508, +8f268b38, +820b8c08, +fc050c86, +88398c08, +ec050808, +70822a70, +8106518c, +08d4050c, +8c08d805, +0c8c08d4, +0508802e, +913880c8, +f33f8008, 81068c08, dc050c85, -bf398c08, +c5398c08, d8050883, 2a708106, 518c08d4, 050c8c08, d4050880, -2e8738be, -883f85b3, -398c08d8, -0508862a, -70810651, +2e883880, +cb803f85, +b8398c08, +d8050886, +2a708106, +518c08d4, +050c8c08, +d4050880, +2e883880, +ccfd3f85, +98398c08, +d8050887, +2a708106, +518c08d4, +050c8c08, +d4050880, +2e9c3880, +ccf23f80, +0881ff06, 8c08d405, 0c8c08d4, -0508802e, -883880c0, -853f8593, -398c08d8, -0508872a, +0508822e, +84e73884, +d8398c08, +ec050884, +05085180, +cac53f80, +0881068c, +08dc050c, +8c08dc05, +08802e88, +38810b8c, +08dc050c, +8c08ec05, +0808842a, 70810651, 8c08d405, 0c8c08d4, 0508802e, -9b38bffb, -3f800881, -ff068c08, -d4050c8c, -08d40508, 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+0851a33f, +7281b9c0, +0cff89a0, +3fff88bc, +3f8197e8, +528151ff, +9cc13f80, +0851873f, +00ff3900, +ff39f73d, +0d7b8197, +ec0882c8, +11085a54, +5a77802e, +80da3881, +88188419, +08ff0581, +712b5955, +59807424, +80ea3880, +7424b538, +73822b78, +11880556, +56818019, +08770653, +72802eb6, +38781670, +08535379, +51740853, 722dff14, fc17fc17, 79812c5a, 57575473, -8025ffa8, -38d13980, -57ff9339, -7251bc13, -0853722d, -7951fed7, -3fff3d0d, -818f940b, -fc057008, -525270ff, -2e913870, -2dfc1270, +8025d638, +77085877, +ffad3881, +97ec0853, +bc1308a5, +387951ff, +833f7408, +53722dff, +14fc17fc, +1779812c, +5a575754, +738025ff, +a838d139, +8057ff93, +397251bc, +13085372, +2d7951fe, +d73fff3d, +0d819ef0, +0bfc0570, 08525270, -ff2e0981, -06f13883, -3d0d0404, -ff95a23f, -04000000, +ff2e9138, +702dfc12, +70085252, +70ff2e09, +8106f138, +833d0d04, +04ff88a5, +3f040000, 00000040, 00000000, 58333030, @@ -3875,129 +4290,6 @@ ff95a23f, 4f444142, 533a2025, 640a0000, -44454255, -473a2065, -74682531, -64205258, -4c4f5320, -6368616e, -67656420, -73746174, -653a2025, -640a0000, -44454255, -473a2065, -74682531, -64205458, -4641554c, -54206368, -616e6765, -64207374, -6174653a, -2025640a, -00000000, -44454255, -473a2065, -74682531, -64204d4f, -44414253, -20636861, -6e676564, -20737461, -74653a20, -25640a00, -494e464f, -3a20416e, -20534650, -2b206d6f, -64756c65, -20686173, -20626565, -6e207265, -6d6f7665, -64206672, -6f6d2065, -74682070, -6f727420, -25642e0a, -00000000, -494e464f, -3a204120, -6e657720, -5346502b, -206d6f64, -756c6520, -68617320, -6265656e, -20696e73, -65727465, -6420696e, -746f2065, -74682070, -6f727420, -25642e0a, -00000000, -44454255, -473a2053, -4646505f, -54595045, -5f53522e, -0a000000, -44454255, -473a2053, -4646505f, -54595045, -5f4c522e, -0a000000, -44454255, -473a2053, -4646505f, -54595045, -5f4c524d, -2e0a0000, -44454255, -473a2053, -4646505f, -54595045, -5f313030, -30424153, -455f5358, -2e0a0000, -44454255, -473a2053, -4646505f, -54595045, -5f313030, -30424153, -455f4c58, -2e0a0000, -44454255, -473a2053, -4646505f, -54595045, -5f313030, -30424153, -455f542e, -0a000000, -44454255, -473a2049, -32432065, -72726f72, -20696e20, -53465050, -5f545950, -452e0a00, -44454255, -473a2054, -77696e41, -782e0a00, -44454255, -473a2055, -6e6b6e6f, -776e2053, -46502b20, -74797065, -2e0a0000, 44657669, 63653a20, 00000000, @@ -4316,6 +4608,217 @@ ff95a23f, 2076616c, 75653a20, 00000000, +44454255, +473a2065, +74682531, +64205258, +4c4f5320, +6368616e, +67656420, +73746174, +653a2025, +640a0000, +44454255, +473a2065, +74682531, +64205458, +4641554c, +54206368, +616e6765, +64207374, +6174653a, +2025640a, +00000000, +44454255, +473a2065, +74682531, +64204d4f, +44414253, +20636861, +6e676564, +20737461, +74653a20, +25640a00, +494e464f, +3a20416e, +20534650, +2b206d6f, +64756c65, +20686173, +20626565, +6e207265, +6d6f7665, +64206672, +6f6d2065, +74682070, +6f727420, +25642e0a, +00000000, +494e464f, +3a204120, +6e657720, +5346502b, +206d6f64, +756c6520, +68617320, +6265656e, +20696e73, +65727465, +6420696e, +746f2065, +74682070, +6f727420, +25642e0a, +00000000, +44454255, +473a2053, +4646505f, +54595045, +5f53522e, +0a000000, +44454255, +473a2053, +4646505f, +54595045, +5f4c522e, +0a000000, +44454255, +473a2053, +4646505f, +54595045, +5f4c524d, +2e0a0000, +44454255, +473a2053, +4646505f, +54595045, +5f313030, +30424153, +455f5358, +2e0a0000, +44454255, +473a2053, +4646505f, +54595045, +5f313030, +30424153, +455f4c58, +2e0a0000, +44454255, +473a2053, +4646505f, +54595045, +5f313030, +30424153, +455f542e, +0a000000, +44454255, +473a2049, +32432065, +72726f72, +20696e20, +53465050, +5f545950, +452e0a00, +44454255, +473a2054, +77696e41, +782e0a00, +44454255, +473a2055, +6e6b6e6f, +776e2053, +46502b20, +74797065, +2e0a0000, +000024aa, +000024b1, +000024a4, +000024a4, +000024a4, +000024a4, +000024b1, +000024b1, +000024b1, +000024b1, +000024b1, +0000249e, +000024b1, +000024b1, +00002498, +00002492, +000025ed, +000025e7, +000025e1, +000025db, +000025d5, +000025cf, +000025c9, +000025c3, +000026f4, +00002909, +00002909, +00002909, +000026ed, +000026e6, +000026df, +000026d8, +000026d1, +000026ca, +000026c3, +000026bc, +000026b5, +000026ae, +000026a7, +000026a0, +0000283f, +00002831, +00002823, +00002815, +00002806, +000027f6, +000027e6, +000027d6, +000027c6, +000027b6, +000027af, +000027a8, +00002798, +00002788, +0000284e, +00002771, +000028ad, +000028a7, +000028a1, +0000289b, +00002900, +00002900, +00002900, +00002900, +00002900, +00002900, +00002900, +00002895, +0000288f, +00000000, +00000001, +00000004, +00000005, +00000006, +00000007, +00000008, +00000020, +00000021, +00000000, +00000001, +00000004, +00000005, +00000006, +00000007, +00000008, +0000000a, +0000000b, +0000ffff, 30313233, 34353637, 38394142, @@ -4334,7 +4837,7 @@ ffffff00, 00000000, 00000000, 00000000, -0000479c, +00004f78, 00000000, 00000000, 0050c285, @@ -4355,12 +4858,12 @@ c0a82802, 00000000, 00000000, 00006000, -0000438c, -00004414, +00004b68, +00004bf0, 00000000, -0000467c, -000046d8, -00004734, +00004e58, +00004eb4, +00004f10, 00000000, 00000000, 00000000, @@ -4370,7 +4873,7 @@ c0a82802, 00000000, 00000000, 00000000, -00004398, +00004b74, 00000000, 00000000, 00000000, @@ -7688,507 +8191,4 @@ ffffffff, 00000000, 00000000, 00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, 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-00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, 00000000;
\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v index bf430b9ea..446fb035b 100644 --- a/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v +++ b/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v @@ -4,13 +4,13 @@ //----------------------------------------------------------------------------- // File : ten_gig_eth_pcs_pma_example_design.v //----------------------------------------------------------------------------- -// Description: This file is a wrapper for the 10GBASE-R core; it contains all +// Description: This file is a wrapper for the 10GBASE-R core; it contains all // of the clock buffers required for implementing the block level //----------------------------------------------------------------------------- // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and +// of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // @@ -62,7 +62,7 @@ module ten_gig_eth_pcs_pma_x300_top // input refclk_p, // input refclk_n, input refclk156, - input refclk156_buf, + input refclk156_buf, output clk156, input reset, input [63 : 0] xgmii_txd, @@ -87,37 +87,37 @@ module ten_gig_eth_pcs_pma_x300_top // Signal declarations wire clk156; - + // Sync the global reset to the relevant clocks reg core_reset_tx; reg core_reset_rx; reg txreset322; reg rxreset322; reg dclk_reset; - + reg core_reset_tx_tmp; reg core_reset_rx_tmp; reg txreset322_tmp; reg rxreset322_tmp; reg dclk_reset_tmp; - + (* KEEP = "true" *) wire txclk322; wire rxclk322; wire dclk; - + wire tx_resetdone_int; wire rx_resetdone_int; reg [63:0] xgmii_txd_reg; reg [7:0] xgmii_txc_reg; wire [63:0] xgmii_rxd_int; wire [7:0] xgmii_rxc_int; - + wire mdio_out_int; wire mdio_tri_int; assign resetdone = tx_resetdone_int && rx_resetdone_int; - + //synthesis attribute async_reg of core_reset_tx_tmp is "true"; //synthesis attribute async_reg of core_reset_tx is "true"; //synthesis attribute async_reg of core_reset_rx_tmp is "true"; @@ -135,19 +135,19 @@ module ten_gig_eth_pcs_pma_x300_top begin // Hold core in reset until everything else is ready... // IJB. Per AR# 53443 changed these lines: -// core_reset_tx_tmp <= (!(tx_resetdone_int) || reset || +// core_reset_tx_tmp <= (!(tx_resetdone_int) || reset || // tx_fault || !(signal_detect) ); core_reset_tx_tmp <= (!(tx_resetdone_int) || reset); - + core_reset_tx <= core_reset_tx_tmp; -// core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || +// core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || // tx_fault || !(signal_detect) ); core_reset_rx_tmp <= (!(rx_resetdone_int) || reset || !(signal_detect)); - + core_reset_rx <= core_reset_rx_tmp; end - end - + end + //synthesis attribute async_reg of txreset322_tmp is "true"; //synthesis attribute async_reg of txreset322 is "true"; always @(posedge reset or posedge txclk322) @@ -163,7 +163,7 @@ module ten_gig_eth_pcs_pma_x300_top txreset322 <= txreset322_tmp; end end - + //synthesis attribute async_reg of rxreset322_tmp is "true"; //synthesis attribute async_reg of rxreset322 is "true"; always @(posedge reset or posedge rxclk322) @@ -179,7 +179,7 @@ module ten_gig_eth_pcs_pma_x300_top rxreset322 <= rxreset322_tmp; end end - + //synthesis attribute async_reg of dclk_reset_tmp is "true"; //synthesis attribute async_reg of dclk_reset is "true"; always @(posedge reset or posedge dclk) @@ -194,28 +194,28 @@ module ten_gig_eth_pcs_pma_x300_top dclk_reset_tmp <= core_reset_rx; dclk_reset <= dclk_reset_tmp; end - end - + end + // Add a pipeline to the xmgii_tx inputs, to aid timing closure always @(posedge clk156) begin - xgmii_txd_reg <= xgmii_txd; - xgmii_txc_reg <= xgmii_txc; + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; end // Add a pipeline to the xmgii_rx outputs, to aid timing closure always @(posedge clk156) begin - xgmii_rxd <= xgmii_rxd_int; - xgmii_rxc <= xgmii_rxc_int; + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; end // Add a pipeline to the mdio outputs, to aid timing closure // This is safe because the mdio clock is running so slowly always @(posedge clk156) begin - mdio_out <= mdio_out_int; - mdio_tri <= mdio_tri_int; + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; end // Instantiate the 10GBASE-R Block Level @@ -256,10 +256,10 @@ module ten_gig_eth_pcs_pma_x300_top .signal_detect(signal_detect), .tx_fault(tx_fault), .tx_disable(tx_disable)); - + // assign core_clk156_out = clk156; - - // Not needed in B250 + + // Not needed in X300 /* -----\/----- EXCLUDED -----\/----- ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) rx_clk_ddr( diff --git a/fpga/usrp3/top/x300/x300.v b/fpga/usrp3/top/x300/x300.v index aa77d1bc7..10409c607 100644 --- a/fpga/usrp3/top/x300/x300.v +++ b/fpga/usrp3/top/x300/x300.v @@ -314,13 +314,13 @@ module x300 ////////////////////////////////////////////////////////////////////// // CPRI Clock output -- this is the dirty recovered clock from the MGT // This goes to the LMK04816 which locks to it and cleans it up - // We get the clean versions back as CPRI_CLK (for the CPRI MGT) + // We get the clean versions back as CPRI_CLK (for the CPRI MGT) // and FPGA_CLK (for our main rfclk) ////////////////////////////////////////////////////////////////////// wire cpri_clk_out = 1'b0; // FIXME - connect to CPRI clock recovery when implemented OBUFDS OBUFDS_cpri (.I(cpri_clk_out), .O(CPRI_CLK_OUT_P), .OB(CPRI_CLK_OUT_N)); - + ///////////////////////////////////////////////////////////////////// // // power-on-reset logic. @@ -365,7 +365,7 @@ module x300 // after programming the AD9610. // //////////////////////////////////////////////////////////////////// - + reset_sync radio_reset_sync ( .clk(radio_clk), @@ -381,8 +381,40 @@ module x300 ); //////////////////////////////////////////////////////////////////// + // PPS + // Support for internal, external, and GPSDO PPS inputs + // Every attempt to minimize propagation between the external PPS + // input and outputs to support daisy-chaining the signal. + //////////////////////////////////////////////////////////////////// + + // Generate an internal PPS signal with a 25% duty cycle + reg [31:0] pps_count; + wire int_pps = (pps_count < 32'd2500000); + always @(posedge ref_clk_10mhz) begin + if (pps_count >= 32'd9999999) + pps_count <= 32'b0; + else + pps_count <= pps_count + 1'b1; + end + + // PPS MUX - selects internal, external, or gpsdo PPS + reg pps; + wire [1:0] pps_select; + wire pps_out_enb; + always @(*) begin + case(pps_select) + 2'b00 : pps = EXT_PPS_IN; + 2'b01 : pps = 1'b0; + 2'b10 : pps = int_pps; + 2'b11 : pps = GPS_PPS_OUT; + default: pps = 1'b0; + endcase + end + + // PPS out and LED + assign EXT_PPS_OUT = pps & pps_out_enb; + assign LED_PPS = ~pps; // active low LED driver - assign LED_PPS = ~(GPS_PPS_OUT | EXT_PPS_IN); assign LED_GPSLOCK = ~GPS_LOCK_OK; assign LED_REFLOCK = ~LMK_Lock; assign {LED_RX1_RX,LED_TXRX1_TX,LED_TXRX1_RX} = ~led0; // active low LED driver @@ -451,7 +483,7 @@ module x300 // Analog diff pairs on I side of ADC are inverted for layout reasons, but data diff pairs are all swapped as well // so I gets a double negative, and is unchanged. Q must be inverted. - capture_ddrlvds #(.WIDTH(14),.B250(1)) cap_db0 + capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db0 (.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB0_ADC_DCLK_P), .ssclk_n(DB0_ADC_DCLK_N), .in_p({{DB0_ADC_DA6_P, DB0_ADC_DA5_P, DB0_ADC_DA4_P, DB0_ADC_DA3_P, DB0_ADC_DA2_P, DB0_ADC_DA1_P, DB0_ADC_DA0_P}, {DB0_ADC_DB6_P, DB0_ADC_DB5_P, DB0_ADC_DB4_P, DB0_ADC_DB3_P, DB0_ADC_DB2_P, DB0_ADC_DB1_P, DB0_ADC_DB0_P}}), @@ -461,7 +493,7 @@ module x300 .out({rx0_i,rx0_q_inv})); assign rx0[31:0] = { rx0_i, 2'b00, ~rx0_q_inv, 2'b00 }; - capture_ddrlvds #(.WIDTH(14),.B250(1)) cap_db1 + capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db1 (.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB1_ADC_DCLK_P), .ssclk_n(DB1_ADC_DCLK_N), .in_p({{DB1_ADC_DA6_P, DB1_ADC_DA5_P, DB1_ADC_DA4_P, DB1_ADC_DA3_P, DB1_ADC_DA2_P, DB1_ADC_DA1_P, DB1_ADC_DA0_P}, {DB1_ADC_DB6_P, DB1_ADC_DB5_P, DB1_ADC_DB4_P, DB1_ADC_DB3_P, DB1_ADC_DB2_P, DB1_ADC_DB1_P, DB1_ADC_DB0_P}}), @@ -470,7 +502,7 @@ module x300 {DB1_ADC_DB6_N, DB1_ADC_DB5_N, DB1_ADC_DB4_N, DB1_ADC_DB3_N, DB1_ADC_DB2_N, DB1_ADC_DB1_N, DB1_ADC_DB0_N}}), .out({rx1_i,rx1_q_inv})); assign rx1[31:0] = { rx1_i, 2'b00, ~rx1_q_inv, 2'b00 }; - + ///////////////////////////////////////////////////////////////////// // // DAC Interface for AD9146 @@ -1756,7 +1788,7 @@ module x300 /////////////////////////////////////////////////////////////////////////////////// // - // B250 Core + // X300 Core // /////////////////////////////////////////////////////////////////////////////////// x300_core x300_core @@ -1836,10 +1868,10 @@ module x300 .gmii_txd1(gmii_txd1), .gmii_tx_en1(gmii_tx_en1), .gmii_tx_er1(gmii_tx_er1), .gmii_rxd1(gmii_rxd1), .gmii_rx_dv1(gmii_rx_dv1), .gmii_rx_er1(gmii_rx_er1), `endif // !`ifdef + // Time + .pps(pps),.pps_select(pps_select), .pps_out_enb(pps_out_enb), // GPS Signals - .gps_pps(GPS_PPS_OUT), .ext_pps(EXT_PPS_IN), .gps_txd(GPS_SER_IN), .gps_rxd(GPS_SER_OUT), - .pps_out(EXT_PPS_OUT), // Debug UART .debug_rxd(debug_rxd), .debug_txd(debug_txd), // Misc. diff --git a/fpga/usrp3/top/x300/x300_core.v b/fpga/usrp3/top/x300/x300_core.v index c783d34ee..4c632b95d 100644 --- a/fpga/usrp3/top/x300/x300_core.v +++ b/fpga/usrp3/top/x300/x300_core.v @@ -104,9 +104,9 @@ module x300_core `endif // !`ifdef // Time - input gps_pps, - input ext_pps, - output reg pps_out, + input pps, + output [1:0] pps_select, + output pps_out_enb, output gps_txd, input gps_rxd, // Debug UART @@ -369,31 +369,20 @@ module x300_core ///////////////////////////////////////////////////////////////////////////////// - // PPS synchronization and generation logic + // PPS synchronization logic ///////////////////////////////////////////////////////////////////////////////// - //PPS input signals will be flopped in via the 10MHz reference clock. //Its assumed that the radio clock, which is derived from the 10MHz, //will be able to flop this captured PPS signal without metastability. //And that the relation of the radio clock to this ref clock will be //consistent enough across multiple units to use for this purpose. - reg [1:0] ext_pps_del, gps_pps_del; - always @(posedge ext_ref_clk) ext_pps_del[1:0] <= {ext_pps_del[0], ext_pps}; - always @(posedge ext_ref_clk) gps_pps_del[1:0] <= {gps_pps_del[0], gps_pps}; - - //Generate a PPS signal disciplined by the input reference PPS. - //The PPS signal is 25% duty cycle, and generated by the rising edge. - reg pps_int; - wire pps_out_enb, pps_select; - reg [31:0] pps_count; - wire pps_duty_high = (pps_count < 32'd2500000); - wire pps_edge = pps_select? (ext_pps_del == 2'b01) : (gps_pps_del == 2'b01); + reg [1:0] pps_del; + always @(posedge ext_ref_clk) pps_del[1:0] <= {pps_del[0], pps}; + + //PPS detection - toggle pps_detect on each PPS rising edge. + reg pps_detect; always @(posedge ext_ref_clk) begin - if (pps_edge) pps_count <= 32'd3; //delay = sampling + detection + flopping out - else if (pps_count == 32'd9999999) pps_count <= 32'b0; - else pps_count <= pps_count + 1'b1; - pps_out <= pps_duty_high? pps_out_enb : 1'b0; - pps_int <= pps_duty_high? 1'b1 : 1'b0; + if (pps_del == 2'b01) pps_detect <= ~pps_detect; end ///////////////////////////////////////////////////////////////////////////////// @@ -415,8 +404,8 @@ module x300_core .SFPP1_ModAbs(SFPP1_ModAbs),.SFPP1_TxFault(SFPP1_TxFault),.SFPP1_RxLOS(SFPP1_RxLOS), .SFPP1_RS0(SFPP1_RS0), .SFPP1_RS1(SFPP1_RS1), //clocky locky misc - .clock_status({LMK_Holdover, LMK_Lock, LMK_Status}), - .clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select, clock_ref_sel[1:0]}), + .clock_status({pps_detect, LMK_Holdover, LMK_Lock, LMK_Status}), + .clock_control({clock_misc_opt[1:0], pps_out_enb, pps_select[1:0], clock_ref_sel[1:0]}), // Eth0 .eth0_tx_tdata(eth0_tx_tdata), .eth0_tx_tuser(eth0_tx_tuser), .eth0_tx_tlast(eth0_tx_tlast), .eth0_tx_tvalid(eth0_tx_tvalid), .eth0_tx_tready(eth0_tx_tready), @@ -557,7 +546,7 @@ module x300_core .tx_tvalid_bo(r0_tx_tvalid_bo), .tx_tready_bo(r0_tx_tready_bo), .tx_tdata_bi(r0_tx_tdata_bi), .tx_tlast_bi(r0_tx_tlast_bi), .tx_tvalid_bi(r0_tx_tvalid_bi), .tx_tready_bi(r0_tx_tready_bi), - .pps(pps_int), .sync_dacs(sync_dacs_radio0) + .pps(pps_del[1]), .sync_dacs(sync_dacs_radio0) ); always @(posedge radio_clk) @@ -590,7 +579,7 @@ module x300_core .tx_tvalid_bo(r1_tx_tvalid_bo), .tx_tready_bo(r1_tx_tready_bo), .tx_tdata_bi(r1_tx_tdata_bi), .tx_tlast_bi(r1_tx_tlast_bi), .tx_tvalid_bi(r1_tx_tvalid_bi), .tx_tready_bi(r1_tx_tready_bi), - .pps(pps_int), .sync_dacs(sync_dacs_radio1) + .pps(pps_del[1]), .sync_dacs(sync_dacs_radio1) ); always @(posedge radio_clk) @@ -987,7 +976,7 @@ module x300_core // .debug() ); - + axi_dram_fifo #(.BASE('h2000000), .SIZE(24), @@ -1107,15 +1096,15 @@ module x300_core // Alternate smaller internal SRAM based FIFO's for Tx when DRAM not compiled into FPGA. // Short FIFO's added for ease of timing closure since large FIFO's spread all over die. // - wire [63:0] r0_tx_tdata_bos; wire r0_tx_tlast_bos, r0_tx_tvalid_bos, r0_tx_tready_bos; + wire [63:0] r0_tx_tdata_bos; wire r0_tx_tlast_bos, r0_tx_tvalid_bos, r0_tx_tready_bos; wire [63:0] r0_tx_tdata_0; wire r0_tx_tlast_0, r0_tx_tvalid_0, r0_tx_tready_0; - wire [63:0] r0_tx_tdata_0s; wire r0_tx_tlast_0s, r0_tx_tvalid_0s, r0_tx_tready_0s; + wire [63:0] r0_tx_tdata_0s; wire r0_tx_tlast_0s, r0_tx_tvalid_0s, r0_tx_tready_0s; wire [63:0] r0_tx_tdata_1; wire r0_tx_tlast_1, r0_tx_tvalid_1, r0_tx_tready_1; - wire [63:0] r0_tx_tdata_1s; wire r0_tx_tlast_1s, r0_tx_tvalid_1s, r0_tx_tready_1s; + wire [63:0] r0_tx_tdata_1s; wire r0_tx_tlast_1s, r0_tx_tvalid_1s, r0_tx_tready_1s; wire [63:0] r0_tx_tdata_2; wire r0_tx_tlast_2, r0_tx_tvalid_2, r0_tx_tready_2; wire [63:0] r0_tx_tdata_2s; wire r0_tx_tlast_2s, r0_tx_tvalid_2s, r0_tx_tready_2s; wire [63:0] r0_tx_tdata_bis; wire r0_tx_tlast_bis, r0_tx_tvalid_bis, r0_tx_tready_bis; - + axi_fifo_short #(.WIDTH(65)) tx_fifo0_bos ( .clk(bus_clk), .reset(bus_rst), .clear(1'b0), @@ -1137,7 +1126,7 @@ module x300_core .o_tdata({r0_tx_tlast_0s,r0_tx_tdata_0s}), .o_tvalid(r0_tx_tvalid_0s), .o_tready(r0_tx_tready_0s), .space(), .occupied() ); - + axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_1 (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), .i_tdata({r0_tx_tlast_0s,r0_tx_tdata_0s}), .i_tvalid(r0_tx_tvalid_0s), .i_tready(r0_tx_tready_0s), @@ -1151,13 +1140,13 @@ module x300_core .o_tdata({r0_tx_tlast_1s,r0_tx_tdata_1s}), .o_tvalid(r0_tx_tvalid_1s), .o_tready(r0_tx_tready_1s), .space(), .occupied() ); - + axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_2 (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), .i_tdata({r0_tx_tlast_1s,r0_tx_tdata_1s}), .i_tvalid(r0_tx_tvalid_1s), .i_tready(r0_tx_tready_1s), .o_tdata({r0_tx_tlast_2,r0_tx_tdata_2}), .o_tvalid(r0_tx_tvalid_2), .o_tready(r0_tx_tready_2), .space(), .occupied()); - + axi_fifo_short #(.WIDTH(65)) tx_fifo0_2s ( .clk(bus_clk), .reset(bus_rst), .clear(1'b0), @@ -1165,13 +1154,13 @@ module x300_core .o_tdata({r0_tx_tlast_2s,r0_tx_tdata_2s}), .o_tvalid(r0_tx_tvalid_2s), .o_tready(r0_tx_tready_2s), .space(), .occupied() ); - + axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_3 (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), .i_tdata({r0_tx_tlast_2s,r0_tx_tdata_2s}), .i_tvalid(r0_tx_tvalid_2s), .i_tready(r0_tx_tready_2s), .o_tdata({r0_tx_tlast_bis,r0_tx_tdata_bis}), .o_tvalid(r0_tx_tvalid_bis), .o_tready(r0_tx_tready_bis), .space(), .occupied()); - + axi_fifo_short #(.WIDTH(65)) tx_fifo0_bis ( .clk(bus_clk), .reset(bus_rst), .clear(1'b0), @@ -1180,15 +1169,15 @@ module x300_core .space(), .occupied() ); - wire [63:0] r1_tx_tdata_bos; wire r1_tx_tlast_bos, r1_tx_tvalid_bos, r1_tx_tready_bos; + wire [63:0] r1_tx_tdata_bos; wire r1_tx_tlast_bos, r1_tx_tvalid_bos, r1_tx_tready_bos; wire [63:0] r1_tx_tdata_0; wire r1_tx_tlast_0, r1_tx_tvalid_0, r1_tx_tready_0; - wire [63:0] r1_tx_tdata_0s; wire r1_tx_tlast_0s, r1_tx_tvalid_0s, r1_tx_tready_0s; + wire [63:0] r1_tx_tdata_0s; wire r1_tx_tlast_0s, r1_tx_tvalid_0s, r1_tx_tready_0s; wire [63:0] r1_tx_tdata_1; wire r1_tx_tlast_1, r1_tx_tvalid_1, r1_tx_tready_1; - wire [63:0] r1_tx_tdata_1s; wire r1_tx_tlast_1s, r1_tx_tvalid_1s, r1_tx_tready_1s; + wire [63:0] r1_tx_tdata_1s; wire r1_tx_tlast_1s, r1_tx_tvalid_1s, r1_tx_tready_1s; wire [63:0] r1_tx_tdata_2; wire r1_tx_tlast_2, r1_tx_tvalid_2, r1_tx_tready_2; wire [63:0] r1_tx_tdata_2s; wire r1_tx_tlast_2s, r1_tx_tvalid_2s, r1_tx_tready_2s; wire [63:0] r1_tx_tdata_bis; wire r1_tx_tlast_bis, r1_tx_tvalid_bis, r1_tx_tready_bis; - + axi_fifo_short #(.WIDTH(65)) tx_fifo1_bos ( .clk(bus_clk), .reset(bus_rst), .clear(1'b0), @@ -1210,7 +1199,7 @@ module x300_core .o_tdata({r1_tx_tlast_0s,r1_tx_tdata_0s}), .o_tvalid(r1_tx_tvalid_0s), .o_tready(r1_tx_tready_0s), .space(), .occupied() ); - + axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_1 (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), .i_tdata({r1_tx_tlast_0s,r1_tx_tdata_0s}), .i_tvalid(r1_tx_tvalid_0s), .i_tready(r1_tx_tready_0s), @@ -1224,13 +1213,13 @@ module x300_core .o_tdata({r1_tx_tlast_1s,r1_tx_tdata_1s}), .o_tvalid(r1_tx_tvalid_1s), .o_tready(r1_tx_tready_1s), .space(), .occupied() ); - + axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_2 (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), .i_tdata({r1_tx_tlast_1s,r1_tx_tdata_1s}), .i_tvalid(r1_tx_tvalid_1s), .i_tready(r1_tx_tready_1s), .o_tdata({r1_tx_tlast_2,r1_tx_tdata_2}), .o_tvalid(r1_tx_tvalid_2), .o_tready(r1_tx_tready_2), .space(), .occupied()); - + axi_fifo_short #(.WIDTH(65)) tx_fifo1_2s ( .clk(bus_clk), .reset(bus_rst), .clear(1'b0), @@ -1238,13 +1227,13 @@ module x300_core .o_tdata({r1_tx_tlast_2s,r1_tx_tdata_2s}), .o_tvalid(r1_tx_tvalid_2s), .o_tready(r1_tx_tready_2s), .space(), .occupied() ); - + axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo1_3 (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), .i_tdata({r1_tx_tlast_2s,r1_tx_tdata_2s}), .i_tvalid(r1_tx_tvalid_2s), .i_tready(r1_tx_tready_2s), .o_tdata({r1_tx_tlast_bis,r1_tx_tdata_bis}), .o_tvalid(r1_tx_tvalid_bis), .o_tready(r1_tx_tready_bis), .space(), .occupied()); - + axi_fifo_short #(.WIDTH(65)) tx_fifo1_bis ( .clk(bus_clk), .reset(bus_rst), .clear(1'b0), @@ -1254,7 +1243,7 @@ module x300_core ); - + `endif // `ifndef NO_DRAM_FIFOS // |