diff options
Diffstat (limited to 'fpga/usrp3/top/x300/timing.ucf')
| -rw-r--r-- | fpga/usrp3/top/x300/timing.ucf | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x300/timing.ucf b/fpga/usrp3/top/x300/timing.ucf new file mode 100644 index 000000000..a84a92a63 --- /dev/null +++ b/fpga/usrp3/top/x300/timing.ucf @@ -0,0 +1,36 @@ + +NET "FPGA_CLK_p" TNM_NET = "FPGA_CLK_p"; +TIMESPEC "TS_FPGA_CLK_p" = PERIOD "FPGA_CLK_p" 5000 ps HIGH 50 %; + +NET "FPGA_CLK_n" TNM_NET = "FPGA_CLK_n"; +TIMESPEC "TS_FPGA_CLK_n" = PERIOD "FPGA_CLK_n" 5000 ps HIGH 50 %; + +NET "FPGA_125MHz_CLK" TNM_NET = "FPGA_125MHz_CLK"; +TIMESPEC "TS_FPGA_125MHz_CLK" = PERIOD "FPGA_125MHz_CLK" 8000 ps HIGH 50 %; + +#NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P"; +#TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 8333 ps HIGH 50 %; + +#NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P"; +#TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 8333 ps HIGH 50 %; + +NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P"; +TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 5000 ps HIGH 50 %; +OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" RISING; +OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" FALLING; + +NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P"; +TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 5000 ps HIGH 50 %; +OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" RISING; +OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" FALLING; + +NET "bus_clk" TNM = bus_clk_grp; +NET "ioport2_clk" TNM = ioport2_clk_grp; +NET "rio40_clk" TNM = rio40_clk_grp; + +TIMESPEC TS_BUS_CLK_TO_IOPORT2_CLK_FALEPATH = FROM bus_clk_grp TO ioport2_clk_grp TIG; +TIMESPEC TS_IOPORT2_CLK_TO_BUS_CLK_FALEPATH = FROM ioport2_clk_grp TO bus_clk_grp TIG; + +TIMESPEC TS_IOPORT2_CLK_TO_RIO40_CLK_FALEPATH = FROM ioport2_clk_grp TO rio40_clk_grp TIG; +TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_clk_grp TIG; + |